diff options
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-designware.h | 29 |
1 files changed, 16 insertions, 13 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 070382869685..8ebfb06584d9 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h | |||
| @@ -11,6 +11,7 @@ | |||
| 11 | #ifndef _PCIE_DESIGNWARE_H | 11 | #ifndef _PCIE_DESIGNWARE_H |
| 12 | #define _PCIE_DESIGNWARE_H | 12 | #define _PCIE_DESIGNWARE_H |
| 13 | 13 | ||
| 14 | #include <linux/bitfield.h> | ||
| 14 | #include <linux/dma-mapping.h> | 15 | #include <linux/dma-mapping.h> |
| 15 | #include <linux/irq.h> | 16 | #include <linux/irq.h> |
| 16 | #include <linux/msi.h> | 17 | #include <linux/msi.h> |
| @@ -30,11 +31,12 @@ | |||
| 30 | 31 | ||
| 31 | /* Synopsys-specific PCIe configuration registers */ | 32 | /* Synopsys-specific PCIe configuration registers */ |
| 32 | #define PCIE_PORT_LINK_CONTROL 0x710 | 33 | #define PCIE_PORT_LINK_CONTROL 0x710 |
| 33 | #define PORT_LINK_MODE_MASK (0x3f << 16) | 34 | #define PORT_LINK_MODE_MASK GENMASK(21, 16) |
| 34 | #define PORT_LINK_MODE_1_LANES (0x1 << 16) | 35 | #define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n) |
| 35 | #define PORT_LINK_MODE_2_LANES (0x3 << 16) | 36 | #define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1) |
| 36 | #define PORT_LINK_MODE_4_LANES (0x7 << 16) | 37 | #define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3) |
| 37 | #define PORT_LINK_MODE_8_LANES (0xf << 16) | 38 | #define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7) |
| 39 | #define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf) | ||
| 38 | 40 | ||
| 39 | #define PCIE_PORT_DEBUG0 0x728 | 41 | #define PCIE_PORT_DEBUG0 0x728 |
| 40 | #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f | 42 | #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f |
| @@ -42,11 +44,12 @@ | |||
| 42 | 44 | ||
| 43 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C | 45 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C |
| 44 | #define PORT_LOGIC_SPEED_CHANGE BIT(17) | 46 | #define PORT_LOGIC_SPEED_CHANGE BIT(17) |
| 45 | #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) | 47 | #define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8) |
| 46 | #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) | 48 | #define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n) |
| 47 | #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) | 49 | #define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1) |
| 48 | #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) | 50 | #define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2) |
| 49 | #define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8) | 51 | #define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4) |
| 52 | #define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8) | ||
| 50 | 53 | ||
| 51 | #define PCIE_MSI_ADDR_LO 0x820 | 54 | #define PCIE_MSI_ADDR_LO 0x820 |
| 52 | #define PCIE_MSI_ADDR_HI 0x824 | 55 | #define PCIE_MSI_ADDR_HI 0x824 |
| @@ -72,9 +75,9 @@ | |||
| 72 | #define PCIE_ATU_UPPER_BASE 0x910 | 75 | #define PCIE_ATU_UPPER_BASE 0x910 |
| 73 | #define PCIE_ATU_LIMIT 0x914 | 76 | #define PCIE_ATU_LIMIT 0x914 |
| 74 | #define PCIE_ATU_LOWER_TARGET 0x918 | 77 | #define PCIE_ATU_LOWER_TARGET 0x918 |
| 75 | #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) | 78 | #define PCIE_ATU_BUS(x) FIELD_PREP(GENMASK(31, 24), x) |
| 76 | #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) | 79 | #define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x) |
| 77 | #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) | 80 | #define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x) |
| 78 | #define PCIE_ATU_UPPER_TARGET 0x91C | 81 | #define PCIE_ATU_UPPER_TARGET 0x91C |
| 79 | 82 | ||
| 80 | #define PCIE_MISC_CONTROL_1_OFF 0x8BC | 83 | #define PCIE_MISC_CONTROL_1_OFF 0x8BC |