162 files changed, 3920 insertions, 2591 deletions

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index bda151788f3f..34b56a8f8480 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
 #
 # PCI configuration
 #
@@ -125,6 +126,7 @@ config PCI_PASID
 
 config PCI_LABEL
         def_bool y if (DMI || ACPI)
+        depends on PCI
         select NLS
 
 config PCI_HYPERV
@@ -135,6 +137,7 @@ config PCI_HYPERV
           PCI devices from a PCI backend to support PCI driver domains.
 
 source "drivers/pci/hotplug/Kconfig"
+source "drivers/pci/cadence/Kconfig"
 source "drivers/pci/dwc/Kconfig"
 source "drivers/pci/host/Kconfig"
 source "drivers/pci/endpoint/Kconfig"
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index c7819b973df7..941970936840 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -3,12 +3,15 @@
 # Makefile for the PCI bus specific drivers.
 #
 
-obj-y           += access.o bus.o probe.o host-bridge.o remove.o pci.o \
+obj-$(CONFIG_PCI)       += access.o bus.o probe.o host-bridge.o remove.o pci.o \
                         pci-driver.o search.o pci-sysfs.o rom.o setup-res.o \
                         irq.o vpd.o setup-bus.o vc.o mmap.o setup-irq.o
 
+ifdef CONFIG_PCI
 obj-$(CONFIG_PROC_FS) += proc.o
 obj-$(CONFIG_SYSFS) += slot.o
+obj-$(CONFIG_OF) += of.o
+endif
 
 obj-$(CONFIG_PCI_QUIRKS) += quirks.o
 
@@ -44,10 +47,15 @@ obj-$(CONFIG_PCI_ECAM) += ecam.o
 
 obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen-pcifront.o
 
-obj-$(CONFIG_OF) += of.o
-
 ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
 
 # PCI host controller drivers
 obj-y += host/
 obj-y += switch/
+
+obj-$(CONFIG_PCI_ENDPOINT)      += endpoint/
+
+# Endpoint library must be initialized before its users
+obj-$(CONFIG_PCIE_CADENCE)      += cadence/
+# pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
+obj-y                           += dwc/
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 913d6722ece9..5e9a9822d9d4 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 #include <linux/delay.h>
 #include <linux/pci.h>
 #include <linux/module.h>
@@ -333,8 +334,7 @@ static size_t pci_vpd_size(struct pci_dev *dev, size_t old_size)
                             (tag == PCI_VPD_LTIN_RW_DATA)) {
                                 if (pci_read_vpd(dev, off+1, 2,
                                                  &header[1]) != 2) {
-                                        dev_warn(&dev->dev,
-                                                 "invalid large VPD tag %02x size at offset %zu",
+                                        pci_warn(dev, "invalid large VPD tag %02x size at offset %zu",
                                                  tag, off + 1);
                                         return 0;
                                 }
@@ -354,8 +354,7 @@ static size_t pci_vpd_size(struct pci_dev *dev, size_t old_size)
                 if ((tag != PCI_VPD_LTIN_ID_STRING) &&
                     (tag != PCI_VPD_LTIN_RO_DATA) &&
                     (tag != PCI_VPD_LTIN_RW_DATA)) {
-                        dev_warn(&dev->dev,
-                                 "invalid %s VPD tag %02x at offset %zu",
+                        pci_warn(dev, "invalid %s VPD tag %02x at offset %zu",
                                  (header[0] & PCI_VPD_LRDT) ? "large" : "short",
                                  tag, off);
                         return 0;
@@ -402,7 +401,7 @@ static int pci_vpd_wait(struct pci_dev *dev)
                         max_sleep *= 2;
         }
 
-        dev_warn(&dev->dev, "VPD access failed.  This is likely a firmware bug on this device.  Contact the card vendor for a firmware update\n");
+        pci_warn(dev, "VPD access failed.  This is likely a firmware bug on this device.  Contact the card vendor for a firmware update\n");
         return -ETIMEDOUT;
 }
 
diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c
index ad8ddbbbf245..6ad80a1fd5a7 100644
--- a/drivers/pci/ats.c
+++ b/drivers/pci/ats.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * drivers/pci/ats.c
  *
diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c
index bc56cf19afd3..737d1c52f002 100644
--- a/drivers/pci/bus.c
+++ b/drivers/pci/bus.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  *      drivers/pci/bus.c
  *
@@ -289,7 +290,7 @@ bool pci_bus_clip_resource(struct pci_dev *dev, int idx)
                 res->end = end;
                 res->flags &= ~IORESOURCE_UNSET;
                 orig_res.flags &= ~IORESOURCE_UNSET;
-                dev_printk(KERN_DEBUG, &dev->dev, "%pR clipped to %pR\n",
+                pci_printk(KERN_DEBUG, dev, "%pR clipped to %pR\n",
                                  &orig_res, res);
 
                 return true;
@@ -325,7 +326,7 @@ void pci_bus_add_device(struct pci_dev *dev)
         dev->match_driver = true;
         retval = device_attach(&dev->dev);
         if (retval < 0 && retval != -EPROBE_DEFER) {
-                dev_warn(&dev->dev, "device attach failed (%d)\n", retval);
+                pci_warn(dev, "device attach failed (%d)\n", retval);
                 pci_proc_detach_device(dev);
                 pci_remove_sysfs_dev_files(dev);
                 return;
diff --git a/drivers/pci/cadence/Kconfig b/drivers/pci/cadence/Kconfig
new file mode 100644
index 000000000000..e6824cb56c16
--- /dev/null
+++ b/drivers/pci/cadence/Kconfig
@@ -0,0 +1,27 @@
+menu "Cadence PCIe controllers support"
+
+config PCIE_CADENCE
+        bool
+
+config PCIE_CADENCE_HOST
+        bool "Cadence PCIe host controller"
+        depends on OF
+        depends on PCI
+        select IRQ_DOMAIN
+        select PCIE_CADENCE
+        help
+          Say Y here if you want to support the Cadence PCIe controller in host
+          mode. This PCIe controller may be embedded into many different vendors
+          SoCs.
+
+config PCIE_CADENCE_EP
+        bool "Cadence PCIe endpoint controller"
+        depends on OF
+        depends on PCI_ENDPOINT
+        select PCIE_CADENCE
+        help
+          Say Y here if you want to support the Cadence PCIe  controller in
+          endpoint mode. This PCIe controller may be embedded into many
+          different vendors SoCs.
+
+endmenu
diff --git a/drivers/pci/cadence/Makefile b/drivers/pci/cadence/Makefile
new file mode 100644
index 000000000000..719392b97998
--- /dev/null
+++ b/drivers/pci/cadence/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o
+obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o
+obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o
diff --git a/drivers/pci/cadence/pcie-cadence-ep.c b/drivers/pci/cadence/pcie-cadence-ep.c
new file mode 100644
index 000000000000..3c3a97743453
--- /dev/null
+++ b/drivers/pci/cadence/pcie-cadence-ep.c
@@ -0,0 +1,542 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017 Cadence
+// Cadence PCIe endpoint controller driver.
+// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
+
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/pci-epc.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/sizes.h>
+
+#include "pcie-cadence.h"
+
+#define CDNS_PCIE_EP_MIN_APERTURE               128     /* 128 bytes */
+#define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE          0x1
+#define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY        0x3
+
+/**
+ * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver
+ * @pcie: Cadence PCIe controller
+ * @max_regions: maximum number of regions supported by hardware
+ * @ob_region_map: bitmask of mapped outbound regions
+ * @ob_addr: base addresses in the AXI bus where the outbound regions start
+ * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ
+ *                 dedicated outbound regions is mapped.
+ * @irq_cpu_addr: base address in the CPU space where a write access triggers
+ *                the sending of a memory write (MSI) / normal message (legacy
+ *                IRQ) TLP through the PCIe bus.
+ * @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ
+ *                dedicated outbound region.
+ * @irq_pci_fn: the latest PCI function that has updated the mapping of
+ *              the MSI/legacy IRQ dedicated outbound region.
+ * @irq_pending: bitmask of asserted legacy IRQs.
+ */
+struct cdns_pcie_ep {
+        struct cdns_pcie                pcie;
+        u32                             max_regions;
+        unsigned long                   ob_region_map;
+        phys_addr_t                     *ob_addr;
+        phys_addr_t                     irq_phys_addr;
+        void __iomem                    *irq_cpu_addr;
+        u64                             irq_pci_addr;
+        u8                              irq_pci_fn;
+        u8                              irq_pending;
+};
+
+static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn,
+                                     struct pci_epf_header *hdr)
+{
+        struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+        struct cdns_pcie *pcie = &ep->pcie;
+
+        cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
+        cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
+        cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code);
+        cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
+                               hdr->subclass_code | hdr->baseclass_code << 8);
+        cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
+                               hdr->cache_line_size);
+        cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id);
+        cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin);
+
+        /*
+         * Vendor ID can only be modified from function 0, all other functions
+         * use the same vendor ID as function 0.
+         */
+        if (fn == 0) {
+                /* Update the vendor IDs. */
+                u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) |
+                         CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);
+
+                cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
+        }
+
+        return 0;
+}
+
+static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, enum pci_barno bar,
+                                dma_addr_t bar_phys, size_t size, int flags)
+{
+        struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+        struct cdns_pcie *pcie = &ep->pcie;
+        u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
+        u64 sz;
+
+        /* BAR size is 2^(aperture + 7) */
+        sz = max_t(size_t, size, CDNS_PCIE_EP_MIN_APERTURE);
+        /*
+         * roundup_pow_of_two() returns an unsigned long, which is not suited
+         * for 64bit values.
+         */
+        sz = 1ULL << fls64(sz - 1);
+        aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
+
+        if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
+                ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS;
+        } else {
+                bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
+                bool is_64bits = sz > SZ_2G;
+
+                if (is_64bits && (bar & 1))
+                        return -EINVAL;
+
+                if (is_64bits && is_prefetch)
+                        ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
+                else if (is_prefetch)
+                        ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
+                else if (is_64bits)
+                        ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
+                else
+                        ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
+        }
+
+        addr0 = lower_32_bits(bar_phys);
+        addr1 = upper_32_bits(bar_phys);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
+                         addr0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
+                         addr1);
+
+        if (bar < BAR_4) {
+                reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
+                b = bar;
+        } else {
+                reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
+                b = bar - BAR_4;
+        }
+
+        cfg = cdns_pcie_readl(pcie, reg);
+        cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
+                 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
+        cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
+                CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
+        cdns_pcie_writel(pcie, reg, cfg);
+
+        return 0;
+}
+
+static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn,
+                                   enum pci_barno bar)
+{
+        struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+        struct cdns_pcie *pcie = &ep->pcie;
+        u32 reg, cfg, b, ctrl;
+
+        if (bar < BAR_4) {
+                reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
+                b = bar;
+        } else {
+                reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
+                b = bar - BAR_4;
+        }
+
+        ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
+        cfg = cdns_pcie_readl(pcie, reg);
+        cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
+                 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
+        cfg |= CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
+        cdns_pcie_writel(pcie, reg, cfg);
+
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0);
+}
+
+static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr,
+                                 u64 pci_addr, size_t size)
+{
+        struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+        struct cdns_pcie *pcie = &ep->pcie;
+        u32 r;
+
+        r = find_first_zero_bit(&ep->ob_region_map,
+                                sizeof(ep->ob_region_map) * BITS_PER_LONG);
+        if (r >= ep->max_regions - 1) {
+                dev_err(&epc->dev, "no free outbound region\n");
+                return -EINVAL;
+        }
+
+        cdns_pcie_set_outbound_region(pcie, fn, r, false, addr, pci_addr, size);
+
+        set_bit(r, &ep->ob_region_map);
+        ep->ob_addr[r] = addr;
+
+        return 0;
+}
+
+static void cdns_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn,
+                                    phys_addr_t addr)
+{
+        struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+        struct cdns_pcie *pcie = &ep->pcie;
+        u32 r;
+
+        for (r = 0; r < ep->max_regions - 1; r++)
+                if (ep->ob_addr[r] == addr)
+                        break;
+
+        if (r == ep->max_regions - 1)
+                return;
+
+        cdns_pcie_reset_outbound_region(pcie, r);
+
+        ep->ob_addr[r] = 0;
+        clear_bit(r, &ep->ob_region_map);
+}
+
+static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 mmc)
+{
+        struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+        struct cdns_pcie *pcie = &ep->pcie;
+        u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
+        u16 flags;
+
+        /*
+         * Set the Multiple Message Capable bitfield into the Message Control
+         * register.
+         */
+        flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
+        flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1);
+        flags |= PCI_MSI_FLAGS_64BIT;
+        flags &= ~PCI_MSI_FLAGS_MASKBIT;
+        cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags);
+
+        return 0;
+}
+
+static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn)
+{
+        struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+        struct cdns_pcie *pcie = &ep->pcie;
+        u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
+        u16 flags, mmc, mme;
+
+        /* Validate that the MSI feature is actually enabled. */
+        flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
+        if (!(flags & PCI_MSI_FLAGS_ENABLE))
+                return -EINVAL;
+
+        /*
+         * Get the Multiple Message Enable bitfield from the Message Control
+         * register.
+         */
+        mmc = (flags & PCI_MSI_FLAGS_QMASK) >> 1;
+        mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
+
+        return mme;
+}
+
+static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn,
+                                     u8 intx, bool is_asserted)
+{
+        struct cdns_pcie *pcie = &ep->pcie;
+        u32 r = ep->max_regions - 1;
+        u32 offset;
+        u16 status;
+        u8 msg_code;
+
+        intx &= 3;
+
+        /* Set the outbound region if needed. */
+        if (unlikely(ep->irq_pci_addr != CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY ||
+                     ep->irq_pci_fn != fn)) {
+                /* Last region was reserved for IRQ writes. */
+                cdns_pcie_set_outbound_region_for_normal_msg(pcie, fn, r,
+                                                             ep->irq_phys_addr);
+                ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY;
+                ep->irq_pci_fn = fn;
+        }
+
+        if (is_asserted) {
+                ep->irq_pending |= BIT(intx);
+                msg_code = MSG_CODE_ASSERT_INTA + intx;
+        } else {
+                ep->irq_pending &= ~BIT(intx);
+                msg_code = MSG_CODE_DEASSERT_INTA + intx;
+        }
+
+        status = cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS);
+        if (((status & PCI_STATUS_INTERRUPT) != 0) ^ (ep->irq_pending != 0)) {
+                status ^= PCI_STATUS_INTERRUPT;
+                cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status);
+        }
+
+        offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) |
+                 CDNS_PCIE_NORMAL_MSG_CODE(msg_code) |
+                 CDNS_PCIE_MSG_NO_DATA;
+        writel(0, ep->irq_cpu_addr + offset);
+}
+
+static int cdns_pcie_ep_send_legacy_irq(struct cdns_pcie_ep *ep, u8 fn, u8 intx)
+{
+        u16 cmd;
+
+        cmd = cdns_pcie_ep_fn_readw(&ep->pcie, fn, PCI_COMMAND);
+        if (cmd & PCI_COMMAND_INTX_DISABLE)
+                return -EINVAL;
+
+        cdns_pcie_ep_assert_intx(ep, fn, intx, true);
+        /*
+         * The mdelay() value was taken from dra7xx_pcie_raise_legacy_irq()
+         * from drivers/pci/dwc/pci-dra7xx.c
+         */
+        mdelay(1);
+        cdns_pcie_ep_assert_intx(ep, fn, intx, false);
+        return 0;
+}
+
+static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
+                                     u8 interrupt_num)
+{
+        struct cdns_pcie *pcie = &ep->pcie;
+        u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
+        u16 flags, mme, data, data_mask;
+        u8 msi_count;
+        u64 pci_addr, pci_addr_mask = 0xff;
+
+        /* Check whether the MSI feature has been enabled by the PCI host. */
+        flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
+        if (!(flags & PCI_MSI_FLAGS_ENABLE))
+                return -EINVAL;
+
+        /* Get the number of enabled MSIs */
+        mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
+        msi_count = 1 << mme;
+        if (!interrupt_num || interrupt_num > msi_count)
+                return -EINVAL;
+
+        /* Compute the data value to be written. */
+        data_mask = msi_count - 1;
+        data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64);
+        data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask);
+
+        /* Get the PCI address where to write the data into. */
+        pci_addr = cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI);
+        pci_addr <<= 32;
+        pci_addr |= cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO);
+        pci_addr &= GENMASK_ULL(63, 2);
+
+        /* Set the outbound region if needed. */
+        if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) ||
+                     ep->irq_pci_fn != fn)) {
+                /* Last region was reserved for IRQ writes. */
+                cdns_pcie_set_outbound_region(pcie, fn, ep->max_regions - 1,
+                                              false,
+                                              ep->irq_phys_addr,
+                                              pci_addr & ~pci_addr_mask,
+                                              pci_addr_mask + 1);
+                ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
+                ep->irq_pci_fn = fn;
+        }
+        writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
+
+        return 0;
+}
+
+static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
+                                  enum pci_epc_irq_type type, u8 interrupt_num)
+{
+        struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+
+        switch (type) {
+        case PCI_EPC_IRQ_LEGACY:
+                return cdns_pcie_ep_send_legacy_irq(ep, fn, 0);
+
+        case PCI_EPC_IRQ_MSI:
+                return cdns_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
+
+        default:
+                break;
+        }
+
+        return -EINVAL;
+}
+
+static int cdns_pcie_ep_start(struct pci_epc *epc)
+{
+        struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+        struct cdns_pcie *pcie = &ep->pcie;
+        struct pci_epf *epf;
+        u32 cfg;
+
+        /*
+         * BIT(0) is hardwired to 1, hence function 0 is always enabled
+         * and can't be disabled anyway.
+         */
+        cfg = BIT(0);
+        list_for_each_entry(epf, &epc->pci_epf, list)
+                cfg |= BIT(epf->func_no);
+        cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg);
+
+        /*
+         * The PCIe links are automatically established by the controller
+         * once for all at powerup: the software can neither start nor stop
+         * those links later at runtime.
+         *
+         * Then we only have to notify the EP core that our links are already
+         * established. However we don't call directly pci_epc_linkup() because
+         * we've already locked the epc->lock.
+         */
+        list_for_each_entry(epf, &epc->pci_epf, list)
+                pci_epf_linkup(epf);
+
+        return 0;
+}
+
+static const struct pci_epc_ops cdns_pcie_epc_ops = {
+        .write_header   = cdns_pcie_ep_write_header,
+        .set_bar        = cdns_pcie_ep_set_bar,
+        .clear_bar      = cdns_pcie_ep_clear_bar,
+        .map_addr       = cdns_pcie_ep_map_addr,
+        .unmap_addr     = cdns_pcie_ep_unmap_addr,
+        .set_msi        = cdns_pcie_ep_set_msi,
+        .get_msi        = cdns_pcie_ep_get_msi,
+        .raise_irq      = cdns_pcie_ep_raise_irq,
+        .start          = cdns_pcie_ep_start,
+};
+
+static const struct of_device_id cdns_pcie_ep_of_match[] = {
+        { .compatible = "cdns,cdns-pcie-ep" },
+
+        { },
+};
+
+static int cdns_pcie_ep_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct device_node *np = dev->of_node;
+        struct cdns_pcie_ep *ep;
+        struct cdns_pcie *pcie;
+        struct pci_epc *epc;
+        struct resource *res;
+        int ret;
+
+        ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
+        if (!ep)
+                return -ENOMEM;
+
+        pcie = &ep->pcie;
+        pcie->is_rc = false;
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
+        pcie->reg_base = devm_ioremap_resource(dev, res);
+        if (IS_ERR(pcie->reg_base)) {
+                dev_err(dev, "missing \"reg\"\n");
+                return PTR_ERR(pcie->reg_base);
+        }
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
+        if (!res) {
+                dev_err(dev, "missing \"mem\"\n");
+                return -EINVAL;
+        }
+        pcie->mem_res = res;
+
+        ret = of_property_read_u32(np, "cdns,max-outbound-regions",
+                                   &ep->max_regions);
+        if (ret < 0) {
+                dev_err(dev, "missing \"cdns,max-outbound-regions\"\n");
+                return ret;
+        }
+        ep->ob_addr = devm_kzalloc(dev, ep->max_regions * sizeof(*ep->ob_addr),
+                                   GFP_KERNEL);
+        if (!ep->ob_addr)
+                return -ENOMEM;
+
+        pm_runtime_enable(dev);
+        ret = pm_runtime_get_sync(dev);
+        if (ret < 0) {
+                dev_err(dev, "pm_runtime_get_sync() failed\n");
+                goto err_get_sync;
+        }
+
+        /* Disable all but function 0 (anyway BIT(0) is hardwired to 1). */
+        cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, BIT(0));
+
+        epc = devm_pci_epc_create(dev, &cdns_pcie_epc_ops);
+        if (IS_ERR(epc)) {
+                dev_err(dev, "failed to create epc device\n");
+                ret = PTR_ERR(epc);
+                goto err_init;
+        }
+
+        epc_set_drvdata(epc, ep);
+
+        if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0)
+                epc->max_functions = 1;
+
+        ret = pci_epc_mem_init(epc, pcie->mem_res->start,
+                               resource_size(pcie->mem_res));
+        if (ret < 0) {
+                dev_err(dev, "failed to initialize the memory space\n");
+                goto err_init;
+        }
+
+        ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
+                                                  SZ_128K);
+        if (!ep->irq_cpu_addr) {
+                dev_err(dev, "failed to reserve memory space for MSI\n");
+                ret = -ENOMEM;
+                goto free_epc_mem;
+        }
+        ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE;
+
+        return 0;
+
+ free_epc_mem:
+        pci_epc_mem_exit(epc);
+
+ err_init:
+        pm_runtime_put_sync(dev);
+
+ err_get_sync:
+        pm_runtime_disable(dev);
+
+        return ret;
+}
+
+static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        int ret;
+
+        ret = pm_runtime_put_sync(dev);
+        if (ret < 0)
+                dev_dbg(dev, "pm_runtime_put_sync failed\n");
+
+        pm_runtime_disable(dev);
+
+        /* The PCIe controller can't be disabled. */
+}
+
+static struct platform_driver cdns_pcie_ep_driver = {
+        .driver = {
+                .name = "cdns-pcie-ep",
+                .of_match_table = cdns_pcie_ep_of_match,
+        },
+        .probe = cdns_pcie_ep_probe,
+        .shutdown = cdns_pcie_ep_shutdown,
+};
+builtin_platform_driver(cdns_pcie_ep_driver);
diff --git a/drivers/pci/cadence/pcie-cadence-host.c b/drivers/pci/cadence/pcie-cadence-host.c
new file mode 100644
index 000000000000..a4ebbd37b553
--- /dev/null
+++ b/drivers/pci/cadence/pcie-cadence-host.c
@@ -0,0 +1,336 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017 Cadence
+// Cadence PCIe host controller driver.
+// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
+
+#include <linux/kernel.h>
+#include <linux/of_address.h>
+#include <linux/of_pci.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include "pcie-cadence.h"
+
+/**
+ * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
+ * @pcie: Cadence PCIe controller
+ * @dev: pointer to PCIe device
+ * @cfg_res: start/end offsets in the physical system memory to map PCI
+ *           configuration space accesses
+ * @bus_range: first/last buses behind the PCIe host controller
+ * @cfg_base: IO mapped window to access the PCI configuration space of a
+ *            single function at a time
+ * @max_regions: maximum number of regions supported by the hardware
+ * @no_bar_nbits: Number of bits to keep for inbound (PCIe -> CPU) address
+ *                translation (nbits sets into the "no BAR match" register)
+ * @vendor_id: PCI vendor ID
+ * @device_id: PCI device ID
+ */
+struct cdns_pcie_rc {
+        struct cdns_pcie        pcie;
+        struct device           *dev;
+        struct resource         *cfg_res;
+        struct resource         *bus_range;
+        void __iomem            *cfg_base;
+        u32                     max_regions;
+        u32                     no_bar_nbits;
+        u16                     vendor_id;
+        u16                     device_id;
+};
+
+static void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
+                                      int where)
+{
+        struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
+        struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge);
+        struct cdns_pcie *pcie = &rc->pcie;
+        unsigned int busn = bus->number;
+        u32 addr0, desc0;
+
+        if (busn == rc->bus_range->start) {
+                /*
+                 * Only the root port (devfn == 0) is connected to this bus.
+                 * All other PCI devices are behind some bridge hence on another
+                 * bus.
+                 */
+                if (devfn)
+                        return NULL;
+
+                return pcie->reg_base + (where & 0xfff);
+        }
+
+        /* Update Output registers for AXI region 0. */
+        addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
+                CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) |
+                CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(busn);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(0), addr0);
+
+        /* Configuration Type 0 or Type 1 access. */
+        desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
+                CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
+        /*
+         * The bus number was already set once for all in desc1 by
+         * cdns_pcie_host_init_address_translation().
+         */
+        if (busn == rc->bus_range->start + 1)
+                desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0;
+        else
+                desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1;
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(0), desc0);
+
+        return rc->cfg_base + (where & 0xfff);
+}
+
+static struct pci_ops cdns_pcie_host_ops = {
+        .map_bus        = cdns_pci_map_bus,
+        .read           = pci_generic_config_read,
+        .write          = pci_generic_config_write,
+};
+
+static const struct of_device_id cdns_pcie_host_of_match[] = {
+        { .compatible = "cdns,cdns-pcie-host" },
+
+        { },
+};
+
+static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
+{
+        struct cdns_pcie *pcie = &rc->pcie;
+        u32 value, ctrl;
+
+        /*
+         * Set the root complex BAR configuration register:
+         * - disable both BAR0 and BAR1.
+         * - enable Prefetchable Memory Base and Limit registers in type 1
+         *   config space (64 bits).
+         * - enable IO Base and Limit registers in type 1 config
+         *   space (32 bits).
+         */
+        ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
+        value = CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) |
+                CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) |
+                CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE |
+                CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS |
+                CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE |
+                CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS;
+        cdns_pcie_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value);
+
+        /* Set root port configuration space */
+        if (rc->vendor_id != 0xffff)
+                cdns_pcie_rp_writew(pcie, PCI_VENDOR_ID, rc->vendor_id);
+        if (rc->device_id != 0xffff)
+                cdns_pcie_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id);
+
+        cdns_pcie_rp_writeb(pcie, PCI_CLASS_REVISION, 0);
+        cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0);
+        cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
+
+        return 0;
+}
+
+static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
+{
+        struct cdns_pcie *pcie = &rc->pcie;
+        struct resource *cfg_res = rc->cfg_res;
+        struct resource *mem_res = pcie->mem_res;
+        struct resource *bus_range = rc->bus_range;
+        struct device *dev = rc->dev;
+        struct device_node *np = dev->of_node;
+        struct of_pci_range_parser parser;
+        struct of_pci_range range;
+        u32 addr0, addr1, desc1;
+        u64 cpu_addr;
+        int r, err;
+
+        /*
+         * Reserve region 0 for PCI configure space accesses:
+         * OB_REGION_PCI_ADDR0 and OB_REGION_DESC0 are updated dynamically by
+         * cdns_pci_map_bus(), other region registers are set here once for all.
+         */
+        addr1 = 0; /* Should be programmed to zero. */
+        desc1 = CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus_range->start);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1);
+
+        cpu_addr = cfg_res->start - mem_res->start;
+        addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) |
+                (lower_32_bits(cpu_addr) & GENMASK(31, 8));
+        addr1 = upper_32_bits(cpu_addr);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(0), addr0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(0), addr1);
+
+        err = of_pci_range_parser_init(&parser, np);
+        if (err)
+                return err;
+
+        r = 1;
+        for_each_of_pci_range(&parser, &range) {
+                bool is_io;
+
+                if (r >= rc->max_regions)
+                        break;
+
+                if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM)
+                        is_io = false;
+                else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO)
+                        is_io = true;
+                else
+                        continue;
+
+                cdns_pcie_set_outbound_region(pcie, 0, r, is_io,
+                                              range.cpu_addr,
+                                              range.pci_addr,
+                                              range.size);
+                r++;
+        }
+
+        /*
+         * Set Root Port no BAR match Inbound Translation registers:
+         * needed for MSI and DMA.
+         * Root Port BAR0 and BAR1 are disabled, hence no need to set their
+         * inbound translation registers.
+         */
+        addr0 = CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(rc->no_bar_nbits);
+        addr1 = 0;
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR0(RP_NO_BAR), addr0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR1(RP_NO_BAR), addr1);
+
+        return 0;
+}
+
+static int cdns_pcie_host_init(struct device *dev,
+                               struct list_head *resources,
+                               struct cdns_pcie_rc *rc)
+{
+        struct resource *bus_range = NULL;
+        int err;
+
+        /* Parse our PCI ranges and request their resources */
+        err = pci_parse_request_of_pci_ranges(dev, resources, &bus_range);
+        if (err)
+                return err;
+
+        rc->bus_range = bus_range;
+        rc->pcie.bus = bus_range->start;
+
+        err = cdns_pcie_host_init_root_port(rc);
+        if (err)
+                goto err_out;
+
+        err = cdns_pcie_host_init_address_translation(rc);
+        if (err)
+                goto err_out;
+
+        return 0;
+
+ err_out:
+        pci_free_resource_list(resources);
+        return err;
+}
+
+static int cdns_pcie_host_probe(struct platform_device *pdev)
+{
+        const char *type;
+        struct device *dev = &pdev->dev;
+        struct device_node *np = dev->of_node;
+        struct pci_host_bridge *bridge;
+        struct list_head resources;
+        struct cdns_pcie_rc *rc;
+        struct cdns_pcie *pcie;
+        struct resource *res;
+        int ret;
+
+        bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
+        if (!bridge)
+                return -ENOMEM;
+
+        rc = pci_host_bridge_priv(bridge);
+        rc->dev = dev;
+
+        pcie = &rc->pcie;
+        pcie->is_rc = true;
+
+        rc->max_regions = 32;
+        of_property_read_u32(np, "cdns,max-outbound-regions", &rc->max_regions);
+
+        rc->no_bar_nbits = 32;
+        of_property_read_u32(np, "cdns,no-bar-match-nbits", &rc->no_bar_nbits);
+
+        rc->vendor_id = 0xffff;
+        of_property_read_u16(np, "vendor-id", &rc->vendor_id);
+
+        rc->device_id = 0xffff;
+        of_property_read_u16(np, "device-id", &rc->device_id);
+
+        type = of_get_property(np, "device_type", NULL);
+        if (!type || strcmp(type, "pci")) {
+                dev_err(dev, "invalid \"device_type\" %s\n", type);
+                return -EINVAL;
+        }
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
+        pcie->reg_base = devm_ioremap_resource(dev, res);
+        if (IS_ERR(pcie->reg_base)) {
+                dev_err(dev, "missing \"reg\"\n");
+                return PTR_ERR(pcie->reg_base);
+        }
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
+        rc->cfg_base = devm_pci_remap_cfg_resource(dev, res);
+        if (IS_ERR(rc->cfg_base)) {
+                dev_err(dev, "missing \"cfg\"\n");
+                return PTR_ERR(rc->cfg_base);
+        }
+        rc->cfg_res = res;
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
+        if (!res) {
+                dev_err(dev, "missing \"mem\"\n");
+                return -EINVAL;
+        }
+        pcie->mem_res = res;
+
+        pm_runtime_enable(dev);
+        ret = pm_runtime_get_sync(dev);
+        if (ret < 0) {
+                dev_err(dev, "pm_runtime_get_sync() failed\n");
+                goto err_get_sync;
+        }
+
+        ret = cdns_pcie_host_init(dev, &resources, rc);
+        if (ret)
+                goto err_init;
+
+        list_splice_init(&resources, &bridge->windows);
+        bridge->dev.parent = dev;
+        bridge->busnr = pcie->bus;
+        bridge->ops = &cdns_pcie_host_ops;
+        bridge->map_irq = of_irq_parse_and_map_pci;
+        bridge->swizzle_irq = pci_common_swizzle;
+
+        ret = pci_host_probe(bridge);
+        if (ret < 0)
+                goto err_host_probe;
+
+        return 0;
+
+ err_host_probe:
+        pci_free_resource_list(&resources);
+
+ err_init:
+        pm_runtime_put_sync(dev);
+
+ err_get_sync:
+        pm_runtime_disable(dev);
+
+        return ret;
+}
+
+static struct platform_driver cdns_pcie_host_driver = {
+        .driver = {
+                .name = "cdns-pcie-host",
+                .of_match_table = cdns_pcie_host_of_match,
+        },
+        .probe = cdns_pcie_host_probe,
+};
+builtin_platform_driver(cdns_pcie_host_driver);
diff --git a/drivers/pci/cadence/pcie-cadence.c b/drivers/pci/cadence/pcie-cadence.c
new file mode 100644
index 000000000000..138d113eb45d
--- /dev/null
+++ b/drivers/pci/cadence/pcie-cadence.c
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017 Cadence
+// Cadence PCIe controller driver.
+// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
+
+#include <linux/kernel.h>
+
+#include "pcie-cadence.h"
+
+void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 fn,
+                                   u32 r, bool is_io,
+                                   u64 cpu_addr, u64 pci_addr, size_t size)
+{
+        /*
+         * roundup_pow_of_two() returns an unsigned long, which is not suited
+         * for 64bit values.
+         */
+        u64 sz = 1ULL << fls64(size - 1);
+        int nbits = ilog2(sz);
+        u32 addr0, addr1, desc0, desc1;
+
+        if (nbits < 8)
+                nbits = 8;
+
+        /* Set the PCI address */
+        addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) |
+                (lower_32_bits(pci_addr) & GENMASK(31, 8));
+        addr1 = upper_32_bits(pci_addr);
+
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), addr1);
+
+        /* Set the PCIe header descriptor */
+        if (is_io)
+                desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO;
+        else
+                desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM;
+        desc1 = 0;
+
+        /*
+         * Whatever Bit [23] is set or not inside DESC0 register of the outbound
+         * PCIe descriptor, the PCI function number must be set into
+         * Bits [26:24] of DESC0 anyway.
+         *
+         * In Root Complex mode, the function number is always 0 but in Endpoint
+         * mode, the PCIe controller may support more than one function. This
+         * function number needs to be set properly into the outbound PCIe
+         * descriptor.
+         *
+         * Besides, setting Bit [23] is mandatory when in Root Complex mode:
+         * then the driver must provide the bus, resp. device, number in
+         * Bits [7:0] of DESC1, resp. Bits[31:27] of DESC0. Like the function
+         * number, the device number is always 0 in Root Complex mode.
+         *
+         * However when in Endpoint mode, we can clear Bit [23] of DESC0, hence
+         * the PCIe controller will use the captured values for the bus and
+         * device numbers.
+         */
+        if (pcie->is_rc) {
+                /* The device and function numbers are always 0. */
+                desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
+                         CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
+                desc1 |= CDNS_PCIE_AT_OB_REGION_DESC1_BUS(pcie->bus);
+        } else {
+                /*
+                 * Use captured values for bus and device numbers but still
+                 * need to set the function number.
+                 */
+                desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(fn);
+        }
+
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), desc0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1);
+
+        /* Set the CPU address */
+        cpu_addr -= pcie->mem_res->start;
+        addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) |
+                (lower_32_bits(cpu_addr) & GENMASK(31, 8));
+        addr1 = upper_32_bits(cpu_addr);
+
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), addr0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), addr1);
+}
+
+void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn,
+                                                  u32 r, u64 cpu_addr)
+{
+        u32 addr0, addr1, desc0, desc1;
+
+        desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG;
+        desc1 = 0;
+
+        /* See cdns_pcie_set_outbound_region() comments above. */
+        if (pcie->is_rc) {
+                desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
+                         CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
+                desc1 |= CDNS_PCIE_AT_OB_REGION_DESC1_BUS(pcie->bus);
+        } else {
+                desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(fn);
+        }
+
+        /* Set the CPU address */
+        cpu_addr -= pcie->mem_res->start;
+        addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(17) |
+                (lower_32_bits(cpu_addr) & GENMASK(31, 8));
+        addr1 = upper_32_bits(cpu_addr);
+
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), 0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), 0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), desc0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), addr0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), addr1);
+}
+
+void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r)
+{
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), 0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), 0);
+
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), 0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), 0);
+
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), 0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), 0);
+}
diff --git a/drivers/pci/cadence/pcie-cadence.h b/drivers/pci/cadence/pcie-cadence.h
new file mode 100644
index 000000000000..4bb27333b05c
--- /dev/null
+++ b/drivers/pci/cadence/pcie-cadence.h
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017 Cadence
+// Cadence PCIe controller driver.
+// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
+
+#ifndef _PCIE_CADENCE_H
+#define _PCIE_CADENCE_H
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+
+/*
+ * Local Management Registers
+ */
+#define CDNS_PCIE_LM_BASE       0x00100000
+
+/* Vendor ID Register */
+#define CDNS_PCIE_LM_ID         (CDNS_PCIE_LM_BASE + 0x0044)
+#define  CDNS_PCIE_LM_ID_VENDOR_MASK    GENMASK(15, 0)
+#define  CDNS_PCIE_LM_ID_VENDOR_SHIFT   0
+#define  CDNS_PCIE_LM_ID_VENDOR(vid) \
+        (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK)
+#define  CDNS_PCIE_LM_ID_SUBSYS_MASK    GENMASK(31, 16)
+#define  CDNS_PCIE_LM_ID_SUBSYS_SHIFT   16
+#define  CDNS_PCIE_LM_ID_SUBSYS(sub) \
+        (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK)
+
+/* Root Port Requestor ID Register */
+#define CDNS_PCIE_LM_RP_RID     (CDNS_PCIE_LM_BASE + 0x0228)
+#define  CDNS_PCIE_LM_RP_RID_MASK       GENMASK(15, 0)
+#define  CDNS_PCIE_LM_RP_RID_SHIFT      0
+#define  CDNS_PCIE_LM_RP_RID_(rid) \
+        (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK)
+
+/* Endpoint Bus and Device Number Register */
+#define CDNS_PCIE_LM_EP_ID      (CDNS_PCIE_LM_BASE + 0x022c)
+#define  CDNS_PCIE_LM_EP_ID_DEV_MASK    GENMASK(4, 0)
+#define  CDNS_PCIE_LM_EP_ID_DEV_SHIFT   0
+#define  CDNS_PCIE_LM_EP_ID_BUS_MASK    GENMASK(15, 8)
+#define  CDNS_PCIE_LM_EP_ID_BUS_SHIFT   8
+
+/* Endpoint Function f BAR b Configuration Registers */
+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \
+        (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008)
+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \
+        (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008)
+#define  CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \
+        (GENMASK(4, 0) << ((b) * 8))
+#define  CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \
+        (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b))
+#define  CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \
+        (GENMASK(7, 5) << ((b) * 8))
+#define  CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \
+        (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))
+
+/* Endpoint Function Configuration Register */
+#define CDNS_PCIE_LM_EP_FUNC_CFG        (CDNS_PCIE_LM_BASE + 0x02c0)
+
+/* Root Complex BAR Configuration Register */
+#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK     GENMASK(5, 0)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \
+        (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK         GENMASK(8, 6)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \
+        (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK     GENMASK(13, 9)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \
+        (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK         GENMASK(16, 14)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \
+        (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE    BIT(17)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS    0
+#define  CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS    BIT(18)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE              BIT(19)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS              0
+#define  CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS              BIT(20)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE           BIT(31)
+
+/* BAR control values applicable to both Endpoint Function and Root Complex */
+#define  CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED             0x0
+#define  CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS            0x1
+#define  CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS           0x4
+#define  CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS  0x5
+#define  CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS           0x6
+#define  CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS  0x7
+
+
+/*
+ * Endpoint Function Registers (PCI configuration space for endpoint functions)
+ */
+#define CDNS_PCIE_EP_FUNC_BASE(fn)      (((fn) << 12) & GENMASK(19, 12))
+
+#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET        0x90
+
+/*
+ * Root Port Registers (PCI configuration space for the root port function)
+ */
+#define CDNS_PCIE_RP_BASE       0x00200000
+
+
+/*
+ * Address Translation Registers
+ */
+#define CDNS_PCIE_AT_BASE       0x00400000
+
+/* Region r Outbound AXI to PCIe Address Translation Register 0 */
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \
+        (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020)
+#define  CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK    GENMASK(5, 0)
+#define  CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \
+        (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
+#define  CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK    GENMASK(19, 12)
+#define  CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \
+        (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK)
+#define  CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK      GENMASK(27, 20)
+#define  CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \
+        (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK)
+
+/* Region r Outbound AXI to PCIe Address Translation Register 1 */
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \
+        (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020)
+
+/* Region r Outbound PCIe Descriptor Register 0 */
+#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \
+        (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020)
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK         GENMASK(3, 0)
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM          0x2
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO           0x6
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0   0xa
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1   0xb
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG   0xc
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG   0xd
+/* Bit 23 MUST be set in RC mode. */
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID     BIT(23)
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK        GENMASK(31, 24)
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \
+        (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK)
+
+/* Region r Outbound PCIe Descriptor Register 1 */
+#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \
+        (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020)
+#define  CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK  GENMASK(7, 0)
+#define  CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \
+        ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK)
+
+/* Region r AXI Region Base Address Register 0 */
+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \
+        (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020)
+#define  CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK    GENMASK(5, 0)
+#define  CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \
+        (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
+
+/* Region r AXI Region Base Address Register 1 */
+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \
+        (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020)
+
+/* Root Port BAR Inbound PCIe to AXI Address Translation Register */
+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \
+        (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008)
+#define  CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK        GENMASK(5, 0)
+#define  CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \
+        (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
+        (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
+
+enum cdns_pcie_rp_bar {
+        RP_BAR0,
+        RP_BAR1,
+        RP_NO_BAR
+};
+
+/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */
+#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \
+        (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008)
+#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \
+        (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008)
+
+/* Normal/Vendor specific message access: offset inside some outbound region */
+#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK       GENMASK(7, 5)
+#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \
+        (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK)
+#define CDNS_PCIE_NORMAL_MSG_CODE_MASK          GENMASK(15, 8)
+#define CDNS_PCIE_NORMAL_MSG_CODE(code) \
+        (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK)
+#define CDNS_PCIE_MSG_NO_DATA                   BIT(16)
+
+enum cdns_pcie_msg_code {
+        MSG_CODE_ASSERT_INTA    = 0x20,
+        MSG_CODE_ASSERT_INTB    = 0x21,
+        MSG_CODE_ASSERT_INTC    = 0x22,
+        MSG_CODE_ASSERT_INTD    = 0x23,
+        MSG_CODE_DEASSERT_INTA  = 0x24,
+        MSG_CODE_DEASSERT_INTB  = 0x25,
+        MSG_CODE_DEASSERT_INTC  = 0x26,
+        MSG_CODE_DEASSERT_INTD  = 0x27,
+};
+
+enum cdns_pcie_msg_routing {
+        /* Route to Root Complex */
+        MSG_ROUTING_TO_RC,
+
+        /* Use Address Routing */
+        MSG_ROUTING_BY_ADDR,
+
+        /* Use ID Routing */
+        MSG_ROUTING_BY_ID,
+
+        /* Route as Broadcast Message from Root Complex */
+        MSG_ROUTING_BCAST,
+
+        /* Local message; terminate at receiver (INTx messages) */
+        MSG_ROUTING_LOCAL,
+
+        /* Gather & route to Root Complex (PME_TO_Ack message) */
+        MSG_ROUTING_GATHER,
+};
+
+/**
+ * struct cdns_pcie - private data for Cadence PCIe controller drivers
+ * @reg_base: IO mapped register base
+ * @mem_res: start/end offsets in the physical system memory to map PCI accesses
+ * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
+ * @bus: In Root Complex mode, the bus number
+ */
+struct cdns_pcie {
+        void __iomem            *reg_base;
+        struct resource         *mem_res;
+        bool                    is_rc;
+        u8                      bus;
+};
+
+/* Register access */
+static inline void cdns_pcie_writeb(struct cdns_pcie *pcie, u32 reg, u8 value)
+{
+        writeb(value, pcie->reg_base + reg);
+}
+
+static inline void cdns_pcie_writew(struct cdns_pcie *pcie, u32 reg, u16 value)
+{
+        writew(value, pcie->reg_base + reg);
+}
+
+static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value)
+{
+        writel(value, pcie->reg_base + reg);
+}
+
+static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg)
+{
+        return readl(pcie->reg_base + reg);
+}
+
+/* Root Port register access */
+static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie,
+                                       u32 reg, u8 value)
+{
+        writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
+}
+
+static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie,
+                                       u32 reg, u16 value)
+{
+        writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
+}
+
+/* Endpoint Function register access */
+static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn,
+                                          u32 reg, u8 value)
+{
+        writeb(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
+}
+
+static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn,
+                                          u32 reg, u16 value)
+{
+        writew(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
+}
+
+static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn,
+                                          u32 reg, u16 value)
+{
+        writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
+}
+
+static inline u8 cdns_pcie_ep_fn_readb(struct cdns_pcie *pcie, u8 fn, u32 reg)
+{
+        return readb(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
+}
+
+static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg)
+{
+        return readw(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
+}
+
+static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg)
+{
+        return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
+}
+
+void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 fn,
+                                   u32 r, bool is_io,
+                                   u64 cpu_addr, u64 pci_addr, size_t size);
+
+void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn,
+                                                  u32 r, u64 cpu_addr);
+
+void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r);
+
+#endif /* _PCIE_CADENCE_H */
diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
index 113e09440f85..0f666b1ce289 100644
--- a/drivers/pci/dwc/Kconfig
+++ b/drivers/pci/dwc/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
 menu "DesignWare PCI Core Support"
 
 config PCIE_DW
@@ -15,39 +17,38 @@ config PCIE_DW_EP
         select PCIE_DW
 
 config PCI_DRA7XX
-        bool "TI DRA7xx PCIe controller"
-        depends on SOC_DRA7XX || COMPILE_TEST
-        depends on (PCI && PCI_MSI_IRQ_DOMAIN) || PCI_ENDPOINT
-        depends on OF && HAS_IOMEM && TI_PIPE3
-        help
-         Enables support for the PCIe controller in the DRA7xx SoC. There
-         are two instances of PCIe controller in DRA7xx. This controller can
-         work either as EP or RC. In order to enable host-specific features
-         PCI_DRA7XX_HOST must be selected and in order to enable device-
-         specific features PCI_DRA7XX_EP must be selected. This uses
-         the DesignWare core.
-
-if PCI_DRA7XX
+        bool
 
 config PCI_DRA7XX_HOST
-        bool "PCI DRA7xx Host Mode"
-        depends on PCI
-        depends on PCI_MSI_IRQ_DOMAIN
+        bool "TI DRA7xx PCIe controller Host Mode"
+        depends on SOC_DRA7XX || COMPILE_TEST
+        depends on PCI && PCI_MSI_IRQ_DOMAIN
+        depends on OF && HAS_IOMEM && TI_PIPE3
         select PCIE_DW_HOST
+        select PCI_DRA7XX
         default y
         help
-         Enables support for the PCIe controller in the DRA7xx SoC to work in
-         host mode.
+          Enables support for the PCIe controller in the DRA7xx SoC to work in
+          host mode. There are two instances of PCIe controller in DRA7xx.
+          This controller can work either as EP or RC. In order to enable
+          host-specific features PCI_DRA7XX_HOST must be selected and in order
+          to enable device-specific features PCI_DRA7XX_EP must be selected.
+          This uses the DesignWare core.
 
 config PCI_DRA7XX_EP
-        bool "PCI DRA7xx Endpoint Mode"
+        bool "TI DRA7xx PCIe controller Endpoint Mode"
+        depends on SOC_DRA7XX || COMPILE_TEST
         depends on PCI_ENDPOINT
+        depends on OF && HAS_IOMEM && TI_PIPE3
         select PCIE_DW_EP
+        select PCI_DRA7XX
         help
-         Enables support for the PCIe controller in the DRA7xx SoC to work in
-         endpoint mode.
-
-endif
+          Enables support for the PCIe controller in the DRA7xx SoC to work in
+          endpoint mode. There are two instances of PCIe controller in DRA7xx.
+          This controller can work either as EP or RC. In order to enable
+          host-specific features PCI_DRA7XX_HOST must be selected and in order
+          to enable device-specific features PCI_DRA7XX_EP must be selected.
+          This uses the DesignWare core.
 
 config PCIE_DW_PLAT
         bool "Platform bus based DesignWare PCIe Controller"
@@ -149,15 +150,28 @@ config PCIE_ARMADA_8K
           DesignWare core functions to implement the driver.
 
 config PCIE_ARTPEC6
-        bool "Axis ARTPEC-6 PCIe controller"
-        depends on PCI
+        bool
+
+config PCIE_ARTPEC6_HOST
+        bool "Axis ARTPEC-6 PCIe controller Host Mode"
         depends on MACH_ARTPEC6
-        depends on PCI_MSI_IRQ_DOMAIN
+        depends on PCI && PCI_MSI_IRQ_DOMAIN
         select PCIEPORTBUS
         select PCIE_DW_HOST
+        select PCIE_ARTPEC6
+        help
+          Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
+          host mode. This uses the DesignWare core.
+
+config PCIE_ARTPEC6_EP
+        bool "Axis ARTPEC-6 PCIe controller Endpoint Mode"
+        depends on MACH_ARTPEC6
+        depends on PCI_ENDPOINT
+        select PCIE_DW_EP
+        select PCIE_ARTPEC6
         help
-          Say Y here to enable PCIe controller support on Axis ARTPEC-6
-          SoCs.  This PCIe controller uses the DesignWare core.
+          Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
+          endpoint mode. This uses the DesignWare core.
 
 config PCIE_KIRIN
         depends on OF && ARM64
diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
index 41ba499c96ee..5d2ce72c7a52 100644
--- a/drivers/pci/dwc/Makefile
+++ b/drivers/pci/dwc/Makefile
@@ -3,9 +3,7 @@ obj-$(CONFIG_PCIE_DW) += pcie-designware.o
 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
-ifneq ($(filter y,$(CONFIG_PCI_DRA7XX_HOST) $(CONFIG_PCI_DRA7XX_EP)),)
-        obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
-endif
+obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
 obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
 obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
@@ -27,4 +25,6 @@ obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
 # ARM64 and use internal ifdefs to only build the pieces we need
 # depending on whether ACPI, the DT driver, or both are enabled.
 
+ifdef CONFIG_PCI
 obj-$(CONFIG_ARM64) += pcie-hisi.o
+endif
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index e77a4ceed74c..ed8558d638e5 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
  *
  * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
  *
  * Authors: Kishon Vijay Abraham I <kishon@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include <linux/delay.h>
@@ -110,7 +107,7 @@ static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
         writel(value, pcie->base + offset);
 }
 
-static u64 dra7xx_pcie_cpu_addr_fixup(u64 pci_addr)
+static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
 {
         return pci_addr & DRA7XX_CPU_TO_BUS_ADDR;
 }
@@ -226,6 +223,7 @@ static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
 
 static const struct irq_domain_ops intx_domain_ops = {
         .map = dra7xx_pcie_intx_map,
+        .xlate = pci_irqd_intx_xlate,
 };
 
 static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
@@ -256,7 +254,8 @@ static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
         struct dra7xx_pcie *dra7xx = arg;
         struct dw_pcie *pci = dra7xx->pci;
         struct pcie_port *pp = &pci->pp;
-        u32 reg;
+        unsigned long reg;
+        u32 virq, bit;
 
         reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
 
@@ -268,8 +267,11 @@ static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
         case INTB:
         case INTC:
         case INTD:
-                generic_handle_irq(irq_find_mapping(dra7xx->irq_domain,
-                                                    ffs(reg)));
+                for_each_set_bit(bit, &reg, PCI_NUM_INTX) {
+                        virq = irq_find_mapping(dra7xx->irq_domain, bit);
+                        if (virq)
+                                generic_handle_irq(virq);
+                }
                 break;
         }
 
@@ -337,15 +339,6 @@ static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
         return IRQ_HANDLED;
 }
 
-static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
-{
-        u32 reg;
-
-        reg = PCI_BASE_ADDRESS_0 + (4 * bar);
-        dw_pcie_writel_dbi2(pci, reg, 0x0);
-        dw_pcie_writel_dbi(pci, reg, 0x0);
-}
-
 static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
 {
         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -375,7 +368,7 @@ static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
         dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg);
 }
 
-static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep,
+static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
                                  enum pci_epc_irq_type type, u8 interrupt_num)
 {
         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -470,6 +463,8 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
         if (!pci->dbi_base)
                 return -ENOMEM;
 
+        pp->ops = &dra7xx_pcie_host_ops;
+
         ret = dw_pcie_host_init(pp);
         if (ret) {
                 dev_err(dev, "failed to initialize host\n");
@@ -599,7 +594,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
         void __iomem *base;
         struct resource *res;
         struct dw_pcie *pci;
-        struct pcie_port *pp;
         struct dra7xx_pcie *dra7xx;
         struct device *dev = &pdev->dev;
         struct device_node *np = dev->of_node;
@@ -627,9 +621,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
         pci->dev = dev;
         pci->ops = &dw_pcie_ops;
 
-        pp = &pci->pp;
-        pp->ops = &dra7xx_pcie_host_ops;
-
         irq = platform_get_irq(pdev, 0);
         if (irq < 0) {
                 dev_err(dev, "missing IRQ resource: %d\n", irq);
@@ -705,6 +696,11 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 
         switch (mode) {
         case DW_PCIE_RC_TYPE:
+                if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {
+                        ret = -ENODEV;
+                        goto err_gpio;
+                }
+
                 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
                                    DEVICE_TYPE_RC);
                 ret = dra7xx_add_pcie_port(dra7xx, pdev);
@@ -712,6 +708,11 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
                         goto err_gpio;
                 break;
         case DW_PCIE_EP_TYPE:
+                if (!IS_ENABLED(CONFIG_PCI_DRA7XX_EP)) {
+                        ret = -ENODEV;
+                        goto err_gpio;
+                }
+
                 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
                                    DEVICE_TYPE_EP);
 
@@ -810,7 +811,7 @@ static int dra7xx_pcie_resume_noirq(struct device *dev)
 }
 #endif
 
-void dra7xx_pcie_shutdown(struct platform_device *pdev)
+static void dra7xx_pcie_shutdown(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
index 5596fdedbb94..ca6278113936 100644
--- a/drivers/pci/dwc/pci-exynos.c
+++ b/drivers/pci/dwc/pci-exynos.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * PCIe host controller driver for Samsung EXYNOS SoCs
  *
@@ -5,10 +6,6 @@
  *              http://www.samsung.com
  *
  * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include <linux/clk.h>
@@ -55,49 +52,8 @@
 #define PCIE_ELBI_SLV_ARMISC            0x120
 #define PCIE_ELBI_SLV_DBI_ENABLE        BIT(21)
 
-/* PCIe Purple registers */
-#define PCIE_PHY_GLOBAL_RESET           0x000
-#define PCIE_PHY_COMMON_RESET           0x004
-#define PCIE_PHY_CMN_REG                0x008
-#define PCIE_PHY_MAC_RESET              0x00c
-#define PCIE_PHY_PLL_LOCKED             0x010
-#define PCIE_PHY_TRSVREG_RESET          0x020
-#define PCIE_PHY_TRSV_RESET             0x024
-
-/* PCIe PHY registers */
-#define PCIE_PHY_IMPEDANCE              0x004
-#define PCIE_PHY_PLL_DIV_0              0x008
-#define PCIE_PHY_PLL_BIAS               0x00c
-#define PCIE_PHY_DCC_FEEDBACK           0x014
-#define PCIE_PHY_PLL_DIV_1              0x05c
-#define PCIE_PHY_COMMON_POWER           0x064
-#define PCIE_PHY_COMMON_PD_CMN          BIT(3)
-#define PCIE_PHY_TRSV0_EMP_LVL          0x084
-#define PCIE_PHY_TRSV0_DRV_LVL          0x088
-#define PCIE_PHY_TRSV0_RXCDR            0x0ac
-#define PCIE_PHY_TRSV0_POWER            0x0c4
-#define PCIE_PHY_TRSV0_PD_TSV           BIT(7)
-#define PCIE_PHY_TRSV0_LVCC             0x0dc
-#define PCIE_PHY_TRSV1_EMP_LVL          0x144
-#define PCIE_PHY_TRSV1_RXCDR            0x16c
-#define PCIE_PHY_TRSV1_POWER            0x184
-#define PCIE_PHY_TRSV1_PD_TSV           BIT(7)
-#define PCIE_PHY_TRSV1_LVCC             0x19c
-#define PCIE_PHY_TRSV2_EMP_LVL          0x204
-#define PCIE_PHY_TRSV2_RXCDR            0x22c
-#define PCIE_PHY_TRSV2_POWER            0x244
-#define PCIE_PHY_TRSV2_PD_TSV           BIT(7)
-#define PCIE_PHY_TRSV2_LVCC             0x25c
-#define PCIE_PHY_TRSV3_EMP_LVL          0x2c4
-#define PCIE_PHY_TRSV3_RXCDR            0x2ec
-#define PCIE_PHY_TRSV3_POWER            0x304
-#define PCIE_PHY_TRSV3_PD_TSV           BIT(7)
-#define PCIE_PHY_TRSV3_LVCC             0x31c
-
 struct exynos_pcie_mem_res {
         void __iomem *elbi_base;   /* DT 0th resource: PCIe CTRL */
-        void __iomem *phy_base;    /* DT 1st resource: PHY CTRL */
-        void __iomem *block_base;  /* DT 2nd resource: PHY ADDITIONAL CTRL */
 };
 
 struct exynos_pcie_clk_res {
@@ -112,8 +68,6 @@ struct exynos_pcie {
         const struct exynos_pcie_ops    *ops;
         int                             reset_gpio;
 
-        /* For Generic PHY Framework */
-        bool                            using_phy;
         struct phy                      *phy;
 };
 
@@ -141,20 +95,6 @@ static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
         if (IS_ERR(ep->mem_res->elbi_base))
                 return PTR_ERR(ep->mem_res->elbi_base);
 
-        /* If using the PHY framework, doesn't need to get other resource */
-        if (ep->using_phy)
-                return 0;
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-        ep->mem_res->phy_base = devm_ioremap_resource(dev, res);
-        if (IS_ERR(ep->mem_res->phy_base))
-                return PTR_ERR(ep->mem_res->phy_base);
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
-        ep->mem_res->block_base = devm_ioremap_resource(dev, res);
-        if (IS_ERR(ep->mem_res->block_base))
-                return PTR_ERR(ep->mem_res->block_base);
-
         return 0;
 }
 
@@ -279,111 +219,6 @@ static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep)
         exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_NONSTICKY_RESET);
         exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_APP_INIT_RESET);
         exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_APP_INIT_RESET);
-        exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_MAC_RESET);
-}
-
-static void exynos_pcie_assert_phy_reset(struct exynos_pcie *ep)
-{
-        exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_MAC_RESET);
-        exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_GLOBAL_RESET);
-}
-
-static void exynos_pcie_deassert_phy_reset(struct exynos_pcie *ep)
-{
-        exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_GLOBAL_RESET);
-        exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_PWR_RESET);
-        exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_COMMON_RESET);
-        exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_CMN_REG);
-        exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_TRSVREG_RESET);
-        exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_TRSV_RESET);
-}
-
-static void exynos_pcie_power_on_phy(struct exynos_pcie *ep)
-{
-        u32 val;
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_COMMON_POWER);
-        val &= ~PCIE_PHY_COMMON_PD_CMN;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_COMMON_POWER);
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV0_POWER);
-        val &= ~PCIE_PHY_TRSV0_PD_TSV;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV0_POWER);
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV1_POWER);
-        val &= ~PCIE_PHY_TRSV1_PD_TSV;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV1_POWER);
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV2_POWER);
-        val &= ~PCIE_PHY_TRSV2_PD_TSV;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV2_POWER);
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV3_POWER);
-        val &= ~PCIE_PHY_TRSV3_PD_TSV;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV3_POWER);
-}
-
-static void exynos_pcie_power_off_phy(struct exynos_pcie *ep)
-{
-        u32 val;
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_COMMON_POWER);
-        val |= PCIE_PHY_COMMON_PD_CMN;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_COMMON_POWER);
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV0_POWER);
-        val |= PCIE_PHY_TRSV0_PD_TSV;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV0_POWER);
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV1_POWER);
-        val |= PCIE_PHY_TRSV1_PD_TSV;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV1_POWER);
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV2_POWER);
-        val |= PCIE_PHY_TRSV2_PD_TSV;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV2_POWER);
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV3_POWER);
-        val |= PCIE_PHY_TRSV3_PD_TSV;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV3_POWER);
-}
-
-static void exynos_pcie_init_phy(struct exynos_pcie *ep)
-{
-        /* DCC feedback control off */
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
-
-        /* set TX/RX impedance */
-        exynos_pcie_writel(ep->mem_res->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
-
-        /* set 50Mhz PHY clock */
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
-
-        /* set TX Differential output for lane 0 */
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
-
-        /* set TX Pre-emphasis Level Control for lane 0 to minimum */
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
-
-        /* set RX clock and data recovery bandwidth */
-        exynos_pcie_writel(ep->mem_res->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
-
-        /* change TX Pre-emphasis Level Control for lanes */
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
-
-        /* set LVCC */
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
 }
 
 static void exynos_pcie_assert_reset(struct exynos_pcie *ep)
@@ -401,7 +236,6 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep)
         struct dw_pcie *pci = ep->pci;
         struct pcie_port *pp = &pci->pp;
         struct device *dev = pci->dev;
-        u32 val;
 
         if (dw_pcie_link_up(pci)) {
                 dev_err(dev, "Link already up\n");
@@ -410,32 +244,13 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep)
 
         exynos_pcie_assert_core_reset(ep);
 
-        if (ep->using_phy) {
-                phy_reset(ep->phy);
-
-                exynos_pcie_writel(ep->mem_res->elbi_base, 1,
-                                PCIE_PWR_RESET);
-
-                phy_power_on(ep->phy);
-                phy_init(ep->phy);
-        } else {
-                exynos_pcie_assert_phy_reset(ep);
-                exynos_pcie_deassert_phy_reset(ep);
-                exynos_pcie_power_on_phy(ep);
-                exynos_pcie_init_phy(ep);
-
-                /* pulse for common reset */
-                exynos_pcie_writel(ep->mem_res->block_base, 1,
-                                        PCIE_PHY_COMMON_RESET);
-                udelay(500);
-                exynos_pcie_writel(ep->mem_res->block_base, 0,
-                                        PCIE_PHY_COMMON_RESET);
-        }
+        phy_reset(ep->phy);
 
-        /* pulse for common reset */
-        exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_COMMON_RESET);
-        udelay(500);
-        exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_COMMON_RESET);
+        exynos_pcie_writel(ep->mem_res->elbi_base, 1,
+                        PCIE_PWR_RESET);
+
+        phy_power_on(ep->phy);
+        phy_init(ep->phy);
 
         exynos_pcie_deassert_core_reset(ep);
         dw_pcie_setup_rc(pp);
@@ -449,18 +264,7 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep)
         if (!dw_pcie_wait_for_link(pci))
                 return 0;
 
-        if (ep->using_phy) {
-                phy_power_off(ep->phy);
-                return -ETIMEDOUT;
-        }
-
-        while (exynos_pcie_readl(ep->mem_res->phy_base,
-                                PCIE_PHY_PLL_LOCKED) == 0) {
-                val = exynos_pcie_readl(ep->mem_res->block_base,
-                                PCIE_PHY_PLL_LOCKED);
-                dev_info(dev, "PLL Locked: 0x%x\n", val);
-        }
-        exynos_pcie_power_off_phy(ep);
+        phy_power_off(ep->phy);
         return -ETIMEDOUT;
 }
 
@@ -678,16 +482,13 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
 
         ep->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
 
-        /* Assume that controller doesn't use the PHY framework */
-        ep->using_phy = false;
-
         ep->phy = devm_of_phy_get(dev, np, NULL);
         if (IS_ERR(ep->phy)) {
                 if (PTR_ERR(ep->phy) == -EPROBE_DEFER)
                         return PTR_ERR(ep->phy);
-                dev_warn(dev, "Use the 'phy' property. Current DT of pci-exynos was deprecated!!\n");
-        } else
-                ep->using_phy = true;
+
+                ep->phy = NULL;
+        }
 
         if (ep->ops && ep->ops->get_mem_resources) {
                 ret = ep->ops->get_mem_resources(pdev, ep);
@@ -695,7 +496,8 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
                         return ret;
         }
 
-        if (ep->ops && ep->ops->get_clk_resources) {
+        if (ep->ops && ep->ops->get_clk_resources &&
+                        ep->ops->init_clk_resources) {
                 ret = ep->ops->get_clk_resources(ep);
                 if (ret)
                         return ret;
@@ -713,8 +515,7 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
         return 0;
 
 fail_probe:
-        if (ep->using_phy)
-                phy_exit(ep->phy);
+        phy_exit(ep->phy);
 
         if (ep->ops && ep->ops->deinit_clk_resources)
                 ep->ops->deinit_clk_resources(ep);
diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c
index b73483534a5b..4fddbd08b089 100644
--- a/drivers/pci/dwc/pci-imx6.c
+++ b/drivers/pci/dwc/pci-imx6.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * PCIe host controller driver for Freescale i.MX6 SoCs
  *
@@ -5,10 +6,6 @@
  *              http://www.kosagi.com
  *
  * Author: Sean Cross <xobs@kosagi.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c
index 2fb20b887d2a..99a0e7076221 100644
--- a/drivers/pci/dwc/pci-keystone-dw.c
+++ b/drivers/pci/dwc/pci-keystone-dw.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * DesignWare application register space functions for Keystone PCI controller
  *
@@ -5,11 +6,6 @@
  *              http://www.ti.com
  *
  * Author: Murali Karicheri <m-karicheri2@ti.com>
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include <linux/irq.h>
diff --git a/drivers/pci/dwc/pci-keystone.c b/drivers/pci/dwc/pci-keystone.c
index 5bee3af47588..d4f8ab90c018 100644
--- a/drivers/pci/dwc/pci-keystone.c
+++ b/drivers/pci/dwc/pci-keystone.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * PCIe host controller driver for Texas Instruments Keystone SoCs
  *
@@ -6,10 +7,6 @@
  *
  * Author: Murali Karicheri <m-karicheri2@ti.com>
  * Implementation based on pci-exynos.c and pcie-designware.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include <linux/irqchip/chained_irq.h>
@@ -178,7 +175,7 @@ static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
         }
 
         /* interrupt controller is in a child node */
-        *np_temp = of_find_node_by_name(np_pcie, controller);
+        *np_temp = of_get_child_by_name(np_pcie, controller);
         if (!(*np_temp)) {
                 dev_err(dev, "Node for %s is absent\n", controller);
                 return -EINVAL;
@@ -187,6 +184,7 @@ static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
         temp = of_irq_count(*np_temp);
         if (!temp) {
                 dev_err(dev, "No IRQ entries in %s\n", controller);
+                of_node_put(*np_temp);
                 return -EINVAL;
         }
 
@@ -204,6 +202,8 @@ static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
                         break;
         }
 
+        of_node_put(*np_temp);
+
         if (temp) {
                 *num_irqs = temp;
                 return 0;
diff --git a/drivers/pci/dwc/pci-keystone.h b/drivers/pci/dwc/pci-keystone.h
index 30b7bc2ac380..1dd1f3ef98e7 100644
--- a/drivers/pci/dwc/pci-keystone.h
+++ b/drivers/pci/dwc/pci-keystone.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Keystone PCI Controller's common includes
  *
@@ -5,11 +6,6 @@
  *              http://www.ti.com
  *
  * Author: Murali Karicheri <m-karicheri2@ti.com>
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #define MAX_MSI_HOST_IRQS               8
diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 8f34c2fdc600..a7b4159631ae 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * PCIe host controller driver for Freescale Layerscape SoCs
  *
  * Copyright (C) 2014 Freescale Semiconductor.
  *
  * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include <linux/kernel.h>
diff --git a/drivers/pci/dwc/pcie-armada8k.c b/drivers/pci/dwc/pcie-armada8k.c
index 370d057c0046..b587352f8b9f 100644
--- a/drivers/pci/dwc/pcie-armada8k.c
+++ b/drivers/pci/dwc/pcie-armada8k.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * PCIe host controller driver for Marvell Armada-8K SoCs
  *
@@ -7,10 +8,6 @@
  *
  * Author: Yehuda Yitshak <yehuday@marvell.com>
  * Author: Shadi Ammouri <shadi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index 6653619db6a1..93b3df9ed1b5 100644
--- a/drivers/pci/dwc/pcie-artpec6.c
+++ b/drivers/pci/dwc/pcie-artpec6.c
@@ -1,18 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * PCIe host controller driver for Axis ARTPEC-6 SoC
  *
  * Author: Niklas Cassel <niklas.cassel@axis.com>
  *
  * Based on work done by Phil Edworthy <phil@edworthys.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include <linux/delay.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/of_device.h>
 #include <linux/pci.h>
 #include <linux/platform_device.h>
 #include <linux/resource.h>
@@ -26,44 +24,72 @@
 
 #define to_artpec6_pcie(x)      dev_get_drvdata((x)->dev)
 
+enum artpec_pcie_variants {
+        ARTPEC6,
+        ARTPEC7,
+};
+
 struct artpec6_pcie {
         struct dw_pcie          *pci;
         struct regmap           *regmap;        /* DT axis,syscon-pcie */
         void __iomem            *phy_base;      /* DT phy */
+        enum artpec_pcie_variants variant;
+        enum dw_pcie_device_mode mode;
 };
 
+struct artpec_pcie_of_data {
+        enum artpec_pcie_variants variant;
+        enum dw_pcie_device_mode mode;
+};
+
+static const struct of_device_id artpec6_pcie_of_match[];
+
 /* PCIe Port Logic registers (memory-mapped) */
 #define PL_OFFSET                       0x700
-#define PCIE_PHY_DEBUG_R0               (PL_OFFSET + 0x28)
-#define PCIE_PHY_DEBUG_R1               (PL_OFFSET + 0x2c)
 
-#define MISC_CONTROL_1_OFF              (PL_OFFSET + 0x1bc)
-#define  DBI_RO_WR_EN                   1
+#define ACK_F_ASPM_CTRL_OFF             (PL_OFFSET + 0xc)
+#define ACK_N_FTS_MASK                  GENMASK(15, 8)
+#define ACK_N_FTS(x)                    (((x) << 8) & ACK_N_FTS_MASK)
+
+#define FAST_TRAINING_SEQ_MASK          GENMASK(7, 0)
+#define FAST_TRAINING_SEQ(x)            (((x) << 0) & FAST_TRAINING_SEQ_MASK)
 
 /* ARTPEC-6 specific registers */
 #define PCIECFG                         0x18
-#define  PCIECFG_DBG_OEN                (1 << 24)
-#define  PCIECFG_CORE_RESET_REQ         (1 << 21)
-#define  PCIECFG_LTSSM_ENABLE           (1 << 20)
-#define  PCIECFG_CLKREQ_B               (1 << 11)
-#define  PCIECFG_REFCLK_ENABLE          (1 << 10)
-#define  PCIECFG_PLL_ENABLE             (1 << 9)
-#define  PCIECFG_PCLK_ENABLE            (1 << 8)
-#define  PCIECFG_RISRCREN               (1 << 4)
-#define  PCIECFG_MODE_TX_DRV_EN         (1 << 3)
-#define  PCIECFG_CISRREN                (1 << 2)
-#define  PCIECFG_MACRO_ENABLE           (1 << 0)
+#define  PCIECFG_DBG_OEN                BIT(24)
+#define  PCIECFG_CORE_RESET_REQ         BIT(21)
+#define  PCIECFG_LTSSM_ENABLE           BIT(20)
+#define  PCIECFG_DEVICE_TYPE_MASK       GENMASK(19, 16)
+#define  PCIECFG_CLKREQ_B               BIT(11)
+#define  PCIECFG_REFCLK_ENABLE          BIT(10)
+#define  PCIECFG_PLL_ENABLE             BIT(9)
+#define  PCIECFG_PCLK_ENABLE            BIT(8)
+#define  PCIECFG_RISRCREN               BIT(4)
+#define  PCIECFG_MODE_TX_DRV_EN         BIT(3)
+#define  PCIECFG_CISRREN                BIT(2)
+#define  PCIECFG_MACRO_ENABLE           BIT(0)
+/* ARTPEC-7 specific fields */
+#define  PCIECFG_REFCLKSEL              BIT(23)
+#define  PCIECFG_NOC_RESET              BIT(3)
+
+#define PCIESTAT                        0x1c
+/* ARTPEC-7 specific fields */
+#define  PCIESTAT_EXTREFCLK             BIT(3)
 
 #define NOCCFG                          0x40
-#define NOCCFG_ENABLE_CLK_PCIE          (1 << 4)
-#define NOCCFG_POWER_PCIE_IDLEACK       (1 << 3)
-#define NOCCFG_POWER_PCIE_IDLE          (1 << 2)
-#define NOCCFG_POWER_PCIE_IDLEREQ       (1 << 1)
+#define  NOCCFG_ENABLE_CLK_PCIE         BIT(4)
+#define  NOCCFG_POWER_PCIE_IDLEACK      BIT(3)
+#define  NOCCFG_POWER_PCIE_IDLE         BIT(2)
+#define  NOCCFG_POWER_PCIE_IDLEREQ      BIT(1)
 
 #define PHY_STATUS                      0x118
-#define PHY_COSPLLLOCK                  (1 << 0)
+#define  PHY_COSPLLLOCK                 BIT(0)
+
+#define PHY_TX_ASIC_OUT                 0x4040
+#define  PHY_TX_ASIC_OUT_TX_ACK         BIT(0)
 
-#define ARTPEC6_CPU_TO_BUS_ADDR         0x0fffffff
+#define PHY_RX_ASIC_OUT                 0x405c
+#define  PHY_RX_ASIC_OUT_ACK            BIT(0)
 
 static u32 artpec6_pcie_readl(struct artpec6_pcie *artpec6_pcie, u32 offset)
 {
@@ -78,22 +104,123 @@ static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u
         regmap_write(artpec6_pcie->regmap, offset, val);
 }
 
-static u64 artpec6_pcie_cpu_addr_fixup(u64 pci_addr)
+static u64 artpec6_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
 {
-        return pci_addr & ARTPEC6_CPU_TO_BUS_ADDR;
+        struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
+        struct pcie_port *pp = &pci->pp;
+        struct dw_pcie_ep *ep = &pci->ep;
+
+        switch (artpec6_pcie->mode) {
+        case DW_PCIE_RC_TYPE:
+                return pci_addr - pp->cfg0_base;
+        case DW_PCIE_EP_TYPE:
+                return pci_addr - ep->phys_base;
+        default:
+                dev_err(pci->dev, "UNKNOWN device type\n");
+        }
+        return pci_addr;
 }
 
-static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
+static int artpec6_pcie_establish_link(struct dw_pcie *pci)
 {
-        struct dw_pcie *pci = artpec6_pcie->pci;
-        struct pcie_port *pp = &pci->pp;
+        struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
+        u32 val;
+
+        val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
+        val |= PCIECFG_LTSSM_ENABLE;
+        artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
+
+        return 0;
+}
+
+static void artpec6_pcie_stop_link(struct dw_pcie *pci)
+{
+        struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
         u32 val;
-        unsigned int retries;
 
-        /* Hold DW core in reset */
         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
-        val |= PCIECFG_CORE_RESET_REQ;
+        val &= ~PCIECFG_LTSSM_ENABLE;
         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
+}
+
+static const struct dw_pcie_ops dw_pcie_ops = {
+        .cpu_addr_fixup = artpec6_pcie_cpu_addr_fixup,
+        .start_link = artpec6_pcie_establish_link,
+        .stop_link = artpec6_pcie_stop_link,
+};
+
+static void artpec6_pcie_wait_for_phy_a6(struct artpec6_pcie *artpec6_pcie)
+{
+        struct dw_pcie *pci = artpec6_pcie->pci;
+        struct device *dev = pci->dev;
+        u32 val;
+        unsigned int retries;
+
+        retries = 50;
+        do {
+                usleep_range(1000, 2000);
+                val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
+                retries--;
+        } while (retries &&
+                (val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
+        if (!retries)
+                dev_err(dev, "PCIe clock manager did not leave idle state\n");
+
+        retries = 50;
+        do {
+                usleep_range(1000, 2000);
+                val = readl(artpec6_pcie->phy_base + PHY_STATUS);
+                retries--;
+        } while (retries && !(val & PHY_COSPLLLOCK));
+        if (!retries)
+                dev_err(dev, "PHY PLL did not lock\n");
+}
+
+static void artpec6_pcie_wait_for_phy_a7(struct artpec6_pcie *artpec6_pcie)
+{
+        struct dw_pcie *pci = artpec6_pcie->pci;
+        struct device *dev = pci->dev;
+        u32 val;
+        u16 phy_status_tx, phy_status_rx;
+        unsigned int retries;
+
+        retries = 50;
+        do {
+                usleep_range(1000, 2000);
+                val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
+                retries--;
+        } while (retries &&
+                (val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
+        if (!retries)
+                dev_err(dev, "PCIe clock manager did not leave idle state\n");
+
+        retries = 50;
+        do {
+                usleep_range(1000, 2000);
+                phy_status_tx = readw(artpec6_pcie->phy_base + PHY_TX_ASIC_OUT);
+                phy_status_rx = readw(artpec6_pcie->phy_base + PHY_RX_ASIC_OUT);
+                retries--;
+        } while (retries && ((phy_status_tx & PHY_TX_ASIC_OUT_TX_ACK) ||
+                                (phy_status_rx & PHY_RX_ASIC_OUT_ACK)));
+        if (!retries)
+                dev_err(dev, "PHY did not enter Pn state\n");
+}
+
+static void artpec6_pcie_wait_for_phy(struct artpec6_pcie *artpec6_pcie)
+{
+        switch (artpec6_pcie->variant) {
+        case ARTPEC6:
+                artpec6_pcie_wait_for_phy_a6(artpec6_pcie);
+                break;
+        case ARTPEC7:
+                artpec6_pcie_wait_for_phy_a7(artpec6_pcie);
+                break;
+        }
+}
+
+static void artpec6_pcie_init_phy_a6(struct artpec6_pcie *artpec6_pcie)
+{
+        u32 val;
 
         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
         val |=  PCIECFG_RISRCREN |      /* Receiver term. 50 Ohm */
@@ -119,45 +246,110 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
         val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
         val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
         artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
+}
 
-        retries = 50;
-        do {
-                usleep_range(1000, 2000);
-                val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
-                retries--;
-        } while (retries &&
-                (val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
+static void artpec6_pcie_init_phy_a7(struct artpec6_pcie *artpec6_pcie)
+{
+        struct dw_pcie *pci = artpec6_pcie->pci;
+        u32 val;
+        bool extrefclk;
 
-        retries = 50;
-        do {
-                usleep_range(1000, 2000);
-                val = readl(artpec6_pcie->phy_base + PHY_STATUS);
-                retries--;
-        } while (retries && !(val & PHY_COSPLLLOCK));
+        /* Check if external reference clock is connected */
+        val = artpec6_pcie_readl(artpec6_pcie, PCIESTAT);
+        extrefclk = !!(val & PCIESTAT_EXTREFCLK);
+        dev_dbg(pci->dev, "Using reference clock: %s\n",
+                extrefclk ? "external" : "internal");
 
-        /* Take DW core out of reset */
         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
-        val &= ~PCIECFG_CORE_RESET_REQ;
+        val |=  PCIECFG_RISRCREN |      /* Receiver term. 50 Ohm */
+                PCIECFG_PCLK_ENABLE;
+        if (extrefclk)
+                val |= PCIECFG_REFCLKSEL;
+        else
+                val &= ~PCIECFG_REFCLKSEL;
         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
-        usleep_range(100, 200);
+        usleep_range(10, 20);
 
-        /* setup root complex */
-        dw_pcie_setup_rc(pp);
+        val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
+        val |= NOCCFG_ENABLE_CLK_PCIE;
+        artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
+        usleep_range(20, 30);
+
+        val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
+        val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
+        artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
+}
+
+static void artpec6_pcie_init_phy(struct artpec6_pcie *artpec6_pcie)
+{
+        switch (artpec6_pcie->variant) {
+        case ARTPEC6:
+                artpec6_pcie_init_phy_a6(artpec6_pcie);
+                break;
+        case ARTPEC7:
+                artpec6_pcie_init_phy_a7(artpec6_pcie);
+                break;
+        }
+}
+
+static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie)
+{
+        struct dw_pcie *pci = artpec6_pcie->pci;
+        u32 val;
+
+        if (artpec6_pcie->variant != ARTPEC7)
+                return;
+
+        /*
+         * Increase the N_FTS (Number of Fast Training Sequences)
+         * to be transmitted when transitioning from L0s to L0.
+         */
+        val = dw_pcie_readl_dbi(pci, ACK_F_ASPM_CTRL_OFF);
+        val &= ~ACK_N_FTS_MASK;
+        val |= ACK_N_FTS(180);
+        dw_pcie_writel_dbi(pci, ACK_F_ASPM_CTRL_OFF, val);
+
+        /*
+         * Set the Number of Fast Training Sequences that the core
+         * advertises as its N_FTS during Gen2 or Gen3 link training.
+         */
+        val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+        val &= ~FAST_TRAINING_SEQ_MASK;
+        val |= FAST_TRAINING_SEQ(180);
+        dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+}
+
+static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie)
+{
+        u32 val;
 
-        /* assert LTSSM enable */
         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
-        val |= PCIECFG_LTSSM_ENABLE;
+        switch (artpec6_pcie->variant) {
+        case ARTPEC6:
+                val |= PCIECFG_CORE_RESET_REQ;
+                break;
+        case ARTPEC7:
+                val &= ~PCIECFG_NOC_RESET;
+                break;
+        }
         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
+}
 
-        /* check if the link is up or not */
-        if (!dw_pcie_wait_for_link(pci))
-                return 0;
-
-        dev_dbg(pci->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
-                dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
-                dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
+static void artpec6_pcie_deassert_core_reset(struct artpec6_pcie *artpec6_pcie)
+{
+        u32 val;
 
-        return -ETIMEDOUT;
+        val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
+        switch (artpec6_pcie->variant) {
+        case ARTPEC6:
+                val &= ~PCIECFG_CORE_RESET_REQ;
+                break;
+        case ARTPEC7:
+                val |= PCIECFG_NOC_RESET;
+                break;
+        }
+        artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
+        usleep_range(100, 200);
 }
 
 static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie)
@@ -174,7 +366,14 @@ static int artpec6_pcie_host_init(struct pcie_port *pp)
         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
         struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
 
-        artpec6_pcie_establish_link(artpec6_pcie);
+        artpec6_pcie_assert_core_reset(artpec6_pcie);
+        artpec6_pcie_init_phy(artpec6_pcie);
+        artpec6_pcie_deassert_core_reset(artpec6_pcie);
+        artpec6_pcie_wait_for_phy(artpec6_pcie);
+        artpec6_pcie_set_nfts(artpec6_pcie);
+        dw_pcie_setup_rc(pp);
+        artpec6_pcie_establish_link(pci);
+        dw_pcie_wait_for_link(pci);
         artpec6_pcie_enable_interrupts(artpec6_pcie);
 
         return 0;
@@ -230,10 +429,78 @@ static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
         return 0;
 }
 
-static const struct dw_pcie_ops dw_pcie_ops = {
-        .cpu_addr_fixup = artpec6_pcie_cpu_addr_fixup,
+static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)
+{
+        struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+        struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
+        enum pci_barno bar;
+
+        artpec6_pcie_assert_core_reset(artpec6_pcie);
+        artpec6_pcie_init_phy(artpec6_pcie);
+        artpec6_pcie_deassert_core_reset(artpec6_pcie);
+        artpec6_pcie_wait_for_phy(artpec6_pcie);
+        artpec6_pcie_set_nfts(artpec6_pcie);
+
+        for (bar = BAR_0; bar <= BAR_5; bar++)
+                dw_pcie_ep_reset_bar(pci, bar);
+}
+
+static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
+                                  enum pci_epc_irq_type type, u8 interrupt_num)
+{
+        struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+
+        switch (type) {
+        case PCI_EPC_IRQ_LEGACY:
+                dev_err(pci->dev, "EP cannot trigger legacy IRQs\n");
+                return -EINVAL;
+        case PCI_EPC_IRQ_MSI:
+                return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
+        default:
+                dev_err(pci->dev, "UNKNOWN IRQ type\n");
+        }
+
+        return 0;
+}
+
+static struct dw_pcie_ep_ops pcie_ep_ops = {
+        .ep_init = artpec6_pcie_ep_init,
+        .raise_irq = artpec6_pcie_raise_irq,
 };
 
+static int artpec6_add_pcie_ep(struct artpec6_pcie *artpec6_pcie,
+                               struct platform_device *pdev)
+{
+        int ret;
+        struct dw_pcie_ep *ep;
+        struct resource *res;
+        struct device *dev = &pdev->dev;
+        struct dw_pcie *pci = artpec6_pcie->pci;
+
+        ep = &pci->ep;
+        ep->ops = &pcie_ep_ops;
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
+        pci->dbi_base2 = devm_ioremap(dev, res->start, resource_size(res));
+        if (!pci->dbi_base2)
+                return -ENOMEM;
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
+        if (!res)
+                return -EINVAL;
+
+        ep->phys_base = res->start;
+        ep->addr_size = resource_size(res);
+
+        ret = dw_pcie_ep_init(ep);
+        if (ret) {
+                dev_err(dev, "failed to initialize endpoint\n");
+                return ret;
+        }
+
+        return 0;
+}
+
 static int artpec6_pcie_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
@@ -242,6 +509,18 @@ static int artpec6_pcie_probe(struct platform_device *pdev)
         struct resource *dbi_base;
         struct resource *phy_base;
         int ret;
+        const struct of_device_id *match;
+        const struct artpec_pcie_of_data *data;
+        enum artpec_pcie_variants variant;
+        enum dw_pcie_device_mode mode;
+
+        match = of_match_device(artpec6_pcie_of_match, dev);
+        if (!match)
+                return -EINVAL;
+
+        data = (struct artpec_pcie_of_data *)match->data;
+        variant = (enum artpec_pcie_variants)data->variant;
+        mode = (enum dw_pcie_device_mode)data->mode;
 
         artpec6_pcie = devm_kzalloc(dev, sizeof(*artpec6_pcie), GFP_KERNEL);
         if (!artpec6_pcie)
@@ -255,6 +534,8 @@ static int artpec6_pcie_probe(struct platform_device *pdev)
         pci->ops = &dw_pcie_ops;
 
         artpec6_pcie->pci = pci;
+        artpec6_pcie->variant = variant;
+        artpec6_pcie->mode = mode;
 
         dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
         pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
@@ -274,15 +555,73 @@ static int artpec6_pcie_probe(struct platform_device *pdev)
 
         platform_set_drvdata(pdev, artpec6_pcie);
 
-        ret = artpec6_add_pcie_port(artpec6_pcie, pdev);
-        if (ret < 0)
-                return ret;
+        switch (artpec6_pcie->mode) {
+        case DW_PCIE_RC_TYPE:
+                if (!IS_ENABLED(CONFIG_PCIE_ARTPEC6_HOST))
+                        return -ENODEV;
+
+                ret = artpec6_add_pcie_port(artpec6_pcie, pdev);
+                if (ret < 0)
+                        return ret;
+                break;
+        case DW_PCIE_EP_TYPE: {
+                u32 val;
+
+                if (!IS_ENABLED(CONFIG_PCIE_ARTPEC6_EP))
+                        return -ENODEV;
+
+                val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
+                val &= ~PCIECFG_DEVICE_TYPE_MASK;
+                artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
+                ret = artpec6_add_pcie_ep(artpec6_pcie, pdev);
+                if (ret < 0)
+                        return ret;
+                break;
+        }
+        default:
+                dev_err(dev, "INVALID device type %d\n", artpec6_pcie->mode);
+        }
 
         return 0;
 }
 
+static const struct artpec_pcie_of_data artpec6_pcie_rc_of_data = {
+        .variant = ARTPEC6,
+        .mode = DW_PCIE_RC_TYPE,
+};
+
+static const struct artpec_pcie_of_data artpec6_pcie_ep_of_data = {
+        .variant = ARTPEC6,
+        .mode = DW_PCIE_EP_TYPE,
+};
+
+static const struct artpec_pcie_of_data artpec7_pcie_rc_of_data = {
+        .variant = ARTPEC7,
+        .mode = DW_PCIE_RC_TYPE,
+};
+
+static const struct artpec_pcie_of_data artpec7_pcie_ep_of_data = {
+        .variant = ARTPEC7,
+        .mode = DW_PCIE_EP_TYPE,
+};
+
 static const struct of_device_id artpec6_pcie_of_match[] = {
-        { .compatible = "axis,artpec6-pcie", },
+        {
+                .compatible = "axis,artpec6-pcie",
+                .data = &artpec6_pcie_rc_of_data,
+        },
+        {
+                .compatible = "axis,artpec6-pcie-ep",
+                .data = &artpec6_pcie_ep_of_data,
+        },
+        {
+                .compatible = "axis,artpec7-pcie",
+                .data = &artpec7_pcie_rc_of_data,
+        },
+        {
+                .compatible = "axis,artpec7-pcie-ep",
+                .data = &artpec7_pcie_ep_of_data,
+        },
         {},
 };
 
diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
index d53d5f168363..3a6feeff5f5b 100644
--- a/drivers/pci/dwc/pcie-designware-ep.c
+++ b/drivers/pci/dwc/pcie-designware-ep.c
@@ -1,20 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
 /**
  * Synopsys DesignWare PCIe Endpoint controller driver
  *
  * Copyright (C) 2017 Texas Instruments
  * Author: Kishon Vijay Abraham I <kishon@ti.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 of
- * the License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #include <linux/of.h>
@@ -30,21 +19,24 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
         pci_epc_linkup(epc);
 }
 
-static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
+void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
 {
         u32 reg;
 
         reg = PCI_BASE_ADDRESS_0 + (4 * bar);
+        dw_pcie_dbi_ro_wr_en(pci);
         dw_pcie_writel_dbi2(pci, reg, 0x0);
         dw_pcie_writel_dbi(pci, reg, 0x0);
+        dw_pcie_dbi_ro_wr_dis(pci);
 }
 
-static int dw_pcie_ep_write_header(struct pci_epc *epc,
+static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
                                    struct pci_epf_header *hdr)
 {
         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 
+        dw_pcie_dbi_ro_wr_en(pci);
         dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid);
         dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid);
         dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid);
@@ -58,6 +50,7 @@ static int dw_pcie_ep_write_header(struct pci_epc *epc,
         dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id);
         dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN,
                            hdr->interrupt_pin);
+        dw_pcie_dbi_ro_wr_dis(pci);
 
         return 0;
 }
@@ -70,8 +63,7 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
         u32 free_win;
         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 
-        free_win = find_first_zero_bit(&ep->ib_window_map,
-                                       sizeof(ep->ib_window_map));
+        free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
         if (free_win >= ep->num_ib_windows) {
                 dev_err(pci->dev, "no free inbound window\n");
                 return -EINVAL;
@@ -85,7 +77,7 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
         }
 
         ep->bar_to_atu[bar] = free_win;
-        set_bit(free_win, &ep->ib_window_map);
+        set_bit(free_win, ep->ib_window_map);
 
         return 0;
 }
@@ -96,8 +88,7 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr,
         u32 free_win;
         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 
-        free_win = find_first_zero_bit(&ep->ob_window_map,
-                                       sizeof(ep->ob_window_map));
+        free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows);
         if (free_win >= ep->num_ob_windows) {
                 dev_err(pci->dev, "no free outbound window\n");
                 return -EINVAL;
@@ -106,13 +97,14 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr,
         dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
                                   phys_addr, pci_addr, size);
 
-        set_bit(free_win, &ep->ob_window_map);
+        set_bit(free_win, ep->ob_window_map);
         ep->outbound_addr[free_win] = phys_addr;
 
         return 0;
 }
 
-static void dw_pcie_ep_clear_bar(struct pci_epc *epc, enum pci_barno bar)
+static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
+                                 enum pci_barno bar)
 {
         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -121,10 +113,11 @@ static void dw_pcie_ep_clear_bar(struct pci_epc *epc, enum pci_barno bar)
         dw_pcie_ep_reset_bar(pci, bar);
 
         dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
-        clear_bit(atu_index, &ep->ib_window_map);
+        clear_bit(atu_index, ep->ib_window_map);
 }
 
-static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar,
+static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
+                              enum pci_barno bar,
                               dma_addr_t bar_phys, size_t size, int flags)
 {
         int ret;
@@ -142,8 +135,10 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar,
         if (ret)
                 return ret;
 
+        dw_pcie_dbi_ro_wr_en(pci);
         dw_pcie_writel_dbi2(pci, reg, size - 1);
         dw_pcie_writel_dbi(pci, reg, flags);
+        dw_pcie_dbi_ro_wr_dis(pci);
 
         return 0;
 }
@@ -163,7 +158,8 @@ static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr,
         return -EINVAL;
 }
 
-static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, phys_addr_t addr)
+static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no,
+                                  phys_addr_t addr)
 {
         int ret;
         u32 atu_index;
@@ -175,10 +171,11 @@ static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, phys_addr_t addr)
                 return;
 
         dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
-        clear_bit(atu_index, &ep->ob_window_map);
+        clear_bit(atu_index, ep->ob_window_map);
 }
 
-static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr,
+static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
+                               phys_addr_t addr,
                                u64 pci_addr, size_t size)
 {
         int ret;
@@ -194,39 +191,37 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr,
         return 0;
 }
 
-static int dw_pcie_ep_get_msi(struct pci_epc *epc)
+static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
 {
         int val;
-        u32 lower_addr;
-        u32 upper_addr;
         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 
-        val = dw_pcie_readb_dbi(pci, MSI_MESSAGE_CONTROL);
-        val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
-
-        lower_addr = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_L32);
-        upper_addr = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_U32);
-
-        if (!(lower_addr || upper_addr))
+        val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
+        if (!(val & MSI_CAP_MSI_EN_MASK))
                 return -EINVAL;
 
+        val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
         return val;
 }
 
-static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
+static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 encode_int)
 {
         int val;
         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 
-        val = (encode_int << MSI_CAP_MMC_SHIFT);
+        val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
+        val &= ~MSI_CAP_MMC_MASK;
+        val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
+        dw_pcie_dbi_ro_wr_en(pci);
         dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
+        dw_pcie_dbi_ro_wr_dis(pci);
 
         return 0;
 }
 
-static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
+static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
                                 enum pci_epc_irq_type type, u8 interrupt_num)
 {
         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
@@ -234,7 +229,7 @@ static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
         if (!ep->ops->raise_irq)
                 return -EINVAL;
 
-        return ep->ops->raise_irq(ep, type, interrupt_num);
+        return ep->ops->raise_irq(ep, func_no, type, interrupt_num);
 }
 
 static void dw_pcie_ep_stop(struct pci_epc *epc)
@@ -272,10 +267,48 @@ static const struct pci_epc_ops epc_ops = {
         .stop                   = dw_pcie_ep_stop,
 };
 
+int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
+                             u8 interrupt_num)
+{
+        struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+        struct pci_epc *epc = ep->epc;
+        u16 msg_ctrl, msg_data;
+        u32 msg_addr_lower, msg_addr_upper;
+        u64 msg_addr;
+        bool has_upper;
+        int ret;
+
+        /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
+        msg_ctrl = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
+        has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
+        msg_addr_lower = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_L32);
+        if (has_upper) {
+                msg_addr_upper = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_U32);
+                msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_64);
+        } else {
+                msg_addr_upper = 0;
+                msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_32);
+        }
+        msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
+        ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
+                                  epc->mem->page_size);
+        if (ret)
+                return ret;
+
+        writel(msg_data | (interrupt_num - 1), ep->msi_mem);
+
+        dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
+
+        return 0;
+}
+
 void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
 {
         struct pci_epc *epc = ep->epc;
 
+        pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
+                              epc->mem->page_size);
+
         pci_epc_mem_exit(epc);
 }
 
@@ -298,12 +331,32 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
                 dev_err(dev, "unable to read *num-ib-windows* property\n");
                 return ret;
         }
+        if (ep->num_ib_windows > MAX_IATU_IN) {
+                dev_err(dev, "invalid *num-ib-windows*\n");
+                return -EINVAL;
+        }
 
         ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
         if (ret < 0) {
                 dev_err(dev, "unable to read *num-ob-windows* property\n");
                 return ret;
         }
+        if (ep->num_ob_windows > MAX_IATU_OUT) {
+                dev_err(dev, "invalid *num-ob-windows*\n");
+                return -EINVAL;
+        }
+
+        ep->ib_window_map = devm_kzalloc(dev, sizeof(long) *
+                                         BITS_TO_LONGS(ep->num_ib_windows),
+                                         GFP_KERNEL);
+        if (!ep->ib_window_map)
+                return -ENOMEM;
+
+        ep->ob_window_map = devm_kzalloc(dev, sizeof(long) *
+                                         BITS_TO_LONGS(ep->num_ob_windows),
+                                         GFP_KERNEL);
+        if (!ep->ob_window_map)
+                return -ENOMEM;
 
         addr = devm_kzalloc(dev, sizeof(phys_addr_t) * ep->num_ob_windows,
                             GFP_KERNEL);
@@ -331,6 +384,13 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
                 return ret;
         }
 
+        ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
+                                             epc->mem->page_size);
+        if (!ep->msi_mem) {
+                dev_err(dev, "Failed to reserve memory for MSI\n");
+                return -ENOMEM;
+        }
+
         ep->epc = epc;
         epc_set_drvdata(epc, ep);
         dw_pcie_setup(pci);
diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index 81e2157a7cfb..8de2d5c69b1d 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Synopsys DesignWare PCIe host controller driver
  *
@@ -5,10 +6,6 @@
  *              http://www.samsung.com
  *
  * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include <linux/irqdomain.h>
@@ -83,10 +80,19 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
 
 void dw_pcie_msi_init(struct pcie_port *pp)
 {
+        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+        struct device *dev = pci->dev;
+        struct page *page;
         u64 msi_target;
 
-        pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
-        msi_target = virt_to_phys((void *)pp->msi_data);
+        page = alloc_page(GFP_KERNEL);
+        pp->msi_data = dma_map_page(dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
+        if (dma_mapping_error(dev, pp->msi_data)) {
+                dev_err(dev, "failed to map MSI data\n");
+                __free_page(page);
+                return;
+        }
+        msi_target = (u64)pp->msi_data;
 
         /* program the msi_data */
         dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
@@ -187,7 +193,7 @@ static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos)
         if (pp->ops->get_msi_addr)
                 msi_target = pp->ops->get_msi_addr(pp);
         else
-                msi_target = virt_to_phys((void *)pp->msi_data);
+                msi_target = (u64)pp->msi_data;
 
         msg.address_lo = (u32)(msi_target & 0xffffffff);
         msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff);
diff --git a/drivers/pci/dwc/pcie-designware-plat.c b/drivers/pci/dwc/pcie-designware-plat.c
index 168e2380f493..ebdf28bcd67d 100644
--- a/drivers/pci/dwc/pcie-designware-plat.c
+++ b/drivers/pci/dwc/pcie-designware-plat.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * PCIe RC driver for Synopsys DesignWare Core
  *
  * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
  *
  * Authors: Joao Pinto <Joao.Pinto@synopsys.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 #include <linux/clk.h>
 #include <linux/delay.h>
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 88abdddee2ad..1b7282e5b494 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Synopsys DesignWare PCIe host controller driver
  *
@@ -5,10 +6,6 @@
  *              http://www.samsung.com
  *
  * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include <linux/delay.h>
@@ -149,7 +146,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
         u32 retries, val;
 
         if (pci->ops->cpu_addr_fixup)
-                cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr);
+                cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
 
         if (pci->iatu_unroll_enabled) {
                 dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr,
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index e5d9d77b778e..11b13864a406 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Synopsys DesignWare PCIe host controller driver
  *
@@ -5,15 +6,12 @@
  *              http://www.samsung.com
  *
  * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #ifndef _PCIE_DESIGNWARE_H
 #define _PCIE_DESIGNWARE_H
 
+#include <linux/dma-mapping.h>
 #include <linux/irq.h>
 #include <linux/msi.h>
 #include <linux/pci.h>
@@ -100,10 +98,14 @@
 
 #define MSI_MESSAGE_CONTROL             0x52
 #define MSI_CAP_MMC_SHIFT               1
+#define MSI_CAP_MMC_MASK                (7 << MSI_CAP_MMC_SHIFT)
 #define MSI_CAP_MME_SHIFT               4
+#define MSI_CAP_MSI_EN_MASK             0x1
 #define MSI_CAP_MME_MASK                (7 << MSI_CAP_MME_SHIFT)
 #define MSI_MESSAGE_ADDR_L32            0x54
 #define MSI_MESSAGE_ADDR_U32            0x58
+#define MSI_MESSAGE_DATA_32             0x58
+#define MSI_MESSAGE_DATA_64             0x5C
 
 /*
  * Maximum number of MSI IRQs can be 256 per controller. But keep
@@ -113,6 +115,10 @@
 #define MAX_MSI_IRQS                    32
 #define MAX_MSI_CTRLS                   (MAX_MSI_IRQS / 32)
 
+/* Maximum number of inbound/outbound iATUs */
+#define MAX_IATU_IN                     256
+#define MAX_IATU_OUT                    256
+
 struct pcie_port;
 struct dw_pcie;
 struct dw_pcie_ep;
@@ -168,7 +174,7 @@ struct pcie_port {
         const struct dw_pcie_host_ops *ops;
         int                     msi_irq;
         struct irq_domain       *irq_domain;
-        unsigned long           msi_data;
+        dma_addr_t              msi_data;
         DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
 };
 
@@ -180,8 +186,8 @@ enum dw_pcie_as_type {
 
 struct dw_pcie_ep_ops {
         void    (*ep_init)(struct dw_pcie_ep *ep);
-        int     (*raise_irq)(struct dw_pcie_ep *ep, enum pci_epc_irq_type type,
-                             u8 interrupt_num);
+        int     (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
+                             enum pci_epc_irq_type type, u8 interrupt_num);
 };
 
 struct dw_pcie_ep {
@@ -192,14 +198,16 @@ struct dw_pcie_ep {
         size_t                  page_size;
         u8                      bar_to_atu[6];
         phys_addr_t             *outbound_addr;
-        unsigned long           ib_window_map;
-        unsigned long           ob_window_map;
+        unsigned long           *ib_window_map;
+        unsigned long           *ob_window_map;
         u32                     num_ib_windows;
         u32                     num_ob_windows;
+        void __iomem            *msi_mem;
+        phys_addr_t             msi_mem_phys;
 };
 
 struct dw_pcie_ops {
-        u64     (*cpu_addr_fixup)(u64 cpu_addr);
+        u64     (*cpu_addr_fixup)(struct dw_pcie *pcie, u64 cpu_addr);
         u32     (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
                             size_t size);
         void    (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
@@ -334,6 +342,9 @@ static inline int dw_pcie_host_init(struct pcie_port *pp)
 void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
 int dw_pcie_ep_init(struct dw_pcie_ep *ep);
 void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
+int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
+                             u8 interrupt_num);
+void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
 #else
 static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
 {
@@ -347,5 +358,15 @@ static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
 {
 }
+
+static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
+                                           u8 interrupt_num)
+{
+        return 0;
+}
+
+static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
+{
+}
 #endif
 #endif /* _PCIE_DESIGNWARE_H */
diff --git a/drivers/pci/dwc/pcie-hisi.c b/drivers/pci/dwc/pcie-hisi.c
index a20179169e06..2658aaebb993 100644
--- a/drivers/pci/dwc/pcie-hisi.c
+++ b/drivers/pci/dwc/pcie-hisi.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * PCIe host controller driver for HiSilicon SoCs
  *
@@ -6,10 +7,6 @@
  * Authors: Zhou Wang <wangzhou1@hisilicon.com>
  *          Dacai Zhu <zhudacai@hisilicon.com>
  *          Gabriele Paoloni <gabriele.paoloni@huawei.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 #include <linux/interrupt.h>
 #include <linux/init.h>
diff --git a/drivers/pci/dwc/pcie-histb.c b/drivers/pci/dwc/pcie-histb.c
index 33b01b734d7d..70b5c0b108bf 100644
--- a/drivers/pci/dwc/pcie-histb.c
+++ b/drivers/pci/dwc/pcie-histb.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * PCIe host controller driver for HiSilicon STB SoCs
  *
@@ -5,10 +6,6 @@
  *
  * Authors: Ruqiang Ju <juruqiang@hisilicon.com>
  *          Jianguo Sun <sunjianguo1@huawei.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/pci/dwc/pcie-kirin.c b/drivers/pci/dwc/pcie-kirin.c
index dc3033cf3c19..13d839bd6160 100644
--- a/drivers/pci/dwc/pcie-kirin.c
+++ b/drivers/pci/dwc/pcie-kirin.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * PCIe host controller driver for Kirin Phone SoCs
  *
@@ -5,10 +6,6 @@
  *              http://www.huawei.com
  *
  * Author: Xiaowei Song <songxiaowei@huawei.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include <asm/compiler.h>
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index ce7ba5b7552a..6310c66e265c 100644
--- a/drivers/pci/dwc/pcie-qcom.c
+++ b/drivers/pci/dwc/pcie-qcom.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Qualcomm PCIe root complex driver
  *
@@ -5,15 +6,6 @@
  * Copyright 2015 Linaro Limited.
  *
  * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/clk.h>
@@ -171,7 +163,7 @@ struct qcom_pcie {
         union qcom_pcie_resources res;
         struct phy *phy;
         struct gpio_desc *reset;
-        struct qcom_pcie_ops *ops;
+        const struct qcom_pcie_ops *ops;
 };
 
 #define to_qcom_pcie(x)         dev_get_drvdata((x)->dev)
@@ -1234,7 +1226,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
 
         pcie->pci = pci;
 
-        pcie->ops = (struct qcom_pcie_ops *)of_device_get_match_data(dev);
+        pcie->ops = of_device_get_match_data(dev);
 
         pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_LOW);
         if (IS_ERR(pcie->reset))
diff --git a/drivers/pci/dwc/pcie-spear13xx.c b/drivers/pci/dwc/pcie-spear13xx.c
index 709189d23b31..ecb58f7b7566 100644
--- a/drivers/pci/dwc/pcie-spear13xx.c
+++ b/drivers/pci/dwc/pcie-spear13xx.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
  *
@@ -6,10 +7,6 @@
  * Copyright (C) 2010-2014 ST Microelectronics
  * Pratyush Anand <pratyush.anand@gmail.com>
  * Mohit Kumar <mohit.kumar.dhaka@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/pci/ecam.c b/drivers/pci/ecam.c
index c228a2eb7faa..1a81af0ba961 100644
--- a/drivers/pci/ecam.c
+++ b/drivers/pci/ecam.c
@@ -1,17 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright 2016 Broadcom
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, version 2, as
- * published by the Free Software Foundation (the "GPL").
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License version 2 (GPLv2) for more details.
- *
- * You should have received a copy of the GNU General Public License
- * version 2 (GPLv2) along with this source code.
  */
 
 #include <linux/device.h>
diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
index c09623ca8c3b..d1e7e4199432 100644
--- a/drivers/pci/endpoint/Kconfig
+++ b/drivers/pci/endpoint/Kconfig
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
 #
 # PCI Endpoint Support
 #
diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile
index 1041f80a4645..95b2fe47e3b0 100644
--- a/drivers/pci/endpoint/Makefile
+++ b/drivers/pci/endpoint/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
 #
 # Makefile for PCI Endpoint Support
 #
diff --git a/drivers/pci/endpoint/functions/Kconfig b/drivers/pci/endpoint/functions/Kconfig
index 2942066607e0..8820d0f7ec77 100644
--- a/drivers/pci/endpoint/functions/Kconfig
+++ b/drivers/pci/endpoint/functions/Kconfig
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
 #
 # PCI Endpoint Functions
 #
diff --git a/drivers/pci/endpoint/functions/Makefile b/drivers/pci/endpoint/functions/Makefile
index 6d94a4801838..d6fafff080e2 100644
--- a/drivers/pci/endpoint/functions/Makefile
+++ b/drivers/pci/endpoint/functions/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
 #
 # Makefile for PCI Endpoint Functions
 #
diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index f9308c2f22e6..64d8a17f8094 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -1,20 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
 /**
  * Test driver to test endpoint functionality
  *
  * Copyright (C) 2017 Texas Instruments
  * Author: Kishon Vijay Abraham I <kishon@ti.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 of
- * the License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #include <linux/crc32.h>
@@ -104,7 +93,8 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test)
                 goto err;
         }
 
-        ret = pci_epc_map_addr(epc, src_phys_addr, reg->src_addr, reg->size);
+        ret = pci_epc_map_addr(epc, epf->func_no, src_phys_addr, reg->src_addr,
+                               reg->size);
         if (ret) {
                 dev_err(dev, "failed to map source address\n");
                 reg->status = STATUS_SRC_ADDR_INVALID;
@@ -119,7 +109,8 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test)
                 goto err_src_map_addr;
         }
 
-        ret = pci_epc_map_addr(epc, dst_phys_addr, reg->dst_addr, reg->size);
+        ret = pci_epc_map_addr(epc, epf->func_no, dst_phys_addr, reg->dst_addr,
+                               reg->size);
         if (ret) {
                 dev_err(dev, "failed to map destination address\n");
                 reg->status = STATUS_DST_ADDR_INVALID;
@@ -128,13 +119,13 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test)
 
         memcpy(dst_addr, src_addr, reg->size);
 
-        pci_epc_unmap_addr(epc, dst_phys_addr);
+        pci_epc_unmap_addr(epc, epf->func_no, dst_phys_addr);
 
 err_dst_addr:
         pci_epc_mem_free_addr(epc, dst_phys_addr, dst_addr, reg->size);
 
 err_src_map_addr:
-        pci_epc_unmap_addr(epc, src_phys_addr);
+        pci_epc_unmap_addr(epc, epf->func_no, src_phys_addr);
 
 err_src_addr:
         pci_epc_mem_free_addr(epc, src_phys_addr, src_addr, reg->size);
@@ -164,7 +155,8 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test)
                 goto err;
         }
 
-        ret = pci_epc_map_addr(epc, phys_addr, reg->src_addr, reg->size);
+        ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->src_addr,
+                               reg->size);
         if (ret) {
                 dev_err(dev, "failed to map address\n");
                 reg->status = STATUS_SRC_ADDR_INVALID;
@@ -186,7 +178,7 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test)
         kfree(buf);
 
 err_map_addr:
-        pci_epc_unmap_addr(epc, phys_addr);
+        pci_epc_unmap_addr(epc, epf->func_no, phys_addr);
 
 err_addr:
         pci_epc_mem_free_addr(epc, phys_addr, src_addr, reg->size);
@@ -215,7 +207,8 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test)
                 goto err;
         }
 
-        ret = pci_epc_map_addr(epc, phys_addr, reg->dst_addr, reg->size);
+        ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->dst_addr,
+                               reg->size);
         if (ret) {
                 dev_err(dev, "failed to map address\n");
                 reg->status = STATUS_DST_ADDR_INVALID;
@@ -242,7 +235,7 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test)
         kfree(buf);
 
 err_map_addr:
-        pci_epc_unmap_addr(epc, phys_addr);
+        pci_epc_unmap_addr(epc, epf->func_no, phys_addr);
 
 err_addr:
         pci_epc_mem_free_addr(epc, phys_addr, dst_addr, reg->size);
@@ -260,11 +253,11 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test, u8 irq)
         struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
 
         reg->status |= STATUS_IRQ_RAISED;
-        msi_count = pci_epc_get_msi(epc);
+        msi_count = pci_epc_get_msi(epc, epf->func_no);
         if (irq > msi_count || msi_count <= 0)
-                pci_epc_raise_irq(epc, PCI_EPC_IRQ_LEGACY, 0);
+                pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_LEGACY, 0);
         else
-                pci_epc_raise_irq(epc, PCI_EPC_IRQ_MSI, irq);
+                pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSI, irq);
 }
 
 static void pci_epf_test_cmd_handler(struct work_struct *work)
@@ -291,7 +284,7 @@ static void pci_epf_test_cmd_handler(struct work_struct *work)
 
         if (command & COMMAND_RAISE_LEGACY_IRQ) {
                 reg->status = STATUS_IRQ_RAISED;
-                pci_epc_raise_irq(epc, PCI_EPC_IRQ_LEGACY, 0);
+                pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_LEGACY, 0);
                 goto reset_handler;
         }
 
@@ -326,11 +319,11 @@ static void pci_epf_test_cmd_handler(struct work_struct *work)
         }
 
         if (command & COMMAND_RAISE_MSI_IRQ) {
-                msi_count = pci_epc_get_msi(epc);
+                msi_count = pci_epc_get_msi(epc, epf->func_no);
                 if (irq > msi_count || msi_count <= 0)
                         goto reset_handler;
                 reg->status = STATUS_IRQ_RAISED;
-                pci_epc_raise_irq(epc, PCI_EPC_IRQ_MSI, irq);
+                pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSI, irq);
                 goto reset_handler;
         }
 
@@ -358,7 +351,7 @@ static void pci_epf_test_unbind(struct pci_epf *epf)
         for (bar = BAR_0; bar <= BAR_5; bar++) {
                 if (epf_test->reg[bar]) {
                         pci_epf_free_space(epf, epf_test->reg[bar], bar);
-                        pci_epc_clear_bar(epc, bar);
+                        pci_epc_clear_bar(epc, epf->func_no, bar);
                 }
         }
 }
@@ -380,7 +373,8 @@ static int pci_epf_test_set_bar(struct pci_epf *epf)
 
         for (bar = BAR_0; bar <= BAR_5; bar++) {
                 epf_bar = &epf->bar[bar];
-                ret = pci_epc_set_bar(epc, bar, epf_bar->phys_addr,
+                ret = pci_epc_set_bar(epc, epf->func_no, bar,
+                                      epf_bar->phys_addr,
                                       epf_bar->size, flags);
                 if (ret) {
                         pci_epf_free_space(epf, epf_test->reg[bar], bar);
@@ -433,7 +427,7 @@ static int pci_epf_test_bind(struct pci_epf *epf)
         if (WARN_ON_ONCE(!epc))
                 return -EINVAL;
 
-        ret = pci_epc_write_header(epc, header);
+        ret = pci_epc_write_header(epc, epf->func_no, header);
         if (ret) {
                 dev_err(dev, "configuration header write failed\n");
                 return ret;
@@ -447,7 +441,7 @@ static int pci_epf_test_bind(struct pci_epf *epf)
         if (ret)
                 return ret;
 
-        ret = pci_epc_set_msi(epc, epf->msi_interrupts);
+        ret = pci_epc_set_msi(epc, epf->func_no, epf->msi_interrupts);
         if (ret)
                 return ret;
 
diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-ep-cfs.c
index 4f74386c1ced..018ea3433cb5 100644
--- a/drivers/pci/endpoint/pci-ep-cfs.c
+++ b/drivers/pci/endpoint/pci-ep-cfs.c
@@ -1,35 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
 /**
  * configfs to configure the PCI endpoint
  *
  * Copyright (C) 2017 Texas Instruments
  * Author: Kishon Vijay Abraham I <kishon@ti.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 of
- * the License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #include <linux/module.h>
+#include <linux/idr.h>
 #include <linux/slab.h>
 
 #include <linux/pci-epc.h>
 #include <linux/pci-epf.h>
 #include <linux/pci-ep-cfs.h>
 
+static DEFINE_IDR(functions_idr);
+static DEFINE_MUTEX(functions_mutex);
 static struct config_group *functions_group;
 static struct config_group *controllers_group;
 
 struct pci_epf_group {
         struct config_group group;
         struct pci_epf *epf;
+        int index;
 };
 
 struct pci_epc_group {
@@ -97,22 +90,23 @@ static int pci_epc_epf_link(struct config_item *epc_item,
 {
         int ret;
         u32 func_no = 0;
-        struct pci_epc *epc;
-        struct pci_epf *epf;
         struct pci_epf_group *epf_group = to_pci_epf_group(epf_item);
         struct pci_epc_group *epc_group = to_pci_epc_group(epc_item);
-
-        epc = epc_group->epc;
-        epf = epf_group->epf;
-        ret = pci_epc_add_epf(epc, epf);
-        if (ret)
-                goto err_add_epf;
+        struct pci_epc *epc = epc_group->epc;
+        struct pci_epf *epf = epf_group->epf;
 
         func_no = find_first_zero_bit(&epc_group->function_num_map,
-                                      sizeof(epc_group->function_num_map));
+                                      BITS_PER_LONG);
+        if (func_no >= BITS_PER_LONG)
+                return -EINVAL;
+
         set_bit(func_no, &epc_group->function_num_map);
         epf->func_no = func_no;
 
+        ret = pci_epc_add_epf(epc, epf);
+        if (ret)
+                goto err_add_epf;
+
         ret = pci_epf_bind(epf);
         if (ret)
                 goto err_epf_bind;
@@ -353,6 +347,9 @@ static void pci_epf_release(struct config_item *item)
 {
         struct pci_epf_group *epf_group = to_pci_epf_group(item);
 
+        mutex_lock(&functions_mutex);
+        idr_remove(&functions_idr, epf_group->index);
+        mutex_unlock(&functions_mutex);
         pci_epf_destroy(epf_group->epf);
         kfree(epf_group);
 }
@@ -372,22 +369,57 @@ static struct config_group *pci_epf_make(struct config_group *group,
 {
         struct pci_epf_group *epf_group;
         struct pci_epf *epf;
+        char *epf_name;
+        int index, err;
 
         epf_group = kzalloc(sizeof(*epf_group), GFP_KERNEL);
         if (!epf_group)
                 return ERR_PTR(-ENOMEM);
 
+        mutex_lock(&functions_mutex);
+        index = idr_alloc(&functions_idr, epf_group, 0, 0, GFP_KERNEL);
+        mutex_unlock(&functions_mutex);
+        if (index < 0) {
+                err = index;
+                goto free_group;
+        }
+
+        epf_group->index = index;
+
         config_group_init_type_name(&epf_group->group, name, &pci_epf_type);
 
-        epf = pci_epf_create(group->cg_item.ci_name);
+        epf_name = kasprintf(GFP_KERNEL, "%s.%d",
+                             group->cg_item.ci_name, epf_group->index);
+        if (!epf_name) {
+                err = -ENOMEM;
+                goto remove_idr;
+        }
+
+        epf = pci_epf_create(epf_name);
         if (IS_ERR(epf)) {
                 pr_err("failed to create endpoint function device\n");
-                return ERR_PTR(-EINVAL);
+                err = -EINVAL;
+                goto free_name;
         }
 
         epf_group->epf = epf;
 
+        kfree(epf_name);
+
         return &epf_group->group;
+
+free_name:
+        kfree(epf_name);
+
+remove_idr:
+        mutex_lock(&functions_mutex);
+        idr_remove(&functions_idr, epf_group->index);
+        mutex_unlock(&functions_mutex);
+
+free_group:
+        kfree(epf_group);
+
+        return ERR_PTR(err);
 }
 
 static void pci_epf_drop(struct config_group *group, struct config_item *item)
diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index 42c2a1156325..e245bba0ab53 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -1,24 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
 /**
  * PCI Endpoint *Controller* (EPC) library
  *
  * Copyright (C) 2017 Texas Instruments
  * Author: Kishon Vijay Abraham I <kishon@ti.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 of
- * the License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #include <linux/device.h>
-#include <linux/dma-mapping.h>
 #include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/of_device.h>
@@ -142,25 +130,26 @@ EXPORT_SYMBOL_GPL(pci_epc_start);
 /**
  * pci_epc_raise_irq() - interrupt the host system
  * @epc: the EPC device which has to interrupt the host
+ * @func_no: the endpoint function number in the EPC device
  * @type: specify the type of interrupt; legacy or MSI
  * @interrupt_num: the MSI interrupt number
  *
  * Invoke to raise an MSI or legacy interrupt
  */
-int pci_epc_raise_irq(struct pci_epc *epc, enum pci_epc_irq_type type,
-                      u8 interrupt_num)
+int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
+                      enum pci_epc_irq_type type, u8 interrupt_num)
 {
         int ret;
         unsigned long flags;
 
-        if (IS_ERR(epc))
+        if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
                 return -EINVAL;
 
         if (!epc->ops->raise_irq)
                 return 0;
 
         spin_lock_irqsave(&epc->lock, flags);
-        ret = epc->ops->raise_irq(epc, type, interrupt_num);
+        ret = epc->ops->raise_irq(epc, func_no, type, interrupt_num);
         spin_unlock_irqrestore(&epc->lock, flags);
 
         return ret;
@@ -170,22 +159,23 @@ EXPORT_SYMBOL_GPL(pci_epc_raise_irq);
 /**
  * pci_epc_get_msi() - get the number of MSI interrupt numbers allocated
  * @epc: the EPC device to which MSI interrupts was requested
+ * @func_no: the endpoint function number in the EPC device
  *
  * Invoke to get the number of MSI interrupts allocated by the RC
  */
-int pci_epc_get_msi(struct pci_epc *epc)
+int pci_epc_get_msi(struct pci_epc *epc, u8 func_no)
 {
         int interrupt;
         unsigned long flags;
 
-        if (IS_ERR(epc))
+        if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
                 return 0;
 
         if (!epc->ops->get_msi)
                 return 0;
 
         spin_lock_irqsave(&epc->lock, flags);
-        interrupt = epc->ops->get_msi(epc);
+        interrupt = epc->ops->get_msi(epc, func_no);
         spin_unlock_irqrestore(&epc->lock, flags);
 
         if (interrupt < 0)
@@ -200,17 +190,18 @@ EXPORT_SYMBOL_GPL(pci_epc_get_msi);
 /**
  * pci_epc_set_msi() - set the number of MSI interrupt numbers required
  * @epc: the EPC device on which MSI has to be configured
+ * @func_no: the endpoint function number in the EPC device
  * @interrupts: number of MSI interrupts required by the EPF
  *
  * Invoke to set the required number of MSI interrupts.
  */
-int pci_epc_set_msi(struct pci_epc *epc, u8 interrupts)
+int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
 {
         int ret;
         u8 encode_int;
         unsigned long flags;
 
-        if (IS_ERR(epc))
+        if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
                 return -EINVAL;
 
         if (!epc->ops->set_msi)
@@ -219,7 +210,7 @@ int pci_epc_set_msi(struct pci_epc *epc, u8 interrupts)
         encode_int = order_base_2(interrupts);
 
         spin_lock_irqsave(&epc->lock, flags);
-        ret = epc->ops->set_msi(epc, encode_int);
+        ret = epc->ops->set_msi(epc, func_no, encode_int);
         spin_unlock_irqrestore(&epc->lock, flags);
 
         return ret;
@@ -229,22 +220,24 @@ EXPORT_SYMBOL_GPL(pci_epc_set_msi);
 /**
  * pci_epc_unmap_addr() - unmap CPU address from PCI address
  * @epc: the EPC device on which address is allocated
+ * @func_no: the endpoint function number in the EPC device
  * @phys_addr: physical address of the local system
  *
  * Invoke to unmap the CPU address from PCI address.
  */
-void pci_epc_unmap_addr(struct pci_epc *epc, phys_addr_t phys_addr)
+void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
+                        phys_addr_t phys_addr)
 {
         unsigned long flags;
 
-        if (IS_ERR(epc))
+        if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
                 return;
 
         if (!epc->ops->unmap_addr)
                 return;
 
         spin_lock_irqsave(&epc->lock, flags);
-        epc->ops->unmap_addr(epc, phys_addr);
+        epc->ops->unmap_addr(epc, func_no, phys_addr);
         spin_unlock_irqrestore(&epc->lock, flags);
 }
 EXPORT_SYMBOL_GPL(pci_epc_unmap_addr);
@@ -252,26 +245,27 @@ EXPORT_SYMBOL_GPL(pci_epc_unmap_addr);
 /**
  * pci_epc_map_addr() - map CPU address to PCI address
  * @epc: the EPC device on which address is allocated
+ * @func_no: the endpoint function number in the EPC device
  * @phys_addr: physical address of the local system
  * @pci_addr: PCI address to which the physical address should be mapped
  * @size: the size of the allocation
  *
  * Invoke to map CPU address with PCI address.
  */
-int pci_epc_map_addr(struct pci_epc *epc, phys_addr_t phys_addr,
-                     u64 pci_addr, size_t size)
+int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
+                     phys_addr_t phys_addr, u64 pci_addr, size_t size)
 {
         int ret;
         unsigned long flags;
 
-        if (IS_ERR(epc))
+        if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
                 return -EINVAL;
 
         if (!epc->ops->map_addr)
                 return 0;
 
         spin_lock_irqsave(&epc->lock, flags);
-        ret = epc->ops->map_addr(epc, phys_addr, pci_addr, size);
+        ret = epc->ops->map_addr(epc, func_no, phys_addr, pci_addr, size);
         spin_unlock_irqrestore(&epc->lock, flags);
 
         return ret;
@@ -281,22 +275,23 @@ EXPORT_SYMBOL_GPL(pci_epc_map_addr);
 /**
  * pci_epc_clear_bar() - reset the BAR
  * @epc: the EPC device for which the BAR has to be cleared
+ * @func_no: the endpoint function number in the EPC device
  * @bar: the BAR number that has to be reset
  *
  * Invoke to reset the BAR of the endpoint device.
  */
-void pci_epc_clear_bar(struct pci_epc *epc, int bar)
+void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, int bar)
 {
         unsigned long flags;
 
-        if (IS_ERR(epc))
+        if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
                 return;
 
         if (!epc->ops->clear_bar)
                 return;
 
         spin_lock_irqsave(&epc->lock, flags);
-        epc->ops->clear_bar(epc, bar);
+        epc->ops->clear_bar(epc, func_no, bar);
         spin_unlock_irqrestore(&epc->lock, flags);
 }
 EXPORT_SYMBOL_GPL(pci_epc_clear_bar);
@@ -304,26 +299,27 @@ EXPORT_SYMBOL_GPL(pci_epc_clear_bar);
 /**
  * pci_epc_set_bar() - configure BAR in order for host to assign PCI addr space
  * @epc: the EPC device on which BAR has to be configured
+ * @func_no: the endpoint function number in the EPC device
  * @bar: the BAR number that has to be configured
  * @size: the size of the addr space
  * @flags: specify memory allocation/io allocation/32bit address/64 bit address
  *
  * Invoke to configure the BAR of the endpoint device.
  */
-int pci_epc_set_bar(struct pci_epc *epc, enum pci_barno bar,
+int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, enum pci_barno bar,
                     dma_addr_t bar_phys, size_t size, int flags)
 {
         int ret;
         unsigned long irq_flags;
 
-        if (IS_ERR(epc))
+        if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
                 return -EINVAL;
 
         if (!epc->ops->set_bar)
                 return 0;
 
         spin_lock_irqsave(&epc->lock, irq_flags);
-        ret = epc->ops->set_bar(epc, bar, bar_phys, size, flags);
+        ret = epc->ops->set_bar(epc, func_no, bar, bar_phys, size, flags);
         spin_unlock_irqrestore(&epc->lock, irq_flags);
 
         return ret;
@@ -333,6 +329,7 @@ EXPORT_SYMBOL_GPL(pci_epc_set_bar);
 /**
  * pci_epc_write_header() - write standard configuration header
  * @epc: the EPC device to which the configuration header should be written
+ * @func_no: the endpoint function number in the EPC device
  * @header: standard configuration header fields
  *
  * Invoke to write the configuration header to the endpoint controller. Every
@@ -340,19 +337,20 @@ EXPORT_SYMBOL_GPL(pci_epc_set_bar);
  * configuration header would be written. The callback function should write
  * the header fields to this dedicated location.
  */
-int pci_epc_write_header(struct pci_epc *epc, struct pci_epf_header *header)
+int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
+                         struct pci_epf_header *header)
 {
         int ret;
         unsigned long flags;
 
-        if (IS_ERR(epc))
+        if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
                 return -EINVAL;
 
         if (!epc->ops->write_header)
                 return 0;
 
         spin_lock_irqsave(&epc->lock, flags);
-        ret = epc->ops->write_header(epc, header);
+        ret = epc->ops->write_header(epc, func_no, header);
         spin_unlock_irqrestore(&epc->lock, flags);
 
         return ret;
@@ -371,7 +369,6 @@ EXPORT_SYMBOL_GPL(pci_epc_write_header);
 int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf)
 {
         unsigned long flags;
-        struct device *dev = epc->dev.parent;
 
         if (epf->epc)
                 return -EBUSY;
@@ -383,12 +380,6 @@ int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf)
                 return -EINVAL;
 
         epf->epc = epc;
-        if (dev->of_node) {
-                of_dma_configure(&epf->dev, dev->of_node);
-        } else {
-                dma_set_coherent_mask(&epf->dev, epc->dev.coherent_dma_mask);
-                epf->dev.dma_mask = epc->dev.dma_mask;
-        }
 
         spin_lock_irqsave(&epc->lock, flags);
         list_add_tail(&epf->list, &epc->pci_epf);
@@ -503,9 +494,7 @@ __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
         INIT_LIST_HEAD(&epc->pci_epf);
 
         device_initialize(&epc->dev);
-        dma_set_coherent_mask(&epc->dev, dev->coherent_dma_mask);
         epc->dev.class = pci_epc_class;
-        epc->dev.dma_mask = dev->dma_mask;
         epc->dev.parent = dev;
         epc->ops = ops;
 
diff --git a/drivers/pci/endpoint/pci-epc-mem.c b/drivers/pci/endpoint/pci-epc-mem.c
index 83b7d5d3fc3e..2bf8bd1f0563 100644
--- a/drivers/pci/endpoint/pci-epc-mem.c
+++ b/drivers/pci/endpoint/pci-epc-mem.c
@@ -1,20 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
 /**
  * PCI Endpoint *Controller* Address Space Management
  *
  * Copyright (C) 2017 Texas Instruments
  * Author: Kishon Vijay Abraham I <kishon@ti.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 of
- * the License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #include <linux/io.h>
diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c
index ae1611a62808..766ce1dca2ec 100644
--- a/drivers/pci/endpoint/pci-epf-core.c
+++ b/drivers/pci/endpoint/pci-epf-core.c
@@ -1,20 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
 /**
  * PCI Endpoint *Function* (EPF) library
  *
  * Copyright (C) 2017 Texas Instruments
  * Author: Kishon Vijay Abraham I <kishon@ti.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 of
- * the License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #include <linux/device.h>
@@ -99,7 +88,7 @@ EXPORT_SYMBOL_GPL(pci_epf_bind);
  */
 void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar)
 {
-        struct device *dev = &epf->dev;
+        struct device *dev = epf->epc->dev.parent;
 
         if (!addr)
                 return;
@@ -122,7 +111,7 @@ EXPORT_SYMBOL_GPL(pci_epf_free_space);
 void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar)
 {
         void *space;
-        struct device *dev = &epf->dev;
+        struct device *dev = epf->epc->dev.parent;
         dma_addr_t phys_addr;
 
         if (size < 128)
diff --git a/drivers/pci/host-bridge.c b/drivers/pci/host-bridge.c
index add66236215c..ac8d81268296 100644
--- a/drivers/pci/host-bridge.c
+++ b/drivers/pci/host-bridge.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * host bridge related code
  */
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 38d12980db0f..a4ed7484d127 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
 menu "PCI host controller drivers"
         depends on PCI
 
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 34ec1d88f961..3b1059190867 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -34,6 +34,8 @@ obj-$(CONFIG_VMD) += vmd.o
 # ARM64 and use internal ifdefs to only build the pieces we need
 # depending on whether ACPI, the DT driver, or both are enabled.
 
+ifdef CONFIG_PCI
 obj-$(CONFIG_ARM64) += pci-thunder-ecam.o
 obj-$(CONFIG_ARM64) += pci-thunder-pem.o
 obj-$(CONFIG_ARM64) += pci-xgene.o
+endif
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 26ed0c08f209..b04d37b3c5de 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Driver for the Aardvark PCIe controller, used on Marvell Armada
  * 3700.
@@ -5,10 +6,6 @@
  * Copyright (C) 2016 Marvell
  *
  * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/delay.h>
diff --git a/drivers/pci/host/pci-host-common.c b/drivers/pci/host/pci-host-common.c
index 44a47d4f0b8f..5d028f53fdcd 100644
--- a/drivers/pci/host/pci-host-common.c
+++ b/drivers/pci/host/pci-host-common.c
@@ -1,18 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Generic PCI host driver common code
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- *
  * Copyright (C) 2014 ARM Limited
  *
  * Author: Will Deacon <will.deacon@arm.com>
@@ -24,50 +13,6 @@
 #include <linux/pci-ecam.h>
 #include <linux/platform_device.h>
 
-static int gen_pci_parse_request_of_pci_ranges(struct device *dev,
-                       struct list_head *resources, struct resource **bus_range)
-{
-        int err, res_valid = 0;
-        struct device_node *np = dev->of_node;
-        resource_size_t iobase;
-        struct resource_entry *win, *tmp;
-
-        err = of_pci_get_host_bridge_resources(np, 0, 0xff, resources, &iobase);
-        if (err)
-                return err;
-
-        err = devm_request_pci_bus_resources(dev, resources);
-        if (err)
-                return err;
-
-        resource_list_for_each_entry_safe(win, tmp, resources) {
-                struct resource *res = win->res;
-
-                switch (resource_type(res)) {
-                case IORESOURCE_IO:
-                        err = pci_remap_iospace(res, iobase);
-                        if (err) {
-                                dev_warn(dev, "error %d: failed to map resource %pR\n",
-                                         err, res);
-                                resource_list_destroy_entry(win);
-                        }
-                        break;
-                case IORESOURCE_MEM:
-                        res_valid |= !(res->flags & IORESOURCE_PREFETCH);
-                        break;
-                case IORESOURCE_BUS:
-                        *bus_range = res;
-                        break;
-                }
-        }
-
-        if (res_valid)
-                return 0;
-
-        dev_err(dev, "non-prefetchable memory resource required\n");
-        return -EINVAL;
-}
-
 static void gen_pci_unmap_cfg(void *ptr)
 {
         pci_ecam_free((struct pci_config_window *)ptr);
@@ -82,9 +27,9 @@ static struct pci_config_window *gen_pci_init(struct device *dev,
         struct pci_config_window *cfg;
 
         /* Parse our PCI ranges and request their resources */
-        err = gen_pci_parse_request_of_pci_ranges(dev, resources, &bus_range);
+        err = pci_parse_request_of_pci_ranges(dev, resources, &bus_range);
         if (err)
-                goto err_out;
+                return ERR_PTR(err);
 
         err = of_address_to_resource(dev->of_node, 0, &cfgres);
         if (err) {
@@ -116,7 +61,6 @@ int pci_host_common_probe(struct platform_device *pdev,
         const char *type;
         struct device *dev = &pdev->dev;
         struct device_node *np = dev->of_node;
-        struct pci_bus *bus, *child;
         struct pci_host_bridge *bridge;
         struct pci_config_window *cfg;
         struct list_head resources;
@@ -135,14 +79,13 @@ int pci_host_common_probe(struct platform_device *pdev,
         of_pci_check_probe_only();
 
         /* Parse and map our Configuration Space windows */
-        INIT_LIST_HEAD(&resources);
         cfg = gen_pci_init(dev, &resources, ops);
         if (IS_ERR(cfg))
                 return PTR_ERR(cfg);
 
         /* Do not reassign resources if probe only */
         if (!pci_has_flag(PCI_PROBE_ONLY))
-                pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);
+                pci_add_flags(PCI_REASSIGN_ALL_BUS);
 
         list_splice_init(&resources, &bridge->windows);
         bridge->dev.parent = dev;
@@ -152,29 +95,11 @@ int pci_host_common_probe(struct platform_device *pdev,
         bridge->map_irq = of_irq_parse_and_map_pci;
         bridge->swizzle_irq = pci_common_swizzle;
 
-        ret = pci_scan_root_bus_bridge(bridge);
+        ret = pci_host_probe(bridge);
         if (ret < 0) {
-                dev_err(dev, "Scanning root bridge failed");
+                pci_free_resource_list(&resources);
                 return ret;
         }
 
-        bus = bridge->bus;
-
-        /*
-         * We insert PCI resources into the iomem_resource and
-         * ioport_resource trees in either pci_bus_claim_resources()
-         * or pci_bus_assign_resources().
-         */
-        if (pci_has_flag(PCI_PROBE_ONLY)) {
-                pci_bus_claim_resources(bus);
-        } else {
-                pci_bus_size_bridges(bus);
-                pci_bus_assign_resources(bus);
-
-                list_for_each_entry(child, &bus->children, node)
-                        pcie_bus_configure_settings(child);
-        }
-
-        pci_bus_add_devices(bus);
         return 0;
 }
diff --git a/drivers/pci/host/pci-host-generic.c b/drivers/pci/host/pci-host-generic.c
index 2f05511ce718..45319ee3b484 100644
--- a/drivers/pci/host/pci-host-generic.c
+++ b/drivers/pci/host/pci-host-generic.c
@@ -1,19 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Simple, generic PCI host controller driver targetting firmware-initialised
  * systems and virtual machines (e.g. the PCI emulation provided by kvmtool).
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- *
  * Copyright (C) 2014 ARM Limited
  *
  * Author: Will Deacon <will.deacon@arm.com>
diff --git a/drivers/pci/host/pci-hyperv.c b/drivers/pci/host/pci-hyperv.c
index 6b8d060d07de..2faf38eab785 100644
--- a/drivers/pci/host/pci-hyperv.c
+++ b/drivers/pci/host/pci-hyperv.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) Microsoft Corporation.
  *
@@ -34,17 +35,6 @@
  * read and write handlers for config space must be aware of this mechanism.
  * Similarly, device setup and teardown involves messages sent to and from
  * the PCI back-end driver in Hyper-V.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
  */
 
 #include <linux/kernel.h>
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index 8d88f19dc171..5d4dccfc9d81 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * PCIe driver for Marvell Armada 370 and Armada XP SoCs
  *
  * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/drivers/pci/host/pci-rcar-gen2.c b/drivers/pci/host/pci-rcar-gen2.c
index e46de69f0380..a28370bb2b2a 100644
--- a/drivers/pci/host/pci-rcar-gen2.c
+++ b/drivers/pci/host/pci-rcar-gen2.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  *  pci-rcar-gen2: internal PCI bus support
  *
@@ -5,10 +6,6 @@
  * Copyright (C) 2013 Cogent Embedded, Inc.
  *
  * Author: Valentine Barshak <valentine.barshak@cogentembedded.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include <linux/delay.h>
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index f9d3960dc39f..dd9b3bcc41c3 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * PCIe host controller driver for Tegra SoCs
  *
@@ -10,20 +11,6 @@
  * Bits taken from arch/arm/mach-dove/pcie.c
  *
  * Author: Thierry Reding <treding@nvidia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  */
 
 #include <linux/clk.h>
@@ -269,11 +256,10 @@ struct tegra_pcie {
 
         void __iomem *pads;
         void __iomem *afi;
+        void __iomem *cfg;
         int irq;
 
-        struct list_head buses;
-        struct resource *cs;
-
+        struct resource cs;
         struct resource io;
         struct resource pio;
         struct resource mem;
@@ -322,7 +308,6 @@ struct tegra_pcie_port {
 };
 
 struct tegra_pcie_bus {
-        struct vm_struct *area;
         struct list_head list;
         unsigned int nr;
 };
@@ -362,109 +347,26 @@ static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
  *
  * Mapping the whole extended configuration space would require 256 MiB of
  * virtual address space, only a small part of which will actually be used.
- * To work around this, a 1 MiB of virtual addresses are allocated per bus
- * when the bus is first accessed. When the physical range is mapped, the
- * the bus number bits are hidden so that the extended register number bits
- * appear as bits [19:16]. Therefore the virtual mapping looks like this:
  *
- *    [19:16] extended register number
- *    [15:11] device number
- *    [10: 8] function number
- *    [ 7: 0] register number
- *
- * This is achieved by stitching together 16 chunks of 64 KiB of physical
- * address space via the MMU.
+ * To work around this, a 4 KiB region is used to generate the required
+ * configuration transaction with relevant B:D:F and register offset values.
+ * This is achieved by dynamically programming base address and size of
+ * AFI_AXI_BAR used for end point config space mapping to make sure that the
+ * address (access to which generates correct config transaction) falls in
+ * this 4 KiB region.
  */
-static unsigned long tegra_pcie_conf_offset(unsigned int devfn, int where)
-{
-        return ((where & 0xf00) << 8) | (PCI_SLOT(devfn) << 11) |
-               (PCI_FUNC(devfn) << 8) | (where & 0xfc);
-}
-
-static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie,
-                                                   unsigned int busnr)
-{
-        struct device *dev = pcie->dev;
-        pgprot_t prot = pgprot_noncached(PAGE_KERNEL);
-        phys_addr_t cs = pcie->cs->start;
-        struct tegra_pcie_bus *bus;
-        unsigned int i;
-        int err;
-
-        bus = kzalloc(sizeof(*bus), GFP_KERNEL);
-        if (!bus)
-                return ERR_PTR(-ENOMEM);
-
-        INIT_LIST_HEAD(&bus->list);
-        bus->nr = busnr;
-
-        /* allocate 1 MiB of virtual addresses */
-        bus->area = get_vm_area(SZ_1M, VM_IOREMAP);
-        if (!bus->area) {
-                err = -ENOMEM;
-                goto free;
-        }
-
-        /* map each of the 16 chunks of 64 KiB each */
-        for (i = 0; i < 16; i++) {
-                unsigned long virt = (unsigned long)bus->area->addr +
-                                     i * SZ_64K;
-                phys_addr_t phys = cs + i * SZ_16M + busnr * SZ_64K;
-
-                err = ioremap_page_range(virt, virt + SZ_64K, phys, prot);
-                if (err < 0) {
-                        dev_err(dev, "ioremap_page_range() failed: %d\n", err);
-                        goto unmap;
-                }
-        }
-
-        return bus;
-
-unmap:
-        vunmap(bus->area->addr);
-free:
-        kfree(bus);
-        return ERR_PTR(err);
-}
-
-static int tegra_pcie_add_bus(struct pci_bus *bus)
-{
-        struct pci_host_bridge *host = pci_find_host_bridge(bus);
-        struct tegra_pcie *pcie = pci_host_bridge_priv(host);
-        struct tegra_pcie_bus *b;
-
-        b = tegra_pcie_bus_alloc(pcie, bus->number);
-        if (IS_ERR(b))
-                return PTR_ERR(b);
-
-        list_add_tail(&b->list, &pcie->buses);
-
-        return 0;
-}
-
-static void tegra_pcie_remove_bus(struct pci_bus *child)
+static unsigned int tegra_pcie_conf_offset(u8 bus, unsigned int devfn,
+                                           unsigned int where)
 {
-        struct pci_host_bridge *host = pci_find_host_bridge(child);
-        struct tegra_pcie *pcie = pci_host_bridge_priv(host);
-        struct tegra_pcie_bus *bus, *tmp;
-
-        list_for_each_entry_safe(bus, tmp, &pcie->buses, list) {
-                if (bus->nr == child->number) {
-                        vunmap(bus->area->addr);
-                        list_del(&bus->list);
-                        kfree(bus);
-                        break;
-                }
-        }
+        return ((where & 0xf00) << 16) | (bus << 16) | (PCI_SLOT(devfn) << 11) |
+               (PCI_FUNC(devfn) << 8) | (where & 0xff);
 }
 
 static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,
                                         unsigned int devfn,
                                         int where)
 {
-        struct pci_host_bridge *host = pci_find_host_bridge(bus);
-        struct tegra_pcie *pcie = pci_host_bridge_priv(host);
-        struct device *dev = pcie->dev;
+        struct tegra_pcie *pcie = bus->sysdata;
         void __iomem *addr = NULL;
 
         if (bus->number == 0) {
@@ -478,19 +380,17 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,
                         }
                 }
         } else {
-                struct tegra_pcie_bus *b;
+                unsigned int offset;
+                u32 base;
 
-                list_for_each_entry(b, &pcie->buses, list)
-                        if (b->nr == bus->number)
-                                addr = (void __iomem *)b->area->addr;
+                offset = tegra_pcie_conf_offset(bus->number, devfn, where);
 
-                if (!addr) {
-                        dev_err(dev, "failed to map cfg. space for bus %u\n",
-                                bus->number);
-                        return NULL;
-                }
+                /* move 4 KiB window to offset within the FPCI region */
+                base = 0xfe100000 + ((offset & ~(SZ_4K - 1)) >> 8);
+                afi_writel(pcie, base, AFI_FPCI_BAR0);
 
-                addr += tegra_pcie_conf_offset(devfn, where);
+                /* move to correct offset within the 4 KiB page */
+                addr = pcie->cfg + (offset & (SZ_4K - 1));
         }
 
         return addr;
@@ -517,8 +417,6 @@ static int tegra_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
 }
 
 static struct pci_ops tegra_pcie_ops = {
-        .add_bus = tegra_pcie_add_bus,
-        .remove_bus = tegra_pcie_remove_bus,
         .map_bus = tegra_pcie_map_bus,
         .read = tegra_pcie_config_read,
         .write = tegra_pcie_config_write,
@@ -661,8 +559,7 @@ static int tegra_pcie_request_resources(struct tegra_pcie *pcie)
 
 static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
 {
-        struct pci_host_bridge *host = pci_find_host_bridge(pdev->bus);
-        struct tegra_pcie *pcie = pci_host_bridge_priv(host);
+        struct tegra_pcie *pcie = pdev->bus->sysdata;
         int irq;
 
         tegra_cpuidle_pcie_irqs_in_use();
@@ -743,12 +640,9 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
         u32 fpci_bar, size, axi_address;
 
         /* Bar 0: type 1 extended configuration space */
-        fpci_bar = 0xfe100000;
-        size = resource_size(pcie->cs);
-        axi_address = pcie->cs->start;
-        afi_writel(pcie, axi_address, AFI_AXI_BAR0_START);
+        size = resource_size(&pcie->cs);
+        afi_writel(pcie, pcie->cs.start, AFI_AXI_BAR0_START);
         afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
-        afi_writel(pcie, fpci_bar, AFI_FPCI_BAR0);
 
         /* Bar 1: downstream IO bar */
         fpci_bar = 0xfdfc0000;
@@ -1353,10 +1247,14 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
                 goto poweroff;
         }
 
-        pcie->cs = devm_request_mem_region(dev, res->start,
-                                           resource_size(res), res->name);
-        if (!pcie->cs) {
-                err = -EADDRNOTAVAIL;
+        pcie->cs = *res;
+
+        /* constrain configuration space to 4 KiB */
+        pcie->cs.end = pcie->cs.start + SZ_4K - 1;
+
+        pcie->cfg = devm_ioremap_resource(dev, &pcie->cs);
+        if (IS_ERR(pcie->cfg)) {
+                err = PTR_ERR(pcie->cfg);
                 goto poweroff;
         }
 
@@ -2345,9 +2243,9 @@ static int tegra_pcie_probe(struct platform_device *pdev)
                 return -ENOMEM;
 
         pcie = pci_host_bridge_priv(host);
+        host->sysdata = pcie;
 
         pcie->soc = of_device_get_match_data(dev);
-        INIT_LIST_HEAD(&pcie->buses);
         INIT_LIST_HEAD(&pcie->ports);
         pcie->dev = dev;
 
@@ -2382,7 +2280,6 @@ static int tegra_pcie_probe(struct platform_device *pdev)
 
         tegra_pcie_enable_ports(pcie);
 
-        pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);
         host->busnr = pcie->busn.start;
         host->dev.parent = &pdev->dev;
         host->ops = &tegra_pcie_ops;
diff --git a/drivers/pci/host/pci-thunder-ecam.c b/drivers/pci/host/pci-thunder-ecam.c
index fc0ca03f280e..32d1d7b81ef4 100644
--- a/drivers/pci/host/pci-thunder-ecam.c
+++ b/drivers/pci/host/pci-thunder-ecam.c
@@ -1,8 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * Copyright (C) 2015, 2016 Cavium, Inc.
  */
 
diff --git a/drivers/pci/host/pci-thunder-pem.c b/drivers/pci/host/pci-thunder-pem.c
index 6e066f8b74df..f127ce8bd4ef 100644
--- a/drivers/pci/host/pci-thunder-pem.c
+++ b/drivers/pci/host/pci-thunder-pem.c
@@ -1,16 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- *
  * Copyright (C) 2015 - 2016 Cavium, Inc.
  */
 
diff --git a/drivers/pci/host/pci-v3-semi.c b/drivers/pci/host/pci-v3-semi.c
index 02f6e1e3a421..7fef64869d19 100644
--- a/drivers/pci/host/pci-v3-semi.c
+++ b/drivers/pci/host/pci-v3-semi.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Support for V3 Semiconductor PCI Local Bus to PCI Bridge
  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
diff --git a/drivers/pci/host/pci-versatile.c b/drivers/pci/host/pci-versatile.c
index d417acab0ecf..5b3876f5312b 100644
--- a/drivers/pci/host/pci-versatile.c
+++ b/drivers/pci/host/pci-versatile.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright 2004 Koninklijke Philips Electronics NV
  *
  * Conversion to platform driver and DT:
  * Copyright 2014 Linaro Ltd.
  *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
  * 14/04/2005 Initial version, colin.king@philips.com
  */
 #include <linux/kernel.h>
@@ -202,7 +194,7 @@ static int versatile_pci_probe(struct platform_device *pdev)
         writel(0, versatile_cfg_base[0] + PCI_INTERRUPT_LINE);
 
         pci_add_flags(PCI_ENABLE_PROC_DOMAINS);
-        pci_add_flags(PCI_REASSIGN_ALL_BUS | PCI_REASSIGN_ALL_RSRC);
+        pci_add_flags(PCI_REASSIGN_ALL_BUS);
 
         list_splice_init(&pci_res, &bridge->windows);
         bridge->dev.parent = dev;
diff --git a/drivers/pci/host/pci-xgene-msi.c b/drivers/pci/host/pci-xgene-msi.c
index 1f42a202b021..df8e4bd5ddb2 100644
--- a/drivers/pci/host/pci-xgene-msi.c
+++ b/drivers/pci/host/pci-xgene-msi.c
@@ -1,19 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * APM X-Gene MSI Driver
  *
  * Copyright (c) 2014, Applied Micro Circuits Corporation
  * Author: Tanmay Inamdar <tinamdar@apm.com>
  *         Duc Dang <dhdang@apm.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 #include <linux/cpu.h>
 #include <linux/interrupt.h>
diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
index 465aa2a1b38d..0a0d7ee6d3c9 100644
--- a/drivers/pci/host/pci-xgene.c
+++ b/drivers/pci/host/pci-xgene.c
@@ -1,20 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /**
  * APM X-Gene PCIe Driver
  *
  * Copyright (c) 2014 Applied Micro Circuits Corporation.
  *
  * Author: Tanmay Inamdar <tinamdar@apm.com>.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
  */
 #include <linux/clk.h>
 #include <linux/delay.h>
@@ -668,7 +658,6 @@ static int xgene_pcie_probe(struct platform_device *pdev)
 
         bus = bridge->bus;
 
-        pci_scan_child_bus(bus);
         pci_assign_unassigned_bus_resources(bus);
         list_for_each_entry(child, &bus->children, node)
                 pcie_bus_configure_settings(child);
diff --git a/drivers/pci/host/pcie-altera-msi.c b/drivers/pci/host/pcie-altera-msi.c
index d8141f4865de..025ef7d9a046 100644
--- a/drivers/pci/host/pcie-altera-msi.c
+++ b/drivers/pci/host/pcie-altera-msi.c
@@ -1,21 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Altera PCIe MSI support
  *
  * Author: Ley Foon Tan <lftan@altera.com>
  *
  * Copyright Altera Corporation (C) 2013-2015. All rights reserved
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #include <linux/interrupt.h>
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index 5cc4f594d79a..2235f4760951 100644
--- a/drivers/pci/host/pcie-altera.c
+++ b/drivers/pci/host/pcie-altera.c
@@ -1,20 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright Altera Corporation (C) 2013-2015. All rights reserved
  *
  * Author: Ley Foon Tan <lftan@altera.com>
  * Description: Altera PCIe host controller driver
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #include <linux/delay.h>
diff --git a/drivers/pci/host/pcie-iproc-bcma.c b/drivers/pci/host/pcie-iproc-bcma.c
index f03d5e3612e9..603c83429cb3 100644
--- a/drivers/pci/host/pcie-iproc-bcma.c
+++ b/drivers/pci/host/pcie-iproc-bcma.c
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2015 Broadcom Corporation
  * Copyright (C) 2015 Hauke Mehrtens <hauke@hauke-m.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/kernel.h>
diff --git a/drivers/pci/host/pcie-iproc-msi.c b/drivers/pci/host/pcie-iproc-msi.c
index 990fc906d73d..9deb56989d72 100644
--- a/drivers/pci/host/pcie-iproc-msi.c
+++ b/drivers/pci/host/pcie-iproc-msi.c
@@ -1,14 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/interrupt.h>
diff --git a/drivers/pci/host/pcie-iproc-platform.c b/drivers/pci/host/pcie-iproc-platform.c
index a5073a921a04..e764a2a2693c 100644
--- a/drivers/pci/host/pcie-iproc-platform.c
+++ b/drivers/pci/host/pcie-iproc-platform.c
@@ -1,14 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/kernel.h>
@@ -92,6 +84,13 @@ static int iproc_pcie_pltfm_probe(struct platform_device *pdev)
                 pcie->need_ob_cfg = true;
         }
 
+        /*
+         * DT nodes are not used by all platforms that use the iProc PCIe
+         * core driver. For platforms that require explict inbound mapping
+         * configuration, "dma-ranges" would have been present in DT
+         */
+        pcie->need_ib_cfg = of_property_read_bool(np, "dma-ranges");
+
         /* PHY use is optional */
         pcie->phy = devm_phy_get(dev, "pcie-phy");
         if (IS_ERR(pcie->phy)) {
diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c
index 935909bbe5c4..cbb095481cdc 100644
--- a/drivers/pci/host/pcie-iproc.c
+++ b/drivers/pci/host/pcie-iproc.c
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
  * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/kernel.h>
@@ -1378,9 +1370,11 @@ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
                 }
         }
 
-        ret = iproc_pcie_map_dma_ranges(pcie);
-        if (ret && ret != -ENOENT)
-                goto err_power_off_phy;
+        if (pcie->need_ib_cfg) {
+                ret = iproc_pcie_map_dma_ranges(pcie);
+                if (ret && ret != -ENOENT)
+                        goto err_power_off_phy;
+        }
 
 #ifdef CONFIG_ARM
         pcie->sysdata.private_data = pcie;
diff --git a/drivers/pci/host/pcie-iproc.h b/drivers/pci/host/pcie-iproc.h
index a6b55cec9a66..d55f56a186cd 100644
--- a/drivers/pci/host/pcie-iproc.h
+++ b/drivers/pci/host/pcie-iproc.h
@@ -1,14 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (C) 2014-2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #ifndef _PCIE_IPROC_H
@@ -74,6 +66,7 @@ struct iproc_msi;
  * @ob: outbound mapping related parameters
  * @ob_map: outbound mapping related parameters specific to the controller
  *
+ * @need_ib_cfg: indicates SW needs to configure the inbound mapping window
  * @ib: inbound mapping related parameters
  * @ib_map: outbound mapping region related parameters
  *
@@ -101,6 +94,7 @@ struct iproc_pcie {
         struct iproc_pcie_ob ob;
         const struct iproc_pcie_ob_map *ob_map;
 
+        bool need_ib_cfg;
         struct iproc_pcie_ib ib;
         const struct iproc_pcie_ib_map *ib_map;
 
diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
index db93efdf1d63..a8b20c5012a9 100644
--- a/drivers/pci/host/pcie-mediatek.c
+++ b/drivers/pci/host/pcie-mediatek.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * MediaTek PCIe host controller driver.
  *
  * Copyright (c) 2017 MediaTek Inc.
  * Author: Ryder Lee <ryder.lee@mediatek.com>
  *         Honghui Zhang <honghui.zhang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
index 52ab3cb0a0bf..b4c4aad2cf66 100644
--- a/drivers/pci/host/pcie-rcar.c
+++ b/drivers/pci/host/pcie-rcar.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * PCIe driver for Renesas R-Car SoCs
  *  Copyright (C) 2014 Renesas Electronics Europe Ltd
@@ -8,10 +9,6 @@
  *  Copyright (C) 2009 - 2011  Paul Mundt
  *
  * Author: Phil Edworthy <phil.edworthy@renesas.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clk.h>
@@ -459,7 +456,7 @@ static int rcar_pcie_enable(struct rcar_pcie *pcie)
 
         rcar_pcie_setup(&bridge->windows, pcie);
 
-        pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);
+        pci_add_flags(PCI_REASSIGN_ALL_BUS);
 
         bridge->dev.parent = dev;
         bridge->sysdata = pcie;
@@ -1123,7 +1120,9 @@ static int rcar_pcie_probe(struct platform_device *pdev)
 
         INIT_LIST_HEAD(&pcie->resources);
 
-        rcar_pcie_parse_request_of_pci_ranges(pcie);
+        err = rcar_pcie_parse_request_of_pci_ranges(pcie);
+        if (err)
+                goto err_free_bridge;
 
         err = rcar_pcie_get_resources(pcie);
         if (err < 0) {
@@ -1178,6 +1177,7 @@ err_pm_disable:
 
 err_free_resource_list:
         pci_free_resource_list(&pcie->resources);
+err_free_bridge:
         pci_free_host_bridge(bridge);
 
         return err;
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 9051c6c8fea4..f1e8f97ea1fb 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Rockchip AXI PCIe host controller driver
  *
@@ -8,11 +9,6 @@
  *
  * Bits taken from Synopsys DesignWare Host controller driver and
  * ARM PCI Host generic driver.
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
  */
 
 #include <linux/bitrev.h>
diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c
index 65dea98b2643..0acaf483d031 100644
--- a/drivers/pci/host/pcie-xilinx-nwl.c
+++ b/drivers/pci/host/pcie-xilinx-nwl.c
@@ -1,13 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * PCIe host controller driver for NWL PCIe Bridge
  * Based on pcie-xilinx.c, pci-tegra.c
  *
  * (C) Copyright 2014 - 2015, Xilinx, Inc.
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
  */
 
 #include <linux/delay.h>
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 7b5325990f5e..0ad188effc09 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * PCIe host controller driver for Xilinx AXI PCIe Bridge
  *
@@ -7,11 +8,6 @@
  *
  * Bits taken from Synopsys DesignWare Host controller driver and
  * ARM PCI Host generic driver.
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
  */
 
 #include <linux/interrupt.h>
diff --git a/drivers/pci/host/vmd.c b/drivers/pci/host/vmd.c
index 509893bc3e63..930a8fa08bd6 100644
--- a/drivers/pci/host/vmd.c
+++ b/drivers/pci/host/vmd.c
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Volume Management Device driver
  * Copyright (c) 2015, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
  */
 
 #include <linux/device.h>
diff --git a/drivers/pci/hotplug/Kconfig b/drivers/pci/hotplug/Kconfig
index aadce45a9b4a..a8f21d051e0c 100644
--- a/drivers/pci/hotplug/Kconfig
+++ b/drivers/pci/hotplug/Kconfig
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
 #
 # PCI Hotplug support
 #
diff --git a/drivers/pci/hotplug/acpi_pcihp.c b/drivers/pci/hotplug/acpi_pcihp.c
index a5e66df4ad14..c9816166978e 100644
--- a/drivers/pci/hotplug/acpi_pcihp.c
+++ b/drivers/pci/hotplug/acpi_pcihp.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Common ACPI functions for hot plug platforms
  *
@@ -5,21 +6,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <kristen.c.accardi@intel.com>
  *
  */
diff --git a/drivers/pci/hotplug/acpiphp.h b/drivers/pci/hotplug/acpiphp.h
index f0ebc8b9a15a..e438a2d734f2 100644
--- a/drivers/pci/hotplug/acpiphp.h
+++ b/drivers/pci/hotplug/acpiphp.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * ACPI PCI Hot Plug Controller Driver
  *
@@ -12,21 +13,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <gregkh@us.ibm.com>,
  *                  <t-kochi@bq.jp.nec.com>
  *
diff --git a/drivers/pci/hotplug/acpiphp_core.c b/drivers/pci/hotplug/acpiphp_core.c
index 3c81fc8b0103..12b5655fd390 100644
--- a/drivers/pci/hotplug/acpiphp_core.c
+++ b/drivers/pci/hotplug/acpiphp_core.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * ACPI PCI Hot Plug Controller Driver
  *
@@ -12,21 +13,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <kristen.c.accardi@intel.com>
  *
  */
diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c
index 5db6f1839dad..e2198a2feeca 100644
--- a/drivers/pci/hotplug/acpiphp_glue.c
+++ b/drivers/pci/hotplug/acpiphp_glue.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * ACPI PCI HotPlug glue functions to ACPI CA subsystem
  *
@@ -11,21 +12,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <kristen.c.accardi@intel.com>
  *
  */
@@ -811,10 +797,8 @@ void acpiphp_enumerate_slots(struct pci_bus *bus)
 
         handle = adev->handle;
         bridge = kzalloc(sizeof(struct acpiphp_bridge), GFP_KERNEL);
-        if (!bridge) {
-                acpi_handle_err(handle, "No memory for bridge object\n");
+        if (!bridge)
                 return;
-        }
 
         INIT_LIST_HEAD(&bridge->slots);
         kref_init(&bridge->ref);
diff --git a/drivers/pci/hotplug/acpiphp_ibm.c b/drivers/pci/hotplug/acpiphp_ibm.c
index 8472c4a27f70..41713f16ff97 100644
--- a/drivers/pci/hotplug/acpiphp_ibm.c
+++ b/drivers/pci/hotplug/acpiphp_ibm.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * ACPI PCI Hot Plug IBM Extension
  *
@@ -6,21 +7,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <vernux@us.ibm.com>
  *
  */
diff --git a/drivers/pci/hotplug/cpci_hotplug.h b/drivers/pci/hotplug/cpci_hotplug.h
index 60e66e027ebc..4658557be01a 100644
--- a/drivers/pci/hotplug/cpci_hotplug.h
+++ b/drivers/pci/hotplug/cpci_hotplug.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * CompactPCI Hot Plug Core Functions
  *
@@ -7,21 +8,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <scottm@somanetworks.com>
  */
 
diff --git a/drivers/pci/hotplug/cpci_hotplug_core.c b/drivers/pci/hotplug/cpci_hotplug_core.c
index 95f689f53920..07b533adc9df 100644
--- a/drivers/pci/hotplug/cpci_hotplug_core.c
+++ b/drivers/pci/hotplug/cpci_hotplug_core.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * CompactPCI Hot Plug Driver
  *
@@ -7,21 +8,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <scottm@somanetworks.com>
  */
 
diff --git a/drivers/pci/hotplug/cpci_hotplug_pci.c b/drivers/pci/hotplug/cpci_hotplug_pci.c
index f616358fa938..389b8fb50cd9 100644
--- a/drivers/pci/hotplug/cpci_hotplug_pci.c
+++ b/drivers/pci/hotplug/cpci_hotplug_pci.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * CompactPCI Hot Plug Driver PCI functions
  *
@@ -5,21 +6,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <scottm@somanetworks.com>
  */
 
diff --git a/drivers/pci/hotplug/cpcihp_generic.c b/drivers/pci/hotplug/cpcihp_generic.c
index bbf9cf8aeaad..17d71edf046f 100644
--- a/drivers/pci/hotplug/cpcihp_generic.c
+++ b/drivers/pci/hotplug/cpcihp_generic.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * cpcihp_generic.c
  *
@@ -7,26 +8,6 @@
  * Copyright 2001 Intel San Luis Obispo
  * Copyright 2000,2001 MontaVista Software Inc.
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
- * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * This generic CompactPCI hotplug driver should allow using the PCI hotplug
  * mechanism on any CompactPCI board that exposes the #ENUM signal as a bit
  * in a system register that can be read through standard port I/O.
diff --git a/drivers/pci/hotplug/cpcihp_zt5550.c b/drivers/pci/hotplug/cpcihp_zt5550.c
index 2f8659a148f5..ae63e5a393c2 100644
--- a/drivers/pci/hotplug/cpcihp_zt5550.c
+++ b/drivers/pci/hotplug/cpcihp_zt5550.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * cpcihp_zt5550.c
  *
@@ -7,26 +8,6 @@
  * Copyright 2001 Intel San Luis Obispo
  * Copyright 2000,2001 MontaVista Software Inc.
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
- * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <scottm@somanetworks.com>
  */
 
diff --git a/drivers/pci/hotplug/cpcihp_zt5550.h b/drivers/pci/hotplug/cpcihp_zt5550.h
index 9a57fda5348c..5ea10df83dd9 100644
--- a/drivers/pci/hotplug/cpcihp_zt5550.h
+++ b/drivers/pci/hotplug/cpcihp_zt5550.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * cpcihp_zt5550.h
  *
@@ -7,26 +8,6 @@
  * Copyright 2001 Intel San Luis Obispo
  * Copyright 2000,2001 MontaVista Software Inc.
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
- * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <scottm@somanetworks.com>
  */
 
diff --git a/drivers/pci/hotplug/cpqphp.h b/drivers/pci/hotplug/cpqphp.h
index c2bbe6b65d06..db78b394a075 100644
--- a/drivers/pci/hotplug/cpqphp.h
+++ b/drivers/pci/hotplug/cpqphp.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Compaq Hot Plug Controller Driver
  *
@@ -7,21 +8,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <greg@kroah.com>
  *
  */
diff --git a/drivers/pci/hotplug/cpqphp_core.c b/drivers/pci/hotplug/cpqphp_core.c
index 70967ac75265..1797e36ec586 100644
--- a/drivers/pci/hotplug/cpqphp_core.c
+++ b/drivers/pci/hotplug/cpqphp_core.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Compaq Hot Plug Controller Driver
  *
@@ -7,21 +8,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <greg@kroah.com>
  *
  * Jan 12, 2003 -       Added 66/100/133MHz PCI-X support,
@@ -835,7 +821,7 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 
         bus = pdev->subordinate;
         if (!bus) {
-                dev_notice(&pdev->dev, "the device is not a bridge, skipping\n");
+                pci_notice(pdev, "the device is not a bridge, skipping\n");
                 rc = -ENODEV;
                 goto err_disable_device;
         }
@@ -883,7 +869,6 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 
         ctrl = kzalloc(sizeof(struct controller), GFP_KERNEL);
         if (!ctrl) {
-                err("%s : out of memory\n", __func__);
                 rc = -ENOMEM;
                 goto err_disable_device;
         }
diff --git a/drivers/pci/hotplug/cpqphp_ctrl.c b/drivers/pci/hotplug/cpqphp_ctrl.c
index a93069e739cb..b1b6e45253b2 100644
--- a/drivers/pci/hotplug/cpqphp_ctrl.c
+++ b/drivers/pci/hotplug/cpqphp_ctrl.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Compaq Hot Plug Controller Driver
  *
@@ -7,21 +8,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <greg@kroah.com>
  *
  */
diff --git a/drivers/pci/hotplug/cpqphp_nvram.c b/drivers/pci/hotplug/cpqphp_nvram.c
index daae8071a156..00cd2b43364f 100644
--- a/drivers/pci/hotplug/cpqphp_nvram.c
+++ b/drivers/pci/hotplug/cpqphp_nvram.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Compaq Hot Plug Controller Driver
  *
@@ -7,21 +8,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <greg@kroah.com>
  *
  */
diff --git a/drivers/pci/hotplug/cpqphp_nvram.h b/drivers/pci/hotplug/cpqphp_nvram.h
index 34e4e54fcf15..918ff8dbfe62 100644
--- a/drivers/pci/hotplug/cpqphp_nvram.h
+++ b/drivers/pci/hotplug/cpqphp_nvram.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Compaq Hot Plug Controller Driver
  *
@@ -6,21 +7,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <greg@kroah.com>
  *
  */
diff --git a/drivers/pci/hotplug/cpqphp_pci.c b/drivers/pci/hotplug/cpqphp_pci.c
index e220d49307bd..1b2b3f3b648b 100644
--- a/drivers/pci/hotplug/cpqphp_pci.c
+++ b/drivers/pci/hotplug/cpqphp_pci.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Compaq Hot Plug Controller Driver
  *
@@ -7,21 +8,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <greg@kroah.com>
  *
  */
@@ -89,7 +75,9 @@ int cpqhp_configure_device(struct controller *ctrl, struct pci_func *func)
         pci_lock_rescan_remove();
 
         if (func->pci_dev == NULL)
-                func->pci_dev = pci_get_bus_and_slot(func->bus, PCI_DEVFN(func->device, func->function));
+                func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus,
+                                                        PCI_DEVFN(func->device,
+                                                        func->function));
 
         /* No pci device, we need to create it then */
         if (func->pci_dev == NULL) {
@@ -99,7 +87,9 @@ int cpqhp_configure_device(struct controller *ctrl, struct pci_func *func)
                 if (num)
                         pci_bus_add_devices(ctrl->pci_dev->bus);
 
-                func->pci_dev = pci_get_bus_and_slot(func->bus, PCI_DEVFN(func->device, func->function));
+                func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus,
+                                                        PCI_DEVFN(func->device,
+                                                        func->function));
                 if (func->pci_dev == NULL) {
                         dbg("ERROR: pci_dev still null\n");
                         goto out;
@@ -129,7 +119,10 @@ int cpqhp_unconfigure_device(struct pci_func *func)
 
         pci_lock_rescan_remove();
         for (j = 0; j < 8 ; j++) {
-                struct pci_dev *temp = pci_get_bus_and_slot(func->bus, PCI_DEVFN(func->device, j));
+                struct pci_dev *temp = pci_get_domain_bus_and_slot(0,
+                                                        func->bus,
+                                                        PCI_DEVFN(func->device,
+                                                        j));
                 if (temp) {
                         pci_dev_put(temp);
                         pci_stop_and_remove_bus_device(temp);
@@ -319,6 +312,7 @@ int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug)
         int cloop = 0;
         int stop_it;
         int index;
+        u16 devfn;
 
         /* Decide which slots are supported */
 
@@ -416,7 +410,9 @@ int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug)
                         new_slot->switch_save = 0x10;
                         /* In case of unsupported board */
                         new_slot->status = DevError;
-                        new_slot->pci_dev = pci_get_bus_and_slot(new_slot->bus, (new_slot->device << 3) | new_slot->function);
+                        devfn = (new_slot->device << 3) | new_slot->function;
+                        new_slot->pci_dev = pci_get_domain_bus_and_slot(0,
+                                                        new_slot->bus, devfn);
 
                         for (cloop = 0; cloop < 0x20; cloop++) {
                                 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), cloop << 2, (u32 *) &(new_slot->config_space[cloop]));
diff --git a/drivers/pci/hotplug/cpqphp_sysfs.c b/drivers/pci/hotplug/cpqphp_sysfs.c
index 775974deda74..fed1360ee9b1 100644
--- a/drivers/pci/hotplug/cpqphp_sysfs.c
+++ b/drivers/pci/hotplug/cpqphp_sysfs.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Compaq Hot Plug Controller Driver
  *
@@ -7,21 +8,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <greg@kroah.com>
  *
  */
diff --git a/drivers/pci/hotplug/ibmphp.h b/drivers/pci/hotplug/ibmphp.h
index d3256838cb05..fddb78606c74 100644
--- a/drivers/pci/hotplug/ibmphp.h
+++ b/drivers/pci/hotplug/ibmphp.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 #ifndef __IBMPHP_H
 #define __IBMPHP_H
 
@@ -11,21 +12,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <gregkh@us.ibm.com>
  *
  */
diff --git a/drivers/pci/hotplug/ibmphp_core.c b/drivers/pci/hotplug/ibmphp_core.c
index 73cf84645c82..b81ca3fa0e84 100644
--- a/drivers/pci/hotplug/ibmphp_core.c
+++ b/drivers/pci/hotplug/ibmphp_core.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * IBM Hot Plug Controller Driver
  *
@@ -8,21 +9,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <gregkh@us.ibm.com>
  *
  */
@@ -603,10 +589,8 @@ int ibmphp_update_slot_info(struct slot *slot_cur)
         u8 mode;
 
         info = kmalloc(sizeof(struct hotplug_slot_info), GFP_KERNEL);
-        if (!info) {
-                err("out of system memory\n");
+        if (!info)
                 return -ENOMEM;
-        }
 
         info->power_status = SLOT_PWRGD(slot_cur->status);
         info->attention_status = SLOT_ATTN(slot_cur->status,
@@ -707,7 +691,8 @@ static void ibm_unconfigure_device(struct pci_func *func)
         pci_lock_rescan_remove();
 
         for (j = 0; j < 0x08; j++) {
-                temp = pci_get_bus_and_slot(func->busno, (func->device << 3) | j);
+                temp = pci_get_domain_bus_and_slot(0, func->busno,
+                                                   (func->device << 3) | j);
                 if (temp) {
                         pci_stop_and_remove_bus_device(temp);
                         pci_dev_put(temp);
@@ -734,14 +719,12 @@ static u8 bus_structure_fixup(u8 busno)
                 return 1;
 
         bus = kmalloc(sizeof(*bus), GFP_KERNEL);
-        if (!bus) {
-                err("%s - out of memory\n", __func__);
+        if (!bus)
                 return 1;
-        }
+
         dev = kmalloc(sizeof(*dev), GFP_KERNEL);
         if (!dev) {
                 kfree(bus);
-                err("%s - out of memory\n", __func__);
                 return 1;
         }
 
@@ -780,7 +763,7 @@ static int ibm_configure_device(struct pci_func *func)
         if (!(bus_structure_fixup(func->busno)))
                 flag = 1;
         if (func->dev == NULL)
-                func->dev = pci_get_bus_and_slot(func->busno,
+                func->dev = pci_get_domain_bus_and_slot(0, func->busno,
                                 PCI_DEVFN(func->device, func->function));
 
         if (func->dev == NULL) {
@@ -793,7 +776,7 @@ static int ibm_configure_device(struct pci_func *func)
                 if (num)
                         pci_bus_add_devices(bus);
 
-                func->dev = pci_get_bus_and_slot(func->busno,
+                func->dev = pci_get_domain_bus_and_slot(0, func->busno,
                                 PCI_DEVFN(func->device, func->function));
                 if (func->dev == NULL) {
                         err("ERROR... : pci_dev still NULL\n");
@@ -1101,7 +1084,6 @@ static int enable_slot(struct hotplug_slot *hs)
         if (!slot_cur->func) {
                 /* We cannot do update_slot_info here, since no memory for
                  * kmalloc n.e.ways, and update_slot_info allocates some */
-                err("out of system memory\n");
                 rc = -ENOMEM;
                 goto error_power;
         }
@@ -1208,7 +1190,6 @@ int ibmphp_do_disable_slot(struct slot *slot_cur)
                 /* We need this for functions that were there on bootup */
                 slot_cur->func = kzalloc(sizeof(struct pci_func), GFP_KERNEL);
                 if (!slot_cur->func) {
-                        err("out of system memory\n");
                         rc = -ENOMEM;
                         goto error;
                 }
@@ -1306,7 +1287,6 @@ static int __init ibmphp_init(void)
 
         ibmphp_pci_bus = kmalloc(sizeof(*ibmphp_pci_bus), GFP_KERNEL);
         if (!ibmphp_pci_bus) {
-                err("out of memory\n");
                 rc = -ENOMEM;
                 goto exit;
         }
diff --git a/drivers/pci/hotplug/ibmphp_ebda.c b/drivers/pci/hotplug/ibmphp_ebda.c
index a6a4dac798e5..64549aa24c0f 100644
--- a/drivers/pci/hotplug/ibmphp_ebda.c
+++ b/drivers/pci/hotplug/ibmphp_ebda.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * IBM Hot Plug Controller Driver
  *
@@ -8,21 +9,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <gregkh@us.ibm.com>
  *
  */
diff --git a/drivers/pci/hotplug/ibmphp_hpc.c b/drivers/pci/hotplug/ibmphp_hpc.c
index a6b458e4ab46..752c384cbd4c 100644
--- a/drivers/pci/hotplug/ibmphp_hpc.c
+++ b/drivers/pci/hotplug/ibmphp_hpc.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * IBM Hot Plug Controller Driver
  *
@@ -7,21 +8,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <gregkh@us.ibm.com>
  *                  <jshah@us.ibm.com>
  *
diff --git a/drivers/pci/hotplug/ibmphp_pci.c b/drivers/pci/hotplug/ibmphp_pci.c
index 25edd0b18b75..e22d023f91d1 100644
--- a/drivers/pci/hotplug/ibmphp_pci.c
+++ b/drivers/pci/hotplug/ibmphp_pci.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * IBM Hot Plug Controller Driver
  *
@@ -8,21 +9,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <gregkh@us.ibm.com>
  *
  */
@@ -167,10 +153,9 @@ int ibmphp_configure_card(struct pci_func *func, u8 slotno)
                                                 goto error;
                                         }
                                         newfunc = kzalloc(sizeof(*newfunc), GFP_KERNEL);
-                                        if (!newfunc) {
-                                                err("out of system memory\n");
+                                        if (!newfunc)
                                                 return -ENOMEM;
-                                        }
+
                                         newfunc->busno = cur_func->busno;
                                         newfunc->device = device;
                                         cur_func->next = newfunc;
@@ -205,10 +190,9 @@ int ibmphp_configure_card(struct pci_func *func, u8 slotno)
                                         for (i = 0; i < 32; i++) {
                                                 if (func->devices[i]) {
                                                         newfunc = kzalloc(sizeof(*newfunc), GFP_KERNEL);
-                                                        if (!newfunc) {
-                                                                err("out of system memory\n");
+                                                        if (!newfunc)
                                                                 return -ENOMEM;
-                                                        }
+
                                                         newfunc->busno = sec_number;
                                                         newfunc->device = (u8) i;
                                                         for (j = 0; j < 4; j++)
@@ -233,10 +217,9 @@ int ibmphp_configure_card(struct pci_func *func, u8 slotno)
                                         }
 
                                         newfunc = kzalloc(sizeof(*newfunc), GFP_KERNEL);
-                                        if (!newfunc) {
-                                                err("out of system memory\n");
+                                        if (!newfunc)
                                                 return -ENOMEM;
-                                        }
+
                                         newfunc->busno = cur_func->busno;
                                         newfunc->device = device;
                                         for (j = 0; j < 4; j++)
@@ -279,10 +262,9 @@ int ibmphp_configure_card(struct pci_func *func, u8 slotno)
                                                 if (func->devices[i]) {
                                                         debug("inside for loop, device is %x\n", i);
                                                         newfunc = kzalloc(sizeof(*newfunc), GFP_KERNEL);
-                                                        if (!newfunc) {
-                                                                err(" out of system memory\n");
+                                                        if (!newfunc)
                                                                 return -ENOMEM;
-                                                        }
+
                                                         newfunc->busno = sec_number;
                                                         newfunc->device = (u8) i;
                                                         for (j = 0; j < 4; j++)
@@ -405,10 +387,9 @@ static int configure_device(struct pci_func *func)
 
                         io[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
 
-                        if (!io[count]) {
-                                err("out of system memory\n");
+                        if (!io[count])
                                 return -ENOMEM;
-                        }
+
                         io[count]->type = IO;
                         io[count]->busno = func->busno;
                         io[count]->devfunc = PCI_DEVFN(func->device, func->function);
@@ -442,10 +423,9 @@ static int configure_device(struct pci_func *func)
                                 debug("len[count] in PFMEM %x, count %d\n", len[count], count);
 
                                 pfmem[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
-                                if (!pfmem[count]) {
-                                        err("out of system memory\n");
+                                if (!pfmem[count])
                                         return -ENOMEM;
-                                }
+
                                 pfmem[count]->type = PFMEM;
                                 pfmem[count]->busno = func->busno;
                                 pfmem[count]->devfunc = PCI_DEVFN(func->device,
@@ -458,7 +438,6 @@ static int configure_device(struct pci_func *func)
                                 } else {
                                         mem_tmp = kzalloc(sizeof(*mem_tmp), GFP_KERNEL);
                                         if (!mem_tmp) {
-                                                err("out of system memory\n");
                                                 kfree(pfmem[count]);
                                                 return -ENOMEM;
                                         }
@@ -508,10 +487,9 @@ static int configure_device(struct pci_func *func)
                                 debug("len[count] in Mem %x, count %d\n", len[count], count);
 
                                 mem[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
-                                if (!mem[count]) {
-                                        err("out of system memory\n");
+                                if (!mem[count])
                                         return -ENOMEM;
-                                }
+
                                 mem[count]->type = MEM;
                                 mem[count]->busno = func->busno;
                                 mem[count]->devfunc = PCI_DEVFN(func->device,
@@ -674,7 +652,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno)
                         bus_io[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
 
                         if (!bus_io[count]) {
-                                err("out of system memory\n");
                                 retval = -ENOMEM;
                                 goto error;
                         }
@@ -706,7 +683,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno)
 
                                 bus_pfmem[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
                                 if (!bus_pfmem[count]) {
-                                        err("out of system memory\n");
                                         retval = -ENOMEM;
                                         goto error;
                                 }
@@ -722,7 +698,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno)
                                 } else {
                                         mem_tmp = kzalloc(sizeof(*mem_tmp), GFP_KERNEL);
                                         if (!mem_tmp) {
-                                                err("out of system memory\n");
                                                 retval = -ENOMEM;
                                                 goto error;
                                         }
@@ -763,7 +738,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno)
 
                                 bus_mem[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
                                 if (!bus_mem[count]) {
-                                        err("out of system memory\n");
                                         retval = -ENOMEM;
                                         goto error;
                                 }
@@ -834,7 +808,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno)
                 io = kzalloc(sizeof(*io), GFP_KERNEL);
 
                 if (!io) {
-                        err("out of system memory\n");
                         retval = -ENOMEM;
                         goto error;
                 }
@@ -856,7 +829,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno)
                 debug("it wants %x memory behind the bridge\n", amount_needed->mem);
                 mem = kzalloc(sizeof(*mem), GFP_KERNEL);
                 if (!mem) {
-                        err("out of system memory\n");
                         retval = -ENOMEM;
                         goto error;
                 }
@@ -878,7 +850,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno)
                 debug("it wants %x pfmemory behind the bridge\n", amount_needed->pfmem);
                 pfmem = kzalloc(sizeof(*pfmem), GFP_KERNEL);
                 if (!pfmem) {
-                        err("out of system memory\n");
                         retval = -ENOMEM;
                         goto error;
                 }
@@ -893,7 +864,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno)
                 } else {
                         mem_tmp = kzalloc(sizeof(*mem_tmp), GFP_KERNEL);
                         if (!mem_tmp) {
-                                err("out of system memory\n");
                                 retval = -ENOMEM;
                                 goto error;
                         }
@@ -924,7 +894,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno)
                 if (!bus) {
                         bus = kzalloc(sizeof(*bus), GFP_KERNEL);
                         if (!bus) {
-                                err("out of system memory\n");
                                 retval = -ENOMEM;
                                 goto error;
                         }
@@ -1652,10 +1621,9 @@ static int add_new_bus(struct bus_node *bus, struct resource_node *io, struct re
         }
         if (io) {
                 io_range = kzalloc(sizeof(*io_range), GFP_KERNEL);
-                if (!io_range) {
-                        err("out of system memory\n");
+                if (!io_range)
                         return -ENOMEM;
-                }
+
                 io_range->start = io->start;
                 io_range->end = io->end;
                 io_range->rangeno = 1;
@@ -1664,10 +1632,9 @@ static int add_new_bus(struct bus_node *bus, struct resource_node *io, struct re
         }
         if (mem) {
                 mem_range = kzalloc(sizeof(*mem_range), GFP_KERNEL);
-                if (!mem_range) {
-                        err("out of system memory\n");
+                if (!mem_range)
                         return -ENOMEM;
-                }
+
                 mem_range->start = mem->start;
                 mem_range->end = mem->end;
                 mem_range->rangeno = 1;
@@ -1676,10 +1643,9 @@ static int add_new_bus(struct bus_node *bus, struct resource_node *io, struct re
         }
         if (pfmem) {
                 pfmem_range = kzalloc(sizeof(*pfmem_range), GFP_KERNEL);
-                if (!pfmem_range) {
-                        err("out of system memory\n");
+                if (!pfmem_range)
                         return -ENOMEM;
-                }
+
                 pfmem_range->start = pfmem->start;
                 pfmem_range->end = pfmem->end;
                 pfmem_range->rangeno = 1;
diff --git a/drivers/pci/hotplug/ibmphp_res.c b/drivers/pci/hotplug/ibmphp_res.c
index aee6e41001e1..5e8caf7a4452 100644
--- a/drivers/pci/hotplug/ibmphp_res.c
+++ b/drivers/pci/hotplug/ibmphp_res.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * IBM Hot Plug Controller Driver
  *
@@ -8,21 +9,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <gregkh@us.ibm.com>
  *
  */
@@ -56,10 +42,8 @@ static struct bus_node * __init alloc_error_bus(struct ebda_pci_rsrc *curr, u8 b
         }
 
         newbus = kzalloc(sizeof(struct bus_node), GFP_KERNEL);
-        if (!newbus) {
-                err("out of system memory\n");
+        if (!newbus)
                 return NULL;
-        }
 
         if (flag)
                 newbus->busno = busno;
@@ -79,10 +63,9 @@ static struct resource_node * __init alloc_resources(struct ebda_pci_rsrc *curr)
         }
 
         rs = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
-        if (!rs) {
-                err("out of system memory\n");
+        if (!rs)
                 return NULL;
-        }
+
         rs->busno = curr->bus_num;
         rs->devfunc = curr->dev_fun;
         rs->start = curr->start_addr;
@@ -99,10 +82,9 @@ static int __init alloc_bus_range(struct bus_node **new_bus, struct range_node *
 
         if (first_bus) {
                 newbus = kzalloc(sizeof(struct bus_node), GFP_KERNEL);
-                if (!newbus) {
-                        err("out of system memory.\n");
+                if (!newbus)
                         return -ENOMEM;
-                }
+
                 newbus->busno = curr->bus_num;
         } else {
                 newbus = *new_bus;
@@ -123,7 +105,6 @@ static int __init alloc_bus_range(struct bus_node **new_bus, struct range_node *
         if (!newrange) {
                 if (first_bus)
                         kfree(newbus);
-                err("out of system memory\n");
                 return -ENOMEM;
         }
         newrange->start = curr->start_addr;
@@ -1707,10 +1688,9 @@ static int __init once_over(void)
                                 bus_cur->firstPFMemFromMem = pfmem_cur;
 
                                 mem = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
-                                if (!mem) {
-                                        err("out of system memory\n");
+                                if (!mem)
                                         return -ENOMEM;
-                                }
+
                                 mem->type = MEM;
                                 mem->busno = pfmem_cur->busno;
                                 mem->devfunc = pfmem_cur->devfunc;
@@ -1989,10 +1969,9 @@ static int __init update_bridge_ranges(struct bus_node **bus)
 
                                                 if ((start_address) && (start_address <= end_address)) {
                                                         range = kzalloc(sizeof(struct range_node), GFP_KERNEL);
-                                                        if (!range) {
-                                                                err("out of system memory\n");
+                                                        if (!range)
                                                                 return -ENOMEM;
-                                                        }
+
                                                         range->start = start_address;
                                                         range->end = end_address + 0xfff;
 
@@ -2016,7 +1995,6 @@ static int __init update_bridge_ranges(struct bus_node **bus)
                                                                 io = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
                                                                 if (!io) {
                                                                         kfree(range);
-                                                                        err("out of system memory\n");
                                                                         return -ENOMEM;
                                                                 }
                                                                 io->type = IO;
@@ -2038,10 +2016,9 @@ static int __init update_bridge_ranges(struct bus_node **bus)
                                                 if ((start_address) && (start_address <= end_address)) {
 
                                                         range = kzalloc(sizeof(struct range_node), GFP_KERNEL);
-                                                        if (!range) {
-                                                                err("out of system memory\n");
+                                                        if (!range)
                                                                 return -ENOMEM;
-                                                        }
+
                                                         range->start = start_address;
                                                         range->end = end_address + 0xfffff;
 
@@ -2066,7 +2043,6 @@ static int __init update_bridge_ranges(struct bus_node **bus)
                                                                 mem = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
                                                                 if (!mem) {
                                                                         kfree(range);
-                                                                        err("out of system memory\n");
                                                                         return -ENOMEM;
                                                                 }
                                                                 mem->type = MEM;
@@ -2092,10 +2068,9 @@ static int __init update_bridge_ranges(struct bus_node **bus)
                                                 if ((start_address) && (start_address <= end_address)) {
 
                                                         range = kzalloc(sizeof(struct range_node), GFP_KERNEL);
-                                                        if (!range) {
-                                                                err("out of system memory\n");
+                                                        if (!range)
                                                                 return -ENOMEM;
-                                                        }
+
                                                         range->start = start_address;
                                                         range->end = end_address + 0xfffff;
 
@@ -2119,7 +2094,6 @@ static int __init update_bridge_ranges(struct bus_node **bus)
                                                                 pfmem = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
                                                                 if (!pfmem) {
                                                                         kfree(range);
-                                                                        err("out of system memory\n");
                                                                         return -ENOMEM;
                                                                 }
                                                                 pfmem->type = PFMEM;
diff --git a/drivers/pci/hotplug/pci_hotplug_core.c b/drivers/pci/hotplug/pci_hotplug_core.c
index 7b0e97be9063..af92fed46ab7 100644
--- a/drivers/pci/hotplug/pci_hotplug_core.c
+++ b/drivers/pci/hotplug/pci_hotplug_core.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * PCI HotPlug Controller Core
  *
@@ -6,21 +7,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <kristen.c.accardi@intel.com>
  *
  * Authors:
diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h
index 06109d40c4ac..636ed8f4b869 100644
--- a/drivers/pci/hotplug/pciehp.h
+++ b/drivers/pci/hotplug/pciehp.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * PCI Express Hot Plug Controller Driver
  *
@@ -8,21 +9,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
  *
  */
diff --git a/drivers/pci/hotplug/pciehp_core.c b/drivers/pci/hotplug/pciehp_core.c
index 35d84845d5af..332b723ff9e6 100644
--- a/drivers/pci/hotplug/pciehp_core.c
+++ b/drivers/pci/hotplug/pciehp_core.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * PCI Express Hot Plug Controller Driver
  *
@@ -8,21 +9,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
  *
  * Authors:
diff --git a/drivers/pci/hotplug/pciehp_ctrl.c b/drivers/pci/hotplug/pciehp_ctrl.c
index 83f3d4af3677..c684faa43387 100644
--- a/drivers/pci/hotplug/pciehp_ctrl.c
+++ b/drivers/pci/hotplug/pciehp_ctrl.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * PCI Express Hot Plug Controller Driver
  *
@@ -8,21 +9,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
  *
  */
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index 7bab0606f1a9..18a42f8f5dc5 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * PCI Express PCI Hot Plug Driver
  *
@@ -8,21 +9,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  *
  */
@@ -838,16 +824,22 @@ struct controller *pcie_init(struct pcie_device *dev)
         struct pci_dev *pdev = dev->port;
 
         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
-        if (!ctrl) {
-                dev_err(&dev->device, "%s: Out of memory\n", __func__);
+        if (!ctrl)
                 goto abort;
-        }
+
         ctrl->pcie = dev;
         pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
 
         if (pdev->hotplug_user_indicators)
                 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
 
+        /*
+         * We assume no Thunderbolt controllers support Command Complete events,
+         * but some controllers falsely claim they do.
+         */
+        if (pdev->is_thunderbolt)
+                slot_cap |= PCI_EXP_SLTCAP_NCCS;
+
         ctrl->slot_cap = slot_cap;
         mutex_init(&ctrl->ctrl_lock);
         init_waitqueue_head(&ctrl->queue);
diff --git a/drivers/pci/hotplug/pciehp_pci.c b/drivers/pci/hotplug/pciehp_pci.c
index 2a1ca020cf5a..3f518dea856d 100644
--- a/drivers/pci/hotplug/pciehp_pci.c
+++ b/drivers/pci/hotplug/pciehp_pci.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * PCI Express Hot Plug Controller Driver
  *
@@ -8,21 +9,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
  *
  */
@@ -79,7 +65,6 @@ int pciehp_configure_device(struct slot *p_slot)
 int pciehp_unconfigure_device(struct slot *p_slot)
 {
         int rc = 0;
-        u8 bctl = 0;
         u8 presence = 0;
         struct pci_dev *dev, *temp;
         struct pci_bus *parent = p_slot->ctrl->pcie->port->subordinate;
@@ -101,17 +86,6 @@ int pciehp_unconfigure_device(struct slot *p_slot)
         list_for_each_entry_safe_reverse(dev, temp, &parent->devices,
                                          bus_list) {
                 pci_dev_get(dev);
-                if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && presence) {
-                        pci_read_config_byte(dev, PCI_BRIDGE_CONTROL, &bctl);
-                        if (bctl & PCI_BRIDGE_CTL_VGA) {
-                                ctrl_err(ctrl,
-                                         "Cannot remove display device %s\n",
-                                         pci_name(dev));
-                                pci_dev_put(dev);
-                                rc = -EINVAL;
-                                break;
-                        }
-                }
                 if (!presence) {
                         pci_dev_set_disconnected(dev, NULL);
                         if (pci_has_subordinate(dev))
diff --git a/drivers/pci/hotplug/pcihp_skeleton.c b/drivers/pci/hotplug/pcihp_skeleton.c
index 172ed89200cd..c19694a04d2c 100644
--- a/drivers/pci/hotplug/pcihp_skeleton.c
+++ b/drivers/pci/hotplug/pcihp_skeleton.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * PCI Hot Plug Controller Skeleton Driver - 0.3
  *
@@ -6,21 +7,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * This driver is to be used as a skeleton driver to show how to interface
  * with the pci hotplug core easily.
  *
diff --git a/drivers/pci/hotplug/pnv_php.c b/drivers/pci/hotplug/pnv_php.c
index 74f6a17e4614..23da3046f160 100644
--- a/drivers/pci/hotplug/pnv_php.c
+++ b/drivers/pci/hotplug/pnv_php.c
@@ -1,12 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * PCI Hotplug Driver for PowerPC PowerNV platform.
  *
  * Copyright Gavin Shan, IBM Corporation 2016.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
  */
 
 #include <linux/libfdt.h>
@@ -266,22 +262,18 @@ static int pnv_php_add_devtree(struct pnv_php_slot *php_slot)
         fdt1 = kzalloc(0x10000, GFP_KERNEL);
         if (!fdt1) {
                 ret = -ENOMEM;
-                dev_warn(&php_slot->pdev->dev, "Cannot alloc FDT blob\n");
                 goto out;
         }
 
         ret = pnv_pci_get_device_tree(php_slot->dn->phandle, fdt1, 0x10000);
         if (ret) {
-                dev_warn(&php_slot->pdev->dev, "Error %d getting FDT blob\n",
-                         ret);
+                pci_warn(php_slot->pdev, "Error %d getting FDT blob\n", ret);
                 goto free_fdt1;
         }
 
         fdt = kzalloc(fdt_totalsize(fdt1), GFP_KERNEL);
         if (!fdt) {
                 ret = -ENOMEM;
-                dev_warn(&php_slot->pdev->dev, "Cannot %d bytes memory\n",
-                         fdt_totalsize(fdt1));
                 goto free_fdt1;
         }
 
@@ -290,7 +282,7 @@ static int pnv_php_add_devtree(struct pnv_php_slot *php_slot)
         dt = of_fdt_unflatten_tree(fdt, php_slot->dn, NULL);
         if (!dt) {
                 ret = -EINVAL;
-                dev_warn(&php_slot->pdev->dev, "Cannot unflatten FDT\n");
+                pci_warn(php_slot->pdev, "Cannot unflatten FDT\n");
                 goto free_fdt;
         }
 
@@ -300,7 +292,7 @@ static int pnv_php_add_devtree(struct pnv_php_slot *php_slot)
         ret = pnv_php_populate_changeset(&php_slot->ocs, php_slot->dn);
         if (ret) {
                 pnv_php_reverse_nodes(php_slot->dn);
-                dev_warn(&php_slot->pdev->dev, "Error %d populating changeset\n",
+                pci_warn(php_slot->pdev, "Error %d populating changeset\n",
                          ret);
                 goto free_dt;
         }
@@ -308,8 +300,7 @@ static int pnv_php_add_devtree(struct pnv_php_slot *php_slot)
         php_slot->dn->child = NULL;
         ret = of_changeset_apply(&php_slot->ocs);
         if (ret) {
-                dev_warn(&php_slot->pdev->dev, "Error %d applying changeset\n",
-                         ret);
+                pci_warn(php_slot->pdev, "Error %d applying changeset\n", ret);
                 goto destroy_changeset;
         }
 
@@ -345,14 +336,14 @@ int pnv_php_set_slot_power_state(struct hotplug_slot *slot,
                 if (be64_to_cpu(msg.params[1]) != php_slot->dn->phandle ||
                     be64_to_cpu(msg.params[2]) != state                 ||
                     be64_to_cpu(msg.params[3]) != OPAL_SUCCESS) {
-                        dev_warn(&php_slot->pdev->dev, "Wrong msg (%lld, %lld, %lld)\n",
+                        pci_warn(php_slot->pdev, "Wrong msg (%lld, %lld, %lld)\n",
                                  be64_to_cpu(msg.params[1]),
                                  be64_to_cpu(msg.params[2]),
                                  be64_to_cpu(msg.params[3]));
                         return -ENOMSG;
                 }
         } else if (ret < 0) {
-                dev_warn(&php_slot->pdev->dev, "Error %d powering %s\n",
+                pci_warn(php_slot->pdev, "Error %d powering %s\n",
                          ret, (state == OPAL_PCI_SLOT_POWER_ON) ? "on" : "off");
                 return ret;
         }
@@ -379,7 +370,7 @@ static int pnv_php_get_power_state(struct hotplug_slot *slot, u8 *state)
          */
         ret = pnv_pci_get_power_state(php_slot->id, &power_state);
         if (ret) {
-                dev_warn(&php_slot->pdev->dev, "Error %d getting power status\n",
+                pci_warn(php_slot->pdev, "Error %d getting power status\n",
                          ret);
         } else {
                 *state = power_state;
@@ -405,8 +396,7 @@ static int pnv_php_get_adapter_state(struct hotplug_slot *slot, u8 *state)
                 slot->info->adapter_status = presence;
                 ret = 0;
         } else {
-                dev_warn(&php_slot->pdev->dev, "Error %d getting presence\n",
-                         ret);
+                pci_warn(php_slot->pdev, "Error %d getting presence\n", ret);
         }
 
         return ret;
@@ -629,8 +619,7 @@ static int pnv_php_register_slot(struct pnv_php_slot *php_slot)
         ret = pci_hp_register(&php_slot->slot, php_slot->bus,
                               php_slot->slot_no, php_slot->name);
         if (ret) {
-                dev_warn(&php_slot->pdev->dev, "Error %d registering slot\n",
-                         ret);
+                pci_warn(php_slot->pdev, "Error %d registering slot\n", ret);
                 return ret;
         }
 
@@ -683,7 +672,7 @@ static int pnv_php_enable_msix(struct pnv_php_slot *php_slot)
         /* Enable MSIx */
         ret = pci_enable_msix_exact(pdev, &entry, 1);
         if (ret) {
-                dev_warn(&pdev->dev, "Error %d enabling MSIx\n", ret);
+                pci_warn(pdev, "Error %d enabling MSIx\n", ret);
                 return ret;
         }
 
@@ -727,7 +716,7 @@ static irqreturn_t pnv_php_interrupt(int irq, void *data)
                    (sts & PCI_EXP_SLTSTA_PDC)) {
                 ret = pnv_pci_get_presence_state(php_slot->id, &presence);
                 if (ret) {
-                        dev_warn(&pdev->dev, "PCI slot [%s] error %d getting presence (0x%04x), to retry the operation.\n",
+                        pci_warn(pdev, "PCI slot [%s] error %d getting presence (0x%04x), to retry the operation.\n",
                                  php_slot->name, ret, sts);
                         return IRQ_HANDLED;
                 }
@@ -757,12 +746,12 @@ static irqreturn_t pnv_php_interrupt(int irq, void *data)
          */
         event = kzalloc(sizeof(*event), GFP_ATOMIC);
         if (!event) {
-                dev_warn(&pdev->dev, "PCI slot [%s] missed hotplug event 0x%04x\n",
+                pci_warn(pdev, "PCI slot [%s] missed hotplug event 0x%04x\n",
                          php_slot->name, sts);
                 return IRQ_HANDLED;
         }
 
-        dev_info(&pdev->dev, "PCI slot [%s] %s (IRQ: %d)\n",
+        pci_info(pdev, "PCI slot [%s] %s (IRQ: %d)\n",
                  php_slot->name, added ? "added" : "removed", irq);
         INIT_WORK(&event->work, pnv_php_event_handler);
         event->added = added;
@@ -782,7 +771,7 @@ static void pnv_php_init_irq(struct pnv_php_slot *php_slot, int irq)
         /* Allocate workqueue */
         php_slot->wq = alloc_workqueue("pciehp-%s", 0, 0, php_slot->name);
         if (!php_slot->wq) {
-                dev_warn(&pdev->dev, "Cannot alloc workqueue\n");
+                pci_warn(pdev, "Cannot alloc workqueue\n");
                 pnv_php_disable_irq(php_slot, true);
                 return;
         }
@@ -806,7 +795,7 @@ static void pnv_php_init_irq(struct pnv_php_slot *php_slot, int irq)
                           php_slot->name, php_slot);
         if (ret) {
                 pnv_php_disable_irq(php_slot, true);
-                dev_warn(&pdev->dev, "Error %d enabling IRQ %d\n", ret, irq);
+                pci_warn(pdev, "Error %d enabling IRQ %d\n", ret, irq);
                 return;
         }
 
@@ -842,7 +831,7 @@ static void pnv_php_enable_irq(struct pnv_php_slot *php_slot)
 
         ret = pci_enable_device(pdev);
         if (ret) {
-                dev_warn(&pdev->dev, "Error %d enabling device\n", ret);
+                pci_warn(pdev, "Error %d enabling device\n", ret);
                 return;
         }
 
diff --git a/drivers/pci/hotplug/rpadlpar.h b/drivers/pci/hotplug/rpadlpar.h
index 81df93931ad0..1eeb55d33171 100644
--- a/drivers/pci/hotplug/rpadlpar.h
+++ b/drivers/pci/hotplug/rpadlpar.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Interface for Dynamic Logical Partitioning of I/O Slots on
  * RPA-compliant PPC64 platform.
@@ -6,11 +7,6 @@
  * October 2003
  *
  * Copyright (C) 2003 IBM.
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
  */
 #ifndef _RPADLPAR_IO_H_
 #define _RPADLPAR_IO_H_
diff --git a/drivers/pci/hotplug/rpadlpar_core.c b/drivers/pci/hotplug/rpadlpar_core.c
index a3449d717a99..e2356a9c7088 100644
--- a/drivers/pci/hotplug/rpadlpar_core.c
+++ b/drivers/pci/hotplug/rpadlpar_core.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Interface for Dynamic Logical Partitioning of I/O Slots on
  * RPA-compliant PPC64 platform.
@@ -8,11 +9,6 @@
  * October 2003
  *
  * Copyright (C) 2003 IBM.
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
  */
 
 #undef DEBUG
@@ -27,6 +23,7 @@
 #include <linux/mutex.h>
 #include <asm/rtas.h>
 #include <asm/vio.h>
+#include <linux/firmware.h>
 
 #include "../pci.h"
 #include "rpaphp.h"
@@ -44,15 +41,14 @@ static struct device_node *find_vio_slot_node(char *drc_name)
 {
         struct device_node *parent = of_find_node_by_name(NULL, "vdevice");
         struct device_node *dn = NULL;
-        char *name;
         int rc;
 
         if (!parent)
                 return NULL;
 
         while ((dn = of_get_next_child(parent, dn))) {
-                rc = rpaphp_get_drc_props(dn, NULL, &name, NULL, NULL);
-                if ((rc == 0) && (!strcmp(drc_name, name)))
+                rc = rpaphp_check_drc_props(dn, drc_name, NULL);
+                if (rc == 0)
                         break;
         }
 
@@ -64,15 +60,12 @@ static struct device_node *find_php_slot_pci_node(char *drc_name,
                                                   char *drc_type)
 {
         struct device_node *np = NULL;
-        char *name;
-        char *type;
         int rc;
 
         while ((np = of_find_node_by_name(np, "pci"))) {
-                rc = rpaphp_get_drc_props(np, NULL, &name, &type, NULL);
+                rc = rpaphp_check_drc_props(np, drc_name, drc_type);
                 if (rc == 0)
-                        if (!strcmp(drc_name, name) && !strcmp(drc_type, type))
-                                break;
+                        break;
         }
 
         return np;
diff --git a/drivers/pci/hotplug/rpadlpar_sysfs.c b/drivers/pci/hotplug/rpadlpar_sysfs.c
index edb5d8a53020..cdbfa5df3a51 100644
--- a/drivers/pci/hotplug/rpadlpar_sysfs.c
+++ b/drivers/pci/hotplug/rpadlpar_sysfs.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Interface for Dynamic Logical Partitioning of I/O Slots on
  * RPA-compliant PPC64 platform.
@@ -6,16 +7,12 @@
  * October 2003
  *
  * Copyright (C) 2003 IBM.
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
  */
 #include <linux/kobject.h>
 #include <linux/string.h>
 #include <linux/pci.h>
 #include <linux/pci_hotplug.h>
+#include "rpaphp.h"
 #include "rpadlpar.h"
 #include "../pci.h"
 
@@ -27,8 +24,6 @@
 #define ADD_SLOT_ATTR_NAME    add_slot
 #define REMOVE_SLOT_ATTR_NAME remove_slot
 
-#define MAX_DRC_NAME_LEN 64
-
 static ssize_t add_slot_store(struct kobject *kobj, struct kobj_attribute *attr,
                               const char *buf, size_t nbytes)
 {
diff --git a/drivers/pci/hotplug/rpaphp.h b/drivers/pci/hotplug/rpaphp.h
index 7db024e68fe6..c8311724bd76 100644
--- a/drivers/pci/hotplug/rpaphp.h
+++ b/drivers/pci/hotplug/rpaphp.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * PCI Hot Plug Controller Driver for RPA-compliant PPC64 platform.
  *
@@ -5,21 +6,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <lxie@us.ibm.com>,
  *
  */
@@ -64,6 +50,10 @@ extern bool rpaphp_debug;
 #define CONFIGURED      1
 #define EMPTY           0
 
+/* DRC constants */
+
+#define MAX_DRC_NAME_LEN 64
+
 /*
  * struct slot - slot information for each *physical* slot
  */
@@ -91,8 +81,8 @@ int rpaphp_get_sensor_state(struct slot *slot, int *state);
 
 /* rpaphp_core.c */
 int rpaphp_add_slot(struct device_node *dn);
-int rpaphp_get_drc_props(struct device_node *dn, int *drc_index,
-                char **drc_name, char **drc_type, int *drc_power_domain);
+int rpaphp_check_drc_props(struct device_node *dn, char *drc_name,
+                char *drc_type);
 
 /* rpaphp_slot.c */
 void dealloc_slot_struct(struct slot *slot);
diff --git a/drivers/pci/hotplug/rpaphp_core.c b/drivers/pci/hotplug/rpaphp_core.c
index 1e29abaaea08..fb5e0845429d 100644
--- a/drivers/pci/hotplug/rpaphp_core.c
+++ b/drivers/pci/hotplug/rpaphp_core.c
@@ -1,24 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * PCI Hot Plug Controller Driver for RPA-compliant PPC64 platform.
  * Copyright (C) 2003 Linda Xie <lxie@us.ibm.com>
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <lxie@us.ibm.com>
  *
  */
@@ -30,6 +16,7 @@
 #include <linux/smp.h>
 #include <linux/init.h>
 #include <linux/vmalloc.h>
+#include <asm/firmware.h>
 #include <asm/eeh.h>       /* for eeh_add_device() */
 #include <asm/rtas.h>           /* rtas_call */
 #include <asm/pci-bridge.h>     /* for pci_controller */
@@ -196,25 +183,21 @@ static int get_children_props(struct device_node *dn, const int **drc_indexes,
         return 0;
 }
 
-/* To get the DRC props describing the current node, first obtain it's
- * my-drc-index property.  Next obtain the DRC list from it's parent.  Use
- * the my-drc-index for correlation, and obtain the requested properties.
+
+/* Verify the existence of 'drc_name' and/or 'drc_type' within the
+ * current node.  First obtain it's my-drc-index property.  Next,
+ * obtain the DRC info from it's parent.  Use the my-drc-index for
+ * correlation, and obtain/validate the requested properties.
  */
-int rpaphp_get_drc_props(struct device_node *dn, int *drc_index,
-                char **drc_name, char **drc_type, int *drc_power_domain)
+
+static int rpaphp_check_drc_props_v1(struct device_node *dn, char *drc_name,
+                                char *drc_type, unsigned int my_index)
 {
+        char *name_tmp, *type_tmp;
         const int *indexes, *names;
         const int *types, *domains;
-        const unsigned int *my_index;
-        char *name_tmp, *type_tmp;
         int i, rc;
 
-        my_index = of_get_property(dn, "ibm,my-drc-index", NULL);
-        if (!my_index) {
-                /* Node isn't DLPAR/hotplug capable */
-                return -EINVAL;
-        }
-
         rc = get_children_props(dn->parent, &indexes, &names, &types, &domains);
         if (rc < 0) {
                 return -EINVAL;
@@ -225,24 +208,84 @@ int rpaphp_get_drc_props(struct device_node *dn, int *drc_index,
 
         /* Iterate through parent properties, looking for my-drc-index */
         for (i = 0; i < be32_to_cpu(indexes[0]); i++) {
-                if ((unsigned int) indexes[i + 1] == *my_index) {
-                        if (drc_name)
-                                *drc_name = name_tmp;
-                        if (drc_type)
-                                *drc_type = type_tmp;
-                        if (drc_index)
-                                *drc_index = be32_to_cpu(*my_index);
-                        if (drc_power_domain)
-                                *drc_power_domain = be32_to_cpu(domains[i+1]);
-                        return 0;
-                }
+                if ((unsigned int) indexes[i + 1] == my_index)
+                        break;
+
                 name_tmp += (strlen(name_tmp) + 1);
                 type_tmp += (strlen(type_tmp) + 1);
         }
 
+        if (((drc_name == NULL) || (drc_name && !strcmp(drc_name, name_tmp))) &&
+            ((drc_type == NULL) || (drc_type && !strcmp(drc_type, type_tmp))))
+                return 0;
+
+        return -EINVAL;
+}
+
+static int rpaphp_check_drc_props_v2(struct device_node *dn, char *drc_name,
+                                char *drc_type, unsigned int my_index)
+{
+        struct property *info;
+        unsigned int entries;
+        struct of_drc_info drc;
+        const __be32 *value;
+        char cell_drc_name[MAX_DRC_NAME_LEN];
+        int j, fndit;
+
+        info = of_find_property(dn->parent, "ibm,drc-info", NULL);
+        if (info == NULL)
+                return -EINVAL;
+
+        value = of_prop_next_u32(info, NULL, &entries);
+        if (!value)
+                return -EINVAL;
+
+        for (j = 0; j < entries; j++) {
+                of_read_drc_info_cell(&info, &value, &drc);
+
+                /* Should now know end of current entry */
+
+                if (my_index > drc.last_drc_index)
+                        continue;
+
+                fndit = 1;
+                break;
+        }
+        /* Found it */
+
+        if (fndit)
+                sprintf(cell_drc_name, "%s%d", drc.drc_name_prefix, 
+                        my_index);
+
+        if (((drc_name == NULL) ||
+             (drc_name && !strcmp(drc_name, cell_drc_name))) &&
+            ((drc_type == NULL) ||
+             (drc_type && !strcmp(drc_type, drc.drc_type))))
+                return 0;
+
         return -EINVAL;
 }
-EXPORT_SYMBOL_GPL(rpaphp_get_drc_props);
+
+int rpaphp_check_drc_props(struct device_node *dn, char *drc_name,
+                        char *drc_type)
+{
+        const unsigned int *my_index;
+
+        my_index = of_get_property(dn, "ibm,my-drc-index", NULL);
+        if (!my_index) {
+                /* Node isn't DLPAR/hotplug capable */
+                return -EINVAL;
+        }
+
+        if (firmware_has_feature(FW_FEATURE_DRC_INFO))
+                return rpaphp_check_drc_props_v2(dn, drc_name, drc_type,
+                                                *my_index);
+        else
+                return rpaphp_check_drc_props_v1(dn, drc_name, drc_type,
+                                                *my_index);
+}
+EXPORT_SYMBOL_GPL(rpaphp_check_drc_props);
+
 
 static int is_php_type(char *drc_type)
 {
diff --git a/drivers/pci/hotplug/rpaphp_pci.c b/drivers/pci/hotplug/rpaphp_pci.c
index 32aabc533be8..0aac33e15dab 100644
--- a/drivers/pci/hotplug/rpaphp_pci.c
+++ b/drivers/pci/hotplug/rpaphp_pci.c
@@ -1,24 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * PCI Hot Plug Controller Driver for RPA-compliant PPC64 platform.
  * Copyright (C) 2003 Linda Xie <lxie@us.ibm.com>
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <lxie@us.ibm.com>
  *
  */
diff --git a/drivers/pci/hotplug/rpaphp_slot.c b/drivers/pci/hotplug/rpaphp_slot.c
index 489862360f2c..3840a2075e6a 100644
--- a/drivers/pci/hotplug/rpaphp_slot.c
+++ b/drivers/pci/hotplug/rpaphp_slot.c
@@ -1,24 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * RPA Virtual I/O device functions
  * Copyright (C) 2004 Linda Xie <lxie@us.ibm.com>
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <lxie@us.ibm.com>
  *
  */
diff --git a/drivers/pci/hotplug/s390_pci_hpc.c b/drivers/pci/hotplug/s390_pci_hpc.c
index 530d0e49f2ed..ffdc2977395d 100644
--- a/drivers/pci/hotplug/s390_pci_hpc.c
+++ b/drivers/pci/hotplug/s390_pci_hpc.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * PCI Hot Plug Controller Driver for System z
  *
@@ -5,8 +6,6 @@
  *
  * Author(s):
  *   Jan Glauber <jang@linux.vnet.ibm.com>
- *
- * License: GPL
  */
 
 #define KMSG_COMPONENT "zpci"
diff --git a/drivers/pci/hotplug/sgi_hotplug.c b/drivers/pci/hotplug/sgi_hotplug.c
index 339bce0403dd..78b6bdbb3a39 100644
--- a/drivers/pci/hotplug/sgi_hotplug.c
+++ b/drivers/pci/hotplug/sgi_hotplug.c
@@ -1,8 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * Copyright (C) 2005-2006 Silicon Graphics, Inc. All rights reserved.
  *
  * This work was based on the 2.4/2.6 kernel development by Dick Reigner.
@@ -245,18 +242,18 @@ static int sn_slot_enable(struct hotplug_slot *bss_hotplug_slot,
 
 
         if (rc == PCI_SLOT_ALREADY_UP) {
-                dev_dbg(&slot->pci_bus->self->dev, "is already active\n");
+                pci_dbg(slot->pci_bus->self, "is already active\n");
                 return 1; /* return 1 to user */
         }
 
         if (rc == PCI_L1_ERR) {
-                dev_dbg(&slot->pci_bus->self->dev, "L1 failure %d with message: %s",
+                pci_dbg(slot->pci_bus->self, "L1 failure %d with message: %s",
                         resp.resp_sub_errno, resp.resp_l1_msg);
                 return -EPERM;
         }
 
         if (rc) {
-                dev_dbg(&slot->pci_bus->self->dev, "insert failed with error %d sub-error %d\n",
+                pci_dbg(slot->pci_bus->self, "insert failed with error %d sub-error %d\n",
                         rc, resp.resp_sub_errno);
                 return -EIO;
         }
@@ -281,23 +278,23 @@ static int sn_slot_disable(struct hotplug_slot *bss_hotplug_slot,
 
         if ((action == PCI_REQ_SLOT_ELIGIBLE) &&
             (rc == PCI_SLOT_ALREADY_DOWN)) {
-                dev_dbg(&slot->pci_bus->self->dev, "Slot %s already inactive\n", slot->physical_path);
+                pci_dbg(slot->pci_bus->self, "Slot %s already inactive\n", slot->physical_path);
                 return 1; /* return 1 to user */
         }
 
         if ((action == PCI_REQ_SLOT_ELIGIBLE) && (rc == PCI_EMPTY_33MHZ)) {
-                dev_dbg(&slot->pci_bus->self->dev, "Cannot remove last 33MHz card\n");
+                pci_dbg(slot->pci_bus->self, "Cannot remove last 33MHz card\n");
                 return -EPERM;
         }
 
         if ((action == PCI_REQ_SLOT_ELIGIBLE) && (rc == PCI_L1_ERR)) {
-                dev_dbg(&slot->pci_bus->self->dev, "L1 failure %d with message \n%s\n",
+                pci_dbg(slot->pci_bus->self, "L1 failure %d with message \n%s\n",
                         resp.resp_sub_errno, resp.resp_l1_msg);
                 return -EPERM;
         }
 
         if ((action == PCI_REQ_SLOT_ELIGIBLE) && rc) {
-                dev_dbg(&slot->pci_bus->self->dev, "remove failed with error %d sub-error %d\n",
+                pci_dbg(slot->pci_bus->self, "remove failed with error %d sub-error %d\n",
                         rc, resp.resp_sub_errno);
                 return -EIO;
         }
@@ -308,12 +305,12 @@ static int sn_slot_disable(struct hotplug_slot *bss_hotplug_slot,
         if ((action == PCI_REQ_SLOT_DISABLE) && !rc) {
                 pcibus_info = SN_PCIBUS_BUSSOFT_INFO(slot->pci_bus);
                 pcibus_info->pbi_enabled_devices &= ~(1 << device_num);
-                dev_dbg(&slot->pci_bus->self->dev, "remove successful\n");
+                pci_dbg(slot->pci_bus->self, "remove successful\n");
                 return 0;
         }
 
         if ((action == PCI_REQ_SLOT_DISABLE) && rc) {
-                dev_dbg(&slot->pci_bus->self->dev, "remove failed rc = %d\n", rc);
+                pci_dbg(slot->pci_bus->self, "remove failed rc = %d\n", rc);
         }
 
         return rc;
@@ -366,7 +363,7 @@ static int enable_slot(struct hotplug_slot *bss_hotplug_slot)
         num_funcs = pci_scan_slot(slot->pci_bus,
                                   PCI_DEVFN(slot->device_num + 1, 0));
         if (!num_funcs) {
-                dev_dbg(&slot->pci_bus->self->dev, "no device in slot\n");
+                pci_dbg(slot->pci_bus->self, "no device in slot\n");
                 mutex_unlock(&sn_hotplug_mutex);
                 return -ENODEV;
         }
@@ -412,7 +409,7 @@ static int enable_slot(struct hotplug_slot *bss_hotplug_slot)
                 phandle = acpi_device_handle(PCI_CONTROLLER(slot->pci_bus)->companion);
 
                 if (acpi_bus_get_device(phandle, &pdevice)) {
-                        dev_dbg(&slot->pci_bus->self->dev, "no parent device, assuming NULL\n");
+                        pci_dbg(slot->pci_bus->self, "no parent device, assuming NULL\n");
                         pdevice = NULL;
                 }
 
@@ -463,9 +460,9 @@ static int enable_slot(struct hotplug_slot *bss_hotplug_slot)
         mutex_unlock(&sn_hotplug_mutex);
 
         if (rc == 0)
-                dev_dbg(&slot->pci_bus->self->dev, "insert operation successful\n");
+                pci_dbg(slot->pci_bus->self, "insert operation successful\n");
         else
-                dev_dbg(&slot->pci_bus->self->dev, "insert operation failed rc = %d\n", rc);
+                pci_dbg(slot->pci_bus->self, "insert operation failed rc = %d\n", rc);
 
         return rc;
 }
@@ -643,16 +640,16 @@ static int sn_hotplug_slot_register(struct pci_bus *pci_bus)
                 if (rc)
                         goto register_err;
         }
-        dev_dbg(&pci_bus->self->dev, "Registered bus with hotplug\n");
+        pci_dbg(pci_bus->self, "Registered bus with hotplug\n");
         return rc;
 
 register_err:
-        dev_dbg(&pci_bus->self->dev, "bus failed to register with err = %d\n",
+        pci_dbg(pci_bus->self, "bus failed to register with err = %d\n",
                 rc);
 
 alloc_err:
         if (rc == -ENOMEM)
-                dev_dbg(&pci_bus->self->dev, "Memory allocation error\n");
+                pci_dbg(pci_bus->self, "Memory allocation error\n");
 
         /* destroy THIS element */
         if (bss_hotplug_slot)
@@ -685,10 +682,10 @@ static int __init sn_pci_hotplug_init(void)
 
                 rc = sn_pci_bus_valid(pci_bus);
                 if (rc != 1) {
-                        dev_dbg(&pci_bus->self->dev, "not a valid hotplug bus\n");
+                        pci_dbg(pci_bus->self, "not a valid hotplug bus\n");
                         continue;
                 }
-                dev_dbg(&pci_bus->self->dev, "valid hotplug bus\n");
+                pci_dbg(pci_bus->self, "valid hotplug bus\n");
 
                 rc = sn_hotplug_slot_register(pci_bus);
                 if (!rc) {
diff --git a/drivers/pci/hotplug/shpchp.h b/drivers/pci/hotplug/shpchp.h
index 70c7ea6af034..c55730b61c9a 100644
--- a/drivers/pci/hotplug/shpchp.h
+++ b/drivers/pci/hotplug/shpchp.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Standard Hot Plug Controller Driver
  *
@@ -8,21 +9,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  *
  */
@@ -62,15 +48,15 @@ do {									\
 #define ctrl_dbg(ctrl, format, arg...)                                  \
         do {                                                            \
                 if (shpchp_debug)                                       \
-                        dev_printk(KERN_DEBUG, &ctrl->pci_dev->dev,     \
+                        pci_printk(KERN_DEBUG, ctrl->pci_dev,           \
                                         format, ## arg);                \
         } while (0)
 #define ctrl_err(ctrl, format, arg...)                                  \
-        dev_err(&ctrl->pci_dev->dev, format, ## arg)
+        pci_err(ctrl->pci_dev, format, ## arg)
 #define ctrl_info(ctrl, format, arg...)                                 \
-        dev_info(&ctrl->pci_dev->dev, format, ## arg)
+        pci_info(ctrl->pci_dev, format, ## arg)
 #define ctrl_warn(ctrl, format, arg...)                                 \
-        dev_warn(&ctrl->pci_dev->dev, format, ## arg)
+        pci_warn(ctrl->pci_dev, format, ## arg)
 
 
 #define SLOT_NAME_SIZE 10
diff --git a/drivers/pci/hotplug/shpchp_core.c b/drivers/pci/hotplug/shpchp_core.c
index 7bfb87bd2b7e..1f0f96908b5a 100644
--- a/drivers/pci/hotplug/shpchp_core.c
+++ b/drivers/pci/hotplug/shpchp_core.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Standard Hot Plug Controller Driver
  *
@@ -8,21 +9,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
  *
  */
@@ -305,10 +291,9 @@ static int shpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                 return -ENODEV;
 
         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
-        if (!ctrl) {
-                dev_err(&pdev->dev, "%s: Out of memory\n", __func__);
+        if (!ctrl)
                 goto err_out_none;
-        }
+
         INIT_LIST_HEAD(&ctrl->slot_list);
 
         rc = shpc_init(ctrl, pdev);
diff --git a/drivers/pci/hotplug/shpchp_ctrl.c b/drivers/pci/hotplug/shpchp_ctrl.c
index 10c7927599b3..bedda5bda910 100644
--- a/drivers/pci/hotplug/shpchp_ctrl.c
+++ b/drivers/pci/hotplug/shpchp_ctrl.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Standard Hot Plug Controller Driver
  *
@@ -8,21 +9,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
  *
  */
diff --git a/drivers/pci/hotplug/shpchp_hpc.c b/drivers/pci/hotplug/shpchp_hpc.c
index 4810e9626d9f..db047284c291 100644
--- a/drivers/pci/hotplug/shpchp_hpc.c
+++ b/drivers/pci/hotplug/shpchp_hpc.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Standard PCI Hot Plug Driver
  *
@@ -8,21 +9,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  *
  */
diff --git a/drivers/pci/hotplug/shpchp_pci.c b/drivers/pci/hotplug/shpchp_pci.c
index ea63db58b4b1..115701301487 100644
--- a/drivers/pci/hotplug/shpchp_pci.c
+++ b/drivers/pci/hotplug/shpchp_pci.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Standard Hot Plug Controller Driver
  *
@@ -8,21 +9,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
  *
  */
@@ -78,7 +64,6 @@ int shpchp_configure_device(struct slot *p_slot)
 int shpchp_unconfigure_device(struct slot *p_slot)
 {
         int rc = 0;
-        u8 bctl = 0;
         struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate;
         struct pci_dev *dev, *temp;
         struct controller *ctrl = p_slot->ctrl;
@@ -93,17 +78,6 @@ int shpchp_unconfigure_device(struct slot *p_slot)
                         continue;
 
                 pci_dev_get(dev);
-                if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
-                        pci_read_config_byte(dev, PCI_BRIDGE_CONTROL, &bctl);
-                        if (bctl & PCI_BRIDGE_CTL_VGA) {
-                                ctrl_err(ctrl,
-                                         "Cannot remove display device %s\n",
-                                         pci_name(dev));
-                                pci_dev_put(dev);
-                                rc = -EINVAL;
-                                break;
-                        }
-                }
                 pci_stop_and_remove_bus_device(dev);
                 pci_dev_put(dev);
         }
diff --git a/drivers/pci/hotplug/shpchp_sysfs.c b/drivers/pci/hotplug/shpchp_sysfs.c
index 7efb56a28c9f..45658bb5c554 100644
--- a/drivers/pci/hotplug/shpchp_sysfs.c
+++ b/drivers/pci/hotplug/shpchp_sysfs.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Compaq Hot Plug Controller Driver
  *
@@ -7,21 +8,6 @@
  *
  * All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
  * Send feedback to <greg@kroah.com>
  *
  */
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index 6bacb8995e96..677924ae0350 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * drivers/pci/iov.c
  *
@@ -259,19 +260,19 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
                         nres++;
         }
         if (nres != iov->nres) {
-                dev_err(&dev->dev, "not enough MMIO resources for SR-IOV\n");
+                pci_err(dev, "not enough MMIO resources for SR-IOV\n");
                 return -ENOMEM;
         }
 
         bus = pci_iov_virtfn_bus(dev, nr_virtfn - 1);
         if (bus > dev->bus->busn_res.end) {
-                dev_err(&dev->dev, "can't enable %d VFs (bus %02x out of range of %pR)\n",
+                pci_err(dev, "can't enable %d VFs (bus %02x out of range of %pR)\n",
                         nr_virtfn, bus, &dev->bus->busn_res);
                 return -ENOMEM;
         }
 
         if (pci_enable_resources(dev, bars)) {
-                dev_err(&dev->dev, "SR-IOV: IOV BARS not allocated\n");
+                pci_err(dev, "SR-IOV: IOV BARS not allocated\n");
                 return -ENOMEM;
         }
 
@@ -298,7 +299,7 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
 
         rc = pcibios_sriov_enable(dev, initial);
         if (rc) {
-                dev_err(&dev->dev, "failure %d from pcibios_sriov_enable()\n", rc);
+                pci_err(dev, "failure %d from pcibios_sriov_enable()\n", rc);
                 goto err_pcibios;
         }
 
@@ -432,7 +433,7 @@ found:
                 }
                 iov->barsz[i] = resource_size(res);
                 res->end = res->start + resource_size(res) * total - 1;
-                dev_info(&dev->dev, "VF(n) BAR%d space: %pR (contains BAR%d for %d VFs)\n",
+                pci_info(dev, "VF(n) BAR%d space: %pR (contains BAR%d for %d VFs)\n",
                          i, res, i, total);
                 i += bar64;
                 nres++;
@@ -636,6 +637,17 @@ void pci_restore_iov_state(struct pci_dev *dev)
 }
 
 /**
+ * pci_vf_drivers_autoprobe - set PF property drivers_autoprobe for VFs
+ * @dev: the PCI device
+ * @auto_probe: set VF drivers auto probe flag
+ */
+void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool auto_probe)
+{
+        if (dev->is_physfn)
+                dev->sriov->drivers_autoprobe = auto_probe;
+}
+
+/**
  * pci_iov_bus_range - find bus range used by Virtual Function
  * @bus: the PCI bus
  *
diff --git a/drivers/pci/irq.c b/drivers/pci/irq.c
index 10929cd43d5d..2a808e10645f 100644
--- a/drivers/pci/irq.c
+++ b/drivers/pci/irq.c
@@ -16,11 +16,10 @@ static void pci_note_irq_problem(struct pci_dev *pdev, const char *reason)
 {
         struct pci_dev *parent = to_pci_dev(pdev->dev.parent);
 
-        dev_err(&pdev->dev,
-                "Potentially misrouted IRQ (Bridge %s %04x:%04x)\n",
+        pci_err(pdev, "Potentially misrouted IRQ (Bridge %s %04x:%04x)\n",
                 dev_name(&parent->dev), parent->vendor, parent->device);
-        dev_err(&pdev->dev, "%s\n", reason);
-        dev_err(&pdev->dev, "Please report to linux-kernel@vger.kernel.org\n");
+        pci_err(pdev, "%s\n", reason);
+        pci_err(pdev, "Please report to linux-kernel@vger.kernel.org\n");
         WARN_ON(1);
 }
 
diff --git a/drivers/pci/mmap.c b/drivers/pci/mmap.c
index 9a5e5a9055eb..814a3ce341fc 100644
--- a/drivers/pci/mmap.c
+++ b/drivers/pci/mmap.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * mmap.c — generic PCI resource mmap helper
  *
  * Copyright © 2017 Amazon.com, Inc. or its affiliates.
  *
  * Author: David Woodhouse <dwmw2@infradead.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include <linux/kernel.h>
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index e06607167858..8b0729c94bb7 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * File:        msi.c
  * Purpose:     PCI Message Signaled Interrupt (MSI)
@@ -578,7 +579,7 @@ static int msi_verify_entries(struct pci_dev *dev)
         for_each_pci_msi_entry(entry, dev) {
                 if (!dev->no_64bit_msi || !entry->msg.address_hi)
                         continue;
-                dev_err(&dev->dev, "Device has broken 64-bit MSI but arch"
+                pci_err(dev, "Device has broken 64-bit MSI but arch"
                         " tried to assign one above 4G\n");
                 return -EIO;
         }
@@ -962,7 +963,7 @@ static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
 
         /* Check whether driver already requested for MSI irq */
         if (dev->msi_enabled) {
-                dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
+                pci_info(dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
                 return -EINVAL;
         }
         return msix_capability_init(dev, entries, nvec, affd);
@@ -1032,8 +1033,7 @@ static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
 
         /* Check whether driver already requested MSI-X irqs */
         if (dev->msix_enabled) {
-                dev_info(&dev->dev,
-                         "can't enable MSI (MSI-X already enabled)\n");
+                pci_info(dev, "can't enable MSI (MSI-X already enabled)\n");
                 return -EINVAL;
         }
 
diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index e112da11630e..a28355c273ae 100644
--- a/drivers/pci/of.c
+++ b/drivers/pci/of.c
@@ -1,19 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * PCI <-> OF mapping helpers
  *
  * Copyright 2011 IBM Corp.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
  */
+#define pr_fmt(fmt)     "PCI: OF: " fmt
 
 #include <linux/irqdomain.h>
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
+#include <linux/of_address.h>
 #include <linux/of_pci.h>
 #include "pci.h"
 
@@ -51,8 +49,9 @@ struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus)
         if (WARN_ON(bus->self || bus->parent))
                 return NULL;
 
-        /* Look for a node pointer in either the intermediary device we
-         * create above the root bus or it's own parent. Normally only
+        /*
+         * Look for a node pointer in either the intermediary device we
+         * create above the root bus or its own parent. Normally only
          * the later is populated.
          */
         if (bus->bridge->of_node)
@@ -88,3 +87,561 @@ struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus)
         return NULL;
 #endif
 }
+
+static inline int __of_pci_pci_compare(struct device_node *node,
+                                       unsigned int data)
+{
+        int devfn;
+
+        devfn = of_pci_get_devfn(node);
+        if (devfn < 0)
+                return 0;
+
+        return devfn == data;
+}
+
+struct device_node *of_pci_find_child_device(struct device_node *parent,
+                                             unsigned int devfn)
+{
+        struct device_node *node, *node2;
+
+        for_each_child_of_node(parent, node) {
+                if (__of_pci_pci_compare(node, devfn))
+                        return node;
+                /*
+                 * Some OFs create a parent node "multifunc-device" as
+                 * a fake root for all functions of a multi-function
+                 * device we go down them as well.
+                 */
+                if (!strcmp(node->name, "multifunc-device")) {
+                        for_each_child_of_node(node, node2) {
+                                if (__of_pci_pci_compare(node2, devfn)) {
+                                        of_node_put(node);
+                                        return node2;
+                                }
+                        }
+                }
+        }
+        return NULL;
+}
+EXPORT_SYMBOL_GPL(of_pci_find_child_device);
+
+/**
+ * of_pci_get_devfn() - Get device and function numbers for a device node
+ * @np: device node
+ *
+ * Parses a standard 5-cell PCI resource and returns an 8-bit value that can
+ * be passed to the PCI_SLOT() and PCI_FUNC() macros to extract the device
+ * and function numbers respectively. On error a negative error code is
+ * returned.
+ */
+int of_pci_get_devfn(struct device_node *np)
+{
+        u32 reg[5];
+        int error;
+
+        error = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg));
+        if (error)
+                return error;
+
+        return (reg[0] >> 8) & 0xff;
+}
+EXPORT_SYMBOL_GPL(of_pci_get_devfn);
+
+/**
+ * of_pci_parse_bus_range() - parse the bus-range property of a PCI device
+ * @node: device node
+ * @res: address to a struct resource to return the bus-range
+ *
+ * Returns 0 on success or a negative error-code on failure.
+ */
+int of_pci_parse_bus_range(struct device_node *node, struct resource *res)
+{
+        u32 bus_range[2];
+        int error;
+
+        error = of_property_read_u32_array(node, "bus-range", bus_range,
+                                           ARRAY_SIZE(bus_range));
+        if (error)
+                return error;
+
+        res->name = node->name;
+        res->start = bus_range[0];
+        res->end = bus_range[1];
+        res->flags = IORESOURCE_BUS;
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(of_pci_parse_bus_range);
+
+/**
+ * This function will try to obtain the host bridge domain number by
+ * finding a property called "linux,pci-domain" of the given device node.
+ *
+ * @node: device tree node with the domain information
+ *
+ * Returns the associated domain number from DT in the range [0-0xffff], or
+ * a negative value if the required property is not found.
+ */
+int of_get_pci_domain_nr(struct device_node *node)
+{
+        u32 domain;
+        int error;
+
+        error = of_property_read_u32(node, "linux,pci-domain", &domain);
+        if (error)
+                return error;
+
+        return (u16)domain;
+}
+EXPORT_SYMBOL_GPL(of_get_pci_domain_nr);
+
+/**
+ * This function will try to find the limitation of link speed by finding
+ * a property called "max-link-speed" of the given device node.
+ *
+ * @node: device tree node with the max link speed information
+ *
+ * Returns the associated max link speed from DT, or a negative value if the
+ * required property is not found or is invalid.
+ */
+int of_pci_get_max_link_speed(struct device_node *node)
+{
+        u32 max_link_speed;
+
+        if (of_property_read_u32(node, "max-link-speed", &max_link_speed) ||
+            max_link_speed > 4)
+                return -EINVAL;
+
+        return max_link_speed;
+}
+EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed);
+
+/**
+ * of_pci_check_probe_only - Setup probe only mode if linux,pci-probe-only
+ *                           is present and valid
+ */
+void of_pci_check_probe_only(void)
+{
+        u32 val;
+        int ret;
+
+        ret = of_property_read_u32(of_chosen, "linux,pci-probe-only", &val);
+        if (ret) {
+                if (ret == -ENODATA || ret == -EOVERFLOW)
+                        pr_warn("linux,pci-probe-only without valid value, ignoring\n");
+                return;
+        }
+
+        if (val)
+                pci_add_flags(PCI_PROBE_ONLY);
+        else
+                pci_clear_flags(PCI_PROBE_ONLY);
+
+        pr_info("PROBE_ONLY %sabled\n", val ? "en" : "dis");
+}
+EXPORT_SYMBOL_GPL(of_pci_check_probe_only);
+
+#if defined(CONFIG_OF_ADDRESS)
+/**
+ * of_pci_get_host_bridge_resources - Parse PCI host bridge resources from DT
+ * @dev: device node of the host bridge having the range property
+ * @busno: bus number associated with the bridge root bus
+ * @bus_max: maximum number of buses for this bridge
+ * @resources: list where the range of resources will be added after DT parsing
+ * @io_base: pointer to a variable that will contain on return the physical
+ * address for the start of the I/O range. Can be NULL if the caller doesn't
+ * expect I/O ranges to be present in the device tree.
+ *
+ * It is the caller's job to free the @resources list.
+ *
+ * This function will parse the "ranges" property of a PCI host bridge device
+ * node and setup the resource mapping based on its content. It is expected
+ * that the property conforms with the Power ePAPR document.
+ *
+ * It returns zero if the range parsing has been successful or a standard error
+ * value if it failed.
+ */
+int of_pci_get_host_bridge_resources(struct device_node *dev,
+                        unsigned char busno, unsigned char bus_max,
+                        struct list_head *resources, resource_size_t *io_base)
+{
+        struct resource_entry *window;
+        struct resource *res;
+        struct resource *bus_range;
+        struct of_pci_range range;
+        struct of_pci_range_parser parser;
+        char range_type[4];
+        int err;
+
+        if (io_base)
+                *io_base = (resource_size_t)OF_BAD_ADDR;
+
+        bus_range = kzalloc(sizeof(*bus_range), GFP_KERNEL);
+        if (!bus_range)
+                return -ENOMEM;
+
+        pr_info("host bridge %pOF ranges:\n", dev);
+
+        err = of_pci_parse_bus_range(dev, bus_range);
+        if (err) {
+                bus_range->start = busno;
+                bus_range->end = bus_max;
+                bus_range->flags = IORESOURCE_BUS;
+                pr_info("  No bus range found for %pOF, using %pR\n",
+                        dev, bus_range);
+        } else {
+                if (bus_range->end > bus_range->start + bus_max)
+                        bus_range->end = bus_range->start + bus_max;
+        }
+        pci_add_resource(resources, bus_range);
+
+        /* Check for ranges property */
+        err = of_pci_range_parser_init(&parser, dev);
+        if (err)
+                goto parse_failed;
+
+        pr_debug("Parsing ranges property...\n");
+        for_each_of_pci_range(&parser, &range) {
+                /* Read next ranges element */
+                if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO)
+                        snprintf(range_type, 4, " IO");
+                else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM)
+                        snprintf(range_type, 4, "MEM");
+                else
+                        snprintf(range_type, 4, "err");
+                pr_info("  %s %#010llx..%#010llx -> %#010llx\n", range_type,
+                        range.cpu_addr, range.cpu_addr + range.size - 1,
+                        range.pci_addr);
+
+                /*
+                 * If we failed translation or got a zero-sized region
+                 * then skip this range
+                 */
+                if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
+                        continue;
+
+                res = kzalloc(sizeof(struct resource), GFP_KERNEL);
+                if (!res) {
+                        err = -ENOMEM;
+                        goto parse_failed;
+                }
+
+                err = of_pci_range_to_resource(&range, dev, res);
+                if (err) {
+                        kfree(res);
+                        continue;
+                }
+
+                if (resource_type(res) == IORESOURCE_IO) {
+                        if (!io_base) {
+                                pr_err("I/O range found for %pOF. Please provide an io_base pointer to save CPU base address\n",
+                                        dev);
+                                err = -EINVAL;
+                                goto conversion_failed;
+                        }
+                        if (*io_base != (resource_size_t)OF_BAD_ADDR)
+                                pr_warn("More than one I/O resource converted for %pOF. CPU base address for old range lost!\n",
+                                        dev);
+                        *io_base = range.cpu_addr;
+                }
+
+                pci_add_resource_offset(resources, res, res->start - range.pci_addr);
+        }
+
+        return 0;
+
+conversion_failed:
+        kfree(res);
+parse_failed:
+        resource_list_for_each_entry(window, resources)
+                kfree(window->res);
+        pci_free_resource_list(resources);
+        return err;
+}
+EXPORT_SYMBOL_GPL(of_pci_get_host_bridge_resources);
+#endif /* CONFIG_OF_ADDRESS */
+
+/**
+ * of_pci_map_rid - Translate a requester ID through a downstream mapping.
+ * @np: root complex device node.
+ * @rid: PCI requester ID to map.
+ * @map_name: property name of the map to use.
+ * @map_mask_name: optional property name of the mask to use.
+ * @target: optional pointer to a target device node.
+ * @id_out: optional pointer to receive the translated ID.
+ *
+ * Given a PCI requester ID, look up the appropriate implementation-defined
+ * platform ID and/or the target device which receives transactions on that
+ * ID, as per the "iommu-map" and "msi-map" bindings. Either of @target or
+ * @id_out may be NULL if only the other is required. If @target points to
+ * a non-NULL device node pointer, only entries targeting that node will be
+ * matched; if it points to a NULL value, it will receive the device node of
+ * the first matching target phandle, with a reference held.
+ *
+ * Return: 0 on success or a standard error code on failure.
+ */
+int of_pci_map_rid(struct device_node *np, u32 rid,
+                   const char *map_name, const char *map_mask_name,
+                   struct device_node **target, u32 *id_out)
+{
+        u32 map_mask, masked_rid;
+        int map_len;
+        const __be32 *map = NULL;
+
+        if (!np || !map_name || (!target && !id_out))
+                return -EINVAL;
+
+        map = of_get_property(np, map_name, &map_len);
+        if (!map) {
+                if (target)
+                        return -ENODEV;
+                /* Otherwise, no map implies no translation */
+                *id_out = rid;
+                return 0;
+        }
+
+        if (!map_len || map_len % (4 * sizeof(*map))) {
+                pr_err("%pOF: Error: Bad %s length: %d\n", np,
+                        map_name, map_len);
+                return -EINVAL;
+        }
+
+        /* The default is to select all bits. */
+        map_mask = 0xffffffff;
+
+        /*
+         * Can be overridden by "{iommu,msi}-map-mask" property.
+         * If of_property_read_u32() fails, the default is used.
+         */
+        if (map_mask_name)
+                of_property_read_u32(np, map_mask_name, &map_mask);
+
+        masked_rid = map_mask & rid;
+        for ( ; map_len > 0; map_len -= 4 * sizeof(*map), map += 4) {
+                struct device_node *phandle_node;
+                u32 rid_base = be32_to_cpup(map + 0);
+                u32 phandle = be32_to_cpup(map + 1);
+                u32 out_base = be32_to_cpup(map + 2);
+                u32 rid_len = be32_to_cpup(map + 3);
+
+                if (rid_base & ~map_mask) {
+                        pr_err("%pOF: Invalid %s translation - %s-mask (0x%x) ignores rid-base (0x%x)\n",
+                                np, map_name, map_name,
+                                map_mask, rid_base);
+                        return -EFAULT;
+                }
+
+                if (masked_rid < rid_base || masked_rid >= rid_base + rid_len)
+                        continue;
+
+                phandle_node = of_find_node_by_phandle(phandle);
+                if (!phandle_node)
+                        return -ENODEV;
+
+                if (target) {
+                        if (*target)
+                                of_node_put(phandle_node);
+                        else
+                                *target = phandle_node;
+
+                        if (*target != phandle_node)
+                                continue;
+                }
+
+                if (id_out)
+                        *id_out = masked_rid - rid_base + out_base;
+
+                pr_debug("%pOF: %s, using mask %08x, rid-base: %08x, out-base: %08x, length: %08x, rid: %08x -> %08x\n",
+                        np, map_name, map_mask, rid_base, out_base,
+                        rid_len, rid, masked_rid - rid_base + out_base);
+                return 0;
+        }
+
+        pr_err("%pOF: Invalid %s translation - no match for rid 0x%x on %pOF\n",
+                np, map_name, rid, target && *target ? *target : NULL);
+        return -EFAULT;
+}
+
+#if IS_ENABLED(CONFIG_OF_IRQ)
+/**
+ * of_irq_parse_pci - Resolve the interrupt for a PCI device
+ * @pdev:       the device whose interrupt is to be resolved
+ * @out_irq:    structure of_irq filled by this function
+ *
+ * This function resolves the PCI interrupt for a given PCI device. If a
+ * device-node exists for a given pci_dev, it will use normal OF tree
+ * walking. If not, it will implement standard swizzling and walk up the
+ * PCI tree until an device-node is found, at which point it will finish
+ * resolving using the OF tree walking.
+ */
+static int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq)
+{
+        struct device_node *dn, *ppnode;
+        struct pci_dev *ppdev;
+        __be32 laddr[3];
+        u8 pin;
+        int rc;
+
+        /*
+         * Check if we have a device node, if yes, fallback to standard
+         * device tree parsing
+         */
+        dn = pci_device_to_OF_node(pdev);
+        if (dn) {
+                rc = of_irq_parse_one(dn, 0, out_irq);
+                if (!rc)
+                        return rc;
+        }
+
+        /*
+         * Ok, we don't, time to have fun. Let's start by building up an
+         * interrupt spec.  we assume #interrupt-cells is 1, which is standard
+         * for PCI. If you do different, then don't use that routine.
+         */
+        rc = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin);
+        if (rc != 0)
+                goto err;
+        /* No pin, exit with no error message. */
+        if (pin == 0)
+                return -ENODEV;
+
+        /* Now we walk up the PCI tree */
+        for (;;) {
+                /* Get the pci_dev of our parent */
+                ppdev = pdev->bus->self;
+
+                /* Ouch, it's a host bridge... */
+                if (ppdev == NULL) {
+                        ppnode = pci_bus_to_OF_node(pdev->bus);
+
+                        /* No node for host bridge ? give up */
+                        if (ppnode == NULL) {
+                                rc = -EINVAL;
+                                goto err;
+                        }
+                } else {
+                        /* We found a P2P bridge, check if it has a node */
+                        ppnode = pci_device_to_OF_node(ppdev);
+                }
+
+                /*
+                 * Ok, we have found a parent with a device-node, hand over to
+                 * the OF parsing code.
+                 * We build a unit address from the linux device to be used for
+                 * resolution. Note that we use the linux bus number which may
+                 * not match your firmware bus numbering.
+                 * Fortunately, in most cases, interrupt-map-mask doesn't
+                 * include the bus number as part of the matching.
+                 * You should still be careful about that though if you intend
+                 * to rely on this function (you ship a firmware that doesn't
+                 * create device nodes for all PCI devices).
+                 */
+                if (ppnode)
+                        break;
+
+                /*
+                 * We can only get here if we hit a P2P bridge with no node;
+                 * let's do standard swizzling and try again
+                 */
+                pin = pci_swizzle_interrupt_pin(pdev, pin);
+                pdev = ppdev;
+        }
+
+        out_irq->np = ppnode;
+        out_irq->args_count = 1;
+        out_irq->args[0] = pin;
+        laddr[0] = cpu_to_be32((pdev->bus->number << 16) | (pdev->devfn << 8));
+        laddr[1] = laddr[2] = cpu_to_be32(0);
+        rc = of_irq_parse_raw(laddr, out_irq);
+        if (rc)
+                goto err;
+        return 0;
+err:
+        if (rc == -ENOENT) {
+                dev_warn(&pdev->dev,
+                        "%s: no interrupt-map found, INTx interrupts not available\n",
+                        __func__);
+                pr_warn_once("%s: possibly some PCI slots don't have level triggered interrupts capability\n",
+                        __func__);
+        } else {
+                dev_err(&pdev->dev, "%s: failed with rc=%d\n", __func__, rc);
+        }
+        return rc;
+}
+
+/**
+ * of_irq_parse_and_map_pci() - Decode a PCI IRQ from the device tree and map to a VIRQ
+ * @dev: The PCI device needing an IRQ
+ * @slot: PCI slot number; passed when used as map_irq callback. Unused
+ * @pin: PCI IRQ pin number; passed when used as map_irq callback. Unused
+ *
+ * @slot and @pin are unused, but included in the function so that this
+ * function can be used directly as the map_irq callback to
+ * pci_assign_irq() and struct pci_host_bridge.map_irq pointer
+ */
+int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        struct of_phandle_args oirq;
+        int ret;
+
+        ret = of_irq_parse_pci(dev, &oirq);
+        if (ret)
+                return 0; /* Proper return code 0 == NO_IRQ */
+
+        return irq_create_of_mapping(&oirq);
+}
+EXPORT_SYMBOL_GPL(of_irq_parse_and_map_pci);
+#endif  /* CONFIG_OF_IRQ */
+
+int pci_parse_request_of_pci_ranges(struct device *dev,
+                                    struct list_head *resources,
+                                    struct resource **bus_range)
+{
+        int err, res_valid = 0;
+        struct device_node *np = dev->of_node;
+        resource_size_t iobase;
+        struct resource_entry *win, *tmp;
+
+        INIT_LIST_HEAD(resources);
+        err = of_pci_get_host_bridge_resources(np, 0, 0xff, resources, &iobase);
+        if (err)
+                return err;
+
+        err = devm_request_pci_bus_resources(dev, resources);
+        if (err)
+                goto out_release_res;
+
+        resource_list_for_each_entry_safe(win, tmp, resources) {
+                struct resource *res = win->res;
+
+                switch (resource_type(res)) {
+                case IORESOURCE_IO:
+                        err = pci_remap_iospace(res, iobase);
+                        if (err) {
+                                dev_warn(dev, "error %d: failed to map resource %pR\n",
+                                         err, res);
+                                resource_list_destroy_entry(win);
+                        }
+                        break;
+                case IORESOURCE_MEM:
+                        res_valid |= !(res->flags & IORESOURCE_PREFETCH);
+                        break;
+                case IORESOURCE_BUS:
+                        if (bus_range)
+                                *bus_range = res;
+                        break;
+                }
+        }
+
+        if (res_valid)
+                return 0;
+
+        dev_err(dev, "non-prefetchable memory resource required\n");
+        err = -EINVAL;
+
+ out_release_res:
+        pci_free_resource_list(resources);
+        return err;
+}
+
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index 4708eb9df71b..78157688dcc9 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * File:        pci-acpi.c
  * Purpose:     Provide PCI support in ACPI
@@ -542,7 +543,7 @@ static int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
         }
 
         if (!error)
-                dev_dbg(&dev->dev, "power state changed by ACPI to %s\n",
+                pci_dbg(dev, "power state changed by ACPI to %s\n",
                          acpi_power_state_string(state_conv[state]));
 
         return error;
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index 5958c8dda4e3..3bed6beda051 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -1,11 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * drivers/pci/pci-driver.c
  *
  * (C) Copyright 2002-2004, 2007 Greg Kroah-Hartman <greg@kroah.com>
  * (C) Copyright 2007 Novell Inc.
- *
- * Released under the GPL v2 only.
- *
  */
 
 #include <linux/pci.h>
diff --git a/drivers/pci/pci-mid.c b/drivers/pci/pci-mid.c
index a4ac940c7696..314e135014dc 100644
--- a/drivers/pci/pci-mid.c
+++ b/drivers/pci/pci-mid.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Intel MID platform PM support
  *
  * Copyright (C) 2016, Intel Corporation
  *
  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
  */
 
 #include <linux/init.h>
diff --git a/drivers/pci/pci-stub.c b/drivers/pci/pci-stub.c
index 886fb3570278..10d54f939048 100644
--- a/drivers/pci/pci-stub.c
+++ b/drivers/pci/pci-stub.c
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /* pci-stub - simple stub driver to reserve a pci device
  *
  * Copyright (C) 2008 Red Hat, Inc.
  * Author:
  *      Chris Wright
  *
- * This work is licensed under the terms of the GNU GPL, version 2.
- *
  * Usage is simple, allocate a new id to the stub driver and bind the
  * device to it.  For example:
  *
@@ -28,7 +27,7 @@ MODULE_PARM_DESC(ids, "Initial PCI IDs to add to the stub driver, format is "
 
 static int pci_stub_probe(struct pci_dev *dev, const struct pci_device_id *id)
 {
-        dev_info(&dev->dev, "claimed by stub\n");
+        pci_info(dev, "claimed by stub\n");
         return 0;
 }
 
diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index 06c7f0b85cd2..eb6bee8724cc 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.c
@@ -278,6 +278,16 @@ static ssize_t subordinate_bus_number_show(struct device *dev,
 }
 static DEVICE_ATTR_RO(subordinate_bus_number);
 
+static ssize_t ari_enabled_show(struct device *dev,
+                                struct device_attribute *attr,
+                                char *buf)
+{
+        struct pci_dev *pci_dev = to_pci_dev(dev);
+
+        return sprintf(buf, "%u\n", pci_ari_enabled(pci_dev->bus));
+}
+static DEVICE_ATTR_RO(ari_enabled);
+
 static ssize_t modalias_show(struct device *dev, struct device_attribute *attr,
                              char *buf)
 {
@@ -348,7 +358,7 @@ static ssize_t numa_node_store(struct device *dev,
                 return -EINVAL;
 
         add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
-        dev_alert(&pdev->dev, FW_BUG "Overriding NUMA node to %d.  Contact your vendor for updates.",
+        pci_alert(pdev, FW_BUG "Overriding NUMA node to %d.  Contact your vendor for updates.",
                   node);
 
         dev->numa_node = node;
@@ -411,7 +421,7 @@ static ssize_t msi_bus_store(struct device *dev, struct device_attribute *attr,
          */
         if (!subordinate) {
                 pdev->no_msi = !val;
-                dev_info(&pdev->dev, "MSI/MSI-X %s for future drivers\n",
+                pci_info(pdev, "MSI/MSI-X %s for future drivers\n",
                          val ? "allowed" : "disallowed");
                 return count;
         }
@@ -613,7 +623,7 @@ static ssize_t sriov_numvfs_store(struct device *dev,
 
         /* is PF driver loaded w/callback */
         if (!pdev->driver || !pdev->driver->sriov_configure) {
-                dev_info(&pdev->dev, "Driver doesn't support SRIOV configuration via sysfs\n");
+                pci_info(pdev, "Driver doesn't support SRIOV configuration via sysfs\n");
                 ret = -ENOENT;
                 goto exit;
         }
@@ -626,7 +636,7 @@ static ssize_t sriov_numvfs_store(struct device *dev,
 
         /* enable VFs */
         if (pdev->sriov->num_VFs) {
-                dev_warn(&pdev->dev, "%d VFs already enabled. Disable before enabling %d VFs\n",
+                pci_warn(pdev, "%d VFs already enabled. Disable before enabling %d VFs\n",
                          pdev->sriov->num_VFs, num_vfs);
                 ret = -EBUSY;
                 goto exit;
@@ -637,7 +647,7 @@ static ssize_t sriov_numvfs_store(struct device *dev,
                 goto exit;
 
         if (ret != num_vfs)
-                dev_warn(&pdev->dev, "%d VFs requested; only %d enabled\n",
+                pci_warn(pdev, "%d VFs requested; only %d enabled\n",
                          num_vfs, ret);
 
 exit:
@@ -786,6 +796,7 @@ static struct attribute *pci_dev_attrs[] = {
         &dev_attr_devspec.attr,
 #endif
         &dev_attr_driver_override.attr,
+        &dev_attr_ari_enabled.attr,
         NULL,
 };
 
@@ -1216,14 +1227,9 @@ static int pci_mmap_resource(struct kobject *kobj, struct bin_attribute *attr,
         if (res->flags & IORESOURCE_MEM && iomem_is_exclusive(res->start))
                 return -EINVAL;
 
-        if (!pci_mmap_fits(pdev, bar, vma, PCI_MMAP_SYSFS)) {
-                WARN(1, "process \"%s\" tried to map 0x%08lx bytes at page 0x%08lx on %s BAR %d (start 0x%16Lx, size 0x%16Lx)\n",
-                        current->comm, vma->vm_end-vma->vm_start, vma->vm_pgoff,
-                        pci_name(pdev), bar,
-                        (u64)pci_resource_start(pdev, bar),
-                        (u64)pci_resource_len(pdev, bar));
+        if (!pci_mmap_fits(pdev, bar, vma, PCI_MMAP_SYSFS))
                 return -EINVAL;
-        }
+
         mmap_type = res->flags & IORESOURCE_MEM ? pci_mmap_mem : pci_mmap_io;
 
         return pci_mmap_resource_range(pdev, bar, vma, mmap_type, write_combine);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 4a7c6864fdf4..f6a4dd10d9b0 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  *      PCI Bus Services, see include/linux/pci.h for further explanation.
  *
@@ -156,7 +157,7 @@ void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
          * Make sure the BAR is actually a memory resource, not an IO resource
          */
         if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
-                dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res);
+                pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
                 return NULL;
         }
         return ioremap_nocache(res->start, resource_size(res));
@@ -648,7 +649,7 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
          */
         if (state != PCI_D0 && dev->current_state <= PCI_D3cold
             && dev->current_state > state) {
-                dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n",
+                pci_err(dev, "invalid power transition (from state %d to %d)\n",
                         dev->current_state, state);
                 return -EINVAL;
         }
@@ -696,7 +697,7 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
         pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
         dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
         if (dev->current_state != state && printk_ratelimit())
-                dev_info(&dev->dev, "Refused to change power state, currently in D%d\n",
+                pci_info(dev, "Refused to change power state, currently in D%d\n",
                          dev->current_state);
 
         /*
@@ -970,7 +971,7 @@ pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
         case PM_EVENT_HIBERNATE:
                 return PCI_D3hot;
         default:
-                dev_info(&dev->dev, "unrecognized suspend event %d\n",
+                pci_info(dev, "unrecognized suspend event %d\n",
                          state.event);
                 BUG();
         }
@@ -1013,7 +1014,7 @@ static int pci_save_pcie_state(struct pci_dev *dev)
 
         save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
         if (!save_state) {
-                dev_err(&dev->dev, "buffer not found in %s\n", __func__);
+                pci_err(dev, "buffer not found in %s\n", __func__);
                 return -ENOMEM;
         }
 
@@ -1061,7 +1062,7 @@ static int pci_save_pcix_state(struct pci_dev *dev)
 
         save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
         if (!save_state) {
-                dev_err(&dev->dev, "buffer not found in %s\n", __func__);
+                pci_err(dev, "buffer not found in %s\n", __func__);
                 return -ENOMEM;
         }
 
@@ -1121,7 +1122,7 @@ static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
                 return;
 
         for (;;) {
-                dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
+                pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
                         offset, val, saved_val);
                 pci_write_config_dword(pdev, offset, saved_val);
                 if (retry-- <= 0)
@@ -1358,7 +1359,7 @@ static void pci_enable_bridge(struct pci_dev *dev)
 
         retval = pci_enable_device(dev);
         if (retval)
-                dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
+                pci_err(dev, "Error enabling bridge (%d), continuing\n",
                         retval);
         pci_set_master(dev);
 }
@@ -1458,6 +1459,7 @@ struct pci_devres {
         unsigned int pinned:1;
         unsigned int orig_intx:1;
         unsigned int restore_intx:1;
+        unsigned int mwi:1;
         u32 region_mask;
 };
 
@@ -1476,6 +1478,9 @@ static void pcim_release(struct device *gendev, void *res)
                 if (this->region_mask & (1 << i))
                         pci_release_region(dev, i);
 
+        if (this->mwi)
+                pci_clear_mwi(dev);
+
         if (this->restore_intx)
                 pci_intx(dev, this->orig_intx);
 
@@ -1863,7 +1868,7 @@ void pci_pme_active(struct pci_dev *dev, bool enable)
                         pme_dev = kmalloc(sizeof(struct pci_pme_device),
                                           GFP_KERNEL);
                         if (!pme_dev) {
-                                dev_warn(&dev->dev, "can't enable PME#\n");
+                                pci_warn(dev, "can't enable PME#\n");
                                 return;
                         }
                         pme_dev->dev = dev;
@@ -1887,7 +1892,7 @@ void pci_pme_active(struct pci_dev *dev, bool enable)
                 }
         }
 
-        dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
+        pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
 }
 EXPORT_SYMBOL(pci_pme_active);
 
@@ -2424,7 +2429,7 @@ void pci_pm_init(struct pci_dev *dev)
         pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
 
         if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
-                dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
+                pci_err(dev, "unsupported PM cap regs version (%u)\n",
                         pmc & PCI_PM_CAP_VER_MASK);
                 return;
         }
@@ -2444,15 +2449,14 @@ void pci_pm_init(struct pci_dev *dev)
                         dev->d2_support = true;
 
                 if (dev->d1_support || dev->d2_support)
-                        dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
+                        pci_printk(KERN_DEBUG, dev, "supports%s%s\n",
                                    dev->d1_support ? " D1" : "",
                                    dev->d2_support ? " D2" : "");
         }
 
         pmc &= PCI_PM_CAP_PME_MASK;
         if (pmc) {
-                dev_printk(KERN_DEBUG, &dev->dev,
-                         "PME# supported from%s%s%s%s%s\n",
+                pci_printk(KERN_DEBUG, dev, "PME# supported from%s%s%s%s%s\n",
                          (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
                          (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
                          (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
@@ -2544,13 +2548,13 @@ static int pci_ea_read(struct pci_dev *dev, int offset)
 
         res = pci_ea_get_resource(dev, bei, prop);
         if (!res) {
-                dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei);
+                pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
                 goto out;
         }
 
         flags = pci_ea_flags(dev, prop);
         if (!flags) {
-                dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop);
+                pci_err(dev, "Unsupported EA properties: %#x\n", prop);
                 goto out;
         }
 
@@ -2600,13 +2604,12 @@ static int pci_ea_read(struct pci_dev *dev, int offset)
         }
 
         if (end < start) {
-                dev_err(&dev->dev, "EA Entry crosses address boundary\n");
+                pci_err(dev, "EA Entry crosses address boundary\n");
                 goto out;
         }
 
         if (ent_size != ent_offset - offset) {
-                dev_err(&dev->dev,
-                        "EA Entry Size (%d) does not match length read (%d)\n",
+                pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
                         ent_size, ent_offset - offset);
                 goto out;
         }
@@ -2617,16 +2620,16 @@ static int pci_ea_read(struct pci_dev *dev, int offset)
         res->flags = flags;
 
         if (bei <= PCI_EA_BEI_BAR5)
-                dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
+                pci_printk(KERN_DEBUG, dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
                            bei, res, prop);
         else if (bei == PCI_EA_BEI_ROM)
-                dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
+                pci_printk(KERN_DEBUG, dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
                            res, prop);
         else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
-                dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
+                pci_printk(KERN_DEBUG, dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
                            bei - PCI_EA_BEI_VF_BAR0, res, prop);
         else
-                dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
+                pci_printk(KERN_DEBUG, dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
                            bei, res, prop);
 
 out:
@@ -2723,13 +2726,11 @@ void pci_allocate_cap_save_buffers(struct pci_dev *dev)
         error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
                                         PCI_EXP_SAVE_REGS * sizeof(u16));
         if (error)
-                dev_err(&dev->dev,
-                        "unable to preallocate PCI Express save buffer\n");
+                pci_err(dev, "unable to preallocate PCI Express save buffer\n");
 
         error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
         if (error)
-                dev_err(&dev->dev,
-                        "unable to preallocate PCI-X save buffer\n");
+                pci_err(dev, "unable to preallocate PCI-X save buffer\n");
 
         pci_allocate_vc_save_buffers(dev);
 }
@@ -3066,6 +3067,81 @@ int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
 }
 
 /**
+ * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
+ * @dev: the PCI device
+ * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
+ *      PCI_EXP_DEVCAP2_ATOMIC_COMP32
+ *      PCI_EXP_DEVCAP2_ATOMIC_COMP64
+ *      PCI_EXP_DEVCAP2_ATOMIC_COMP128
+ *
+ * Return 0 if all upstream bridges support AtomicOp routing, egress
+ * blocking is disabled on all upstream ports, and the root port supports
+ * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
+ * AtomicOp completion), or negative otherwise.
+ */
+int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
+{
+        struct pci_bus *bus = dev->bus;
+        struct pci_dev *bridge;
+        u32 cap, ctl2;
+
+        if (!pci_is_pcie(dev))
+                return -EINVAL;
+
+        /*
+         * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
+         * AtomicOp requesters.  For now, we only support endpoints as
+         * requesters and root ports as completers.  No endpoints as
+         * completers, and no peer-to-peer.
+         */
+
+        switch (pci_pcie_type(dev)) {
+        case PCI_EXP_TYPE_ENDPOINT:
+        case PCI_EXP_TYPE_LEG_END:
+        case PCI_EXP_TYPE_RC_END:
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        while (bus->parent) {
+                bridge = bus->self;
+
+                pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
+
+                switch (pci_pcie_type(bridge)) {
+                /* Ensure switch ports support AtomicOp routing */
+                case PCI_EXP_TYPE_UPSTREAM:
+                case PCI_EXP_TYPE_DOWNSTREAM:
+                        if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
+                                return -EINVAL;
+                        break;
+
+                /* Ensure root port supports all the sizes we care about */
+                case PCI_EXP_TYPE_ROOT_PORT:
+                        if ((cap & cap_mask) != cap_mask)
+                                return -EINVAL;
+                        break;
+                }
+
+                /* Ensure upstream ports don't block AtomicOps on egress */
+                if (!bridge->has_secondary_link) {
+                        pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
+                                                   &ctl2);
+                        if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
+                                return -EINVAL;
+                }
+
+                bus = bus->parent;
+        }
+
+        pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
+                                 PCI_EXP_DEVCTL2_ATOMIC_REQ);
+        return 0;
+}
+EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
+
+/**
  * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
  * @dev: the PCI device
  * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
@@ -3198,7 +3274,7 @@ static int __pci_request_region(struct pci_dev *pdev, int bar,
         return 0;
 
 err_out:
-        dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
+        pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
                  &pdev->resource[bar]);
         return -EBUSY;
 }
@@ -3621,7 +3697,7 @@ static void __pci_set_master(struct pci_dev *dev, bool enable)
         else
                 cmd = old_cmd & ~PCI_COMMAND_MASTER;
         if (cmd != old_cmd) {
-                dev_dbg(&dev->dev, "%s bus mastering\n",
+                pci_dbg(dev, "%s bus mastering\n",
                         enable ? "enabling" : "disabling");
                 pci_write_config_word(dev, PCI_COMMAND, cmd);
         }
@@ -3722,7 +3798,7 @@ int pci_set_cacheline_size(struct pci_dev *dev)
         if (cacheline_size == pci_cache_line_size)
                 return 0;
 
-        dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n",
+        pci_printk(KERN_DEBUG, dev, "cache line size of %d is not supported\n",
                    pci_cache_line_size << 2);
 
         return -EINVAL;
@@ -3751,7 +3827,7 @@ int pci_set_mwi(struct pci_dev *dev)
 
         pci_read_config_word(dev, PCI_COMMAND, &cmd);
         if (!(cmd & PCI_COMMAND_INVALIDATE)) {
-                dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
+                pci_dbg(dev, "enabling Mem-Wr-Inval\n");
                 cmd |= PCI_COMMAND_INVALIDATE;
                 pci_write_config_word(dev, PCI_COMMAND, cmd);
         }
@@ -3761,6 +3837,27 @@ int pci_set_mwi(struct pci_dev *dev)
 EXPORT_SYMBOL(pci_set_mwi);
 
 /**
+ * pcim_set_mwi - a device-managed pci_set_mwi()
+ * @dev: the PCI device for which MWI is enabled
+ *
+ * Managed pci_set_mwi().
+ *
+ * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
+ */
+int pcim_set_mwi(struct pci_dev *dev)
+{
+        struct pci_devres *dr;
+
+        dr = find_pci_dr(dev);
+        if (!dr)
+                return -ENOMEM;
+
+        dr->mwi = 1;
+        return pci_set_mwi(dev);
+}
+EXPORT_SYMBOL(pcim_set_mwi);
+
+/**
  * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
  * @dev: the PCI device for which MWI is enabled
  *
@@ -3947,13 +4044,13 @@ static void pci_flr_wait(struct pci_dev *dev)
         pci_read_config_dword(dev, PCI_COMMAND, &id);
         while (id == ~0) {
                 if (delay > timeout) {
-                        dev_warn(&dev->dev, "not ready %dms after FLR; giving up\n",
+                        pci_warn(dev, "not ready %dms after FLR; giving up\n",
                                  100 + delay - 1);
                         return;
                 }
 
                 if (delay > 1000)
-                        dev_info(&dev->dev, "not ready %dms after FLR; waiting\n",
+                        pci_info(dev, "not ready %dms after FLR; waiting\n",
                                  100 + delay - 1);
 
                 msleep(delay);
@@ -3962,7 +4059,7 @@ static void pci_flr_wait(struct pci_dev *dev)
         }
 
         if (delay > 1000)
-                dev_info(&dev->dev, "ready %dms after FLR\n", 100 + delay - 1);
+                pci_info(dev, "ready %dms after FLR\n", 100 + delay - 1);
 }
 
 /**
@@ -3994,7 +4091,7 @@ static bool pcie_has_flr(struct pci_dev *dev)
 void pcie_flr(struct pci_dev *dev)
 {
         if (!pci_wait_for_pending_transaction(dev))
-                dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
+                pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
 
         pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
         pci_flr_wait(dev);
@@ -4027,7 +4124,7 @@ static int pci_af_flr(struct pci_dev *dev, int probe)
          */
         if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
                                  PCI_AF_STATUS_TP << 8))
-                dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
+                pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
 
         pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
         pci_flr_wait(dev);
@@ -5150,12 +5247,12 @@ void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
                 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
                                               sizeof(long), GFP_KERNEL);
         if (!dev->dma_alias_mask) {
-                dev_warn(&dev->dev, "Unable to allocate DMA alias mask\n");
+                pci_warn(dev, "Unable to allocate DMA alias mask\n");
                 return;
         }
 
         set_bit(devfn, dev->dma_alias_mask);
-        dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n",
+        pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
                  PCI_SLOT(devfn), PCI_FUNC(devfn));
 }
 
@@ -5304,7 +5401,7 @@ static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
                 return;
 
         if (r->flags & IORESOURCE_PCI_FIXED) {
-                dev_info(&dev->dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
+                pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
                          bar, r, (unsigned long long)align);
                 return;
         }
@@ -5341,7 +5438,7 @@ static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
          * devices and we use the second.
          */
 
-        dev_info(&dev->dev, "BAR%d %pR: requesting alignment to %#llx\n",
+        pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
                  bar, r, (unsigned long long)align);
 
         if (resize) {
@@ -5387,13 +5484,11 @@ void pci_reassigndev_resource_alignment(struct pci_dev *dev)
 
         if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
             (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
-                dev_warn(&dev->dev,
-                        "Can't reassign resources to host bridge.\n");
+                pci_warn(dev, "Can't reassign resources to host bridge\n");
                 return;
         }
 
-        dev_info(&dev->dev,
-                "Disabling memory decoding and releasing memory resources.\n");
+        pci_info(dev, "Disabling memory decoding and releasing memory resources\n");
         pci_read_config_word(dev, PCI_COMMAND, &command);
         command &= ~PCI_COMMAND_MEMORY;
         pci_write_config_word(dev, PCI_COMMAND, command);
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index f6b58b32a67c..fcd81911b127 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -38,21 +38,21 @@ int pci_probe_reset_function(struct pci_dev *dev);
  * struct pci_platform_pm_ops - Firmware PM callbacks
  *
  * @is_manageable: returns 'true' if given device is power manageable by the
- *                 platform firmware
+ *                 platform firmware
  *
  * @set_state: invokes the platform firmware to set the device's power state
  *
  * @get_state: queries the platform firmware for a device's current power state
  *
  * @choose_state: returns PCI power state of given device preferred by the
- *                platform; to be used during system-wide transitions from a
- *                sleeping state to the working state and vice versa
+ *                platform; to be used during system-wide transitions from a
+ *                sleeping state to the working state and vice versa
  *
  * @set_wakeup: enables/disables wakeup capability for the device
  *
  * @need_resume: returns 'true' if the given device (which is currently
- *              suspended) needs to be resumed to be configured for system
- *              wakeup.
+ *               suspended) needs to be resumed to be configured for system
+ *               wakeup.
  *
  * If given platform is generally capable of power managing PCI devices, all of
  * these callbacks are mandatory.
@@ -112,7 +112,7 @@ struct pci_vpd_ops {
 
 struct pci_vpd {
         const struct pci_vpd_ops *ops;
-        struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
+        struct bin_attribute *attr;     /* Descriptor for sysfs VPD entry */
         struct mutex    lock;
         unsigned int    len;
         u16             flag;
@@ -199,7 +199,7 @@ extern const struct attribute_group *pci_bus_groups[];
 
 /**
  * pci_match_one_device - Tell if a PCI device structure has a matching
- *                        PCI device id structure
+ *                        PCI device id structure
  * @id: single PCI device id structure to match
  * @dev: the PCI device structure to match against
  *
@@ -231,7 +231,7 @@ struct pci_slot_attribute {
 
 enum pci_bar_type {
         pci_bar_unknown,        /* Standard PCI BAR probe */
-        pci_bar_io,             /* An io port BAR */
+        pci_bar_io,             /* An I/O port BAR */
         pci_bar_mem32,          /* A 32-bit memory BAR */
         pci_bar_mem64,          /* A 64-bit memory BAR */
 };
@@ -255,24 +255,24 @@ void pci_disable_bridge_window(struct pci_dev *dev);
 
 /* Single Root I/O Virtualization */
 struct pci_sriov {
-        int pos;                /* capability position */
-        int nres;               /* number of resources */
-        u32 cap;                /* SR-IOV Capabilities */
-        u16 ctrl;               /* SR-IOV Control */
-        u16 total_VFs;          /* total VFs associated with the PF */
-        u16 initial_VFs;        /* initial VFs associated with the PF */
-        u16 num_VFs;            /* number of VFs available */
-        u16 offset;             /* first VF Routing ID offset */
-        u16 stride;             /* following VF stride */
-        u16 vf_device;          /* VF device ID */
-        u32 pgsz;               /* page size for BAR alignment */
-        u8 link;                /* Function Dependency Link */
-        u8 max_VF_buses;        /* max buses consumed by VFs */
-        u16 driver_max_VFs;     /* max num VFs driver supports */
-        struct pci_dev *dev;    /* lowest numbered PF */
-        struct pci_dev *self;   /* this PF */
-        resource_size_t barsz[PCI_SRIOV_NUM_BARS];      /* VF BAR size */
-        bool drivers_autoprobe; /* auto probing of VFs by driver */
+        int             pos;            /* Capability position */
+        int             nres;           /* Number of resources */
+        u32             cap;            /* SR-IOV Capabilities */
+        u16             ctrl;           /* SR-IOV Control */
+        u16             total_VFs;      /* Total VFs associated with the PF */
+        u16             initial_VFs;    /* Initial VFs associated with the PF */
+        u16             num_VFs;        /* Number of VFs available */
+        u16             offset;         /* First VF Routing ID offset */
+        u16             stride;         /* Following VF stride */
+        u16             vf_device;      /* VF device ID */
+        u32             pgsz;           /* Page size for BAR alignment */
+        u8              link;           /* Function Dependency Link */
+        u8              max_VF_buses;   /* Max buses consumed by VFs */
+        u16             driver_max_VFs; /* Max num VFs driver supports */
+        struct pci_dev  *dev;           /* Lowest numbered PF */
+        struct pci_dev  *self;          /* This PF */
+        resource_size_t barsz[PCI_SRIOV_NUM_BARS];      /* VF BAR size */
+        bool            drivers_autoprobe; /* Auto probing of VFs by driver */
 };
 
 /* pci_dev priv_flags */
@@ -335,13 +335,33 @@ static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
         if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
                 return pci_sriov_resource_alignment(dev, resno);
 #endif
-        if (dev->class >> 8  == PCI_CLASS_BRIDGE_CARDBUS)
+        if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
                 return pci_cardbus_resource_alignment(res);
         return resource_alignment(res);
 }
 
 void pci_enable_acs(struct pci_dev *dev);
 
+#ifdef CONFIG_PCIEASPM
+void pcie_aspm_init_link_state(struct pci_dev *pdev);
+void pcie_aspm_exit_link_state(struct pci_dev *pdev);
+void pcie_aspm_pm_state_change(struct pci_dev *pdev);
+void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
+#else
+static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
+static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
+static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
+static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
+#endif
+
+#ifdef CONFIG_PCIEASPM_DEBUG
+void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
+void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
+#else
+static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { }
+static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { }
+#endif
+
 #ifdef CONFIG_PCIE_PTM
 void pci_ptm_init(struct pci_dev *dev);
 #else
diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig
index ac53edbc9613..b12e28b3d8f9 100644
--- a/drivers/pci/pcie/Kconfig
+++ b/drivers/pci/pcie/Kconfig
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
 #
 # PCI Express Port Bus Configuration
 #
@@ -92,7 +93,7 @@ config PCIE_PME
 
 config PCIE_DPC
         bool "PCIe Downstream Port Containment support"
-        depends on PCIEPORTBUS
+        depends on PCIEPORTBUS && PCIEAER
         default n
         help
           This enables PCI Express Downstream Port Containment (DPC)
diff --git a/drivers/pci/pcie/aer/Kconfig b/drivers/pci/pcie/aer/Kconfig
index 7d1437b01fdd..5a64eb3d6c7a 100644
--- a/drivers/pci/pcie/aer/Kconfig
+++ b/drivers/pci/pcie/aer/Kconfig
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
 #
 # PCI Express Root Port Device AER Configuration
 #
diff --git a/drivers/pci/pcie/aer/Kconfig.debug b/drivers/pci/pcie/aer/Kconfig.debug
index 9142949734f5..67e02174b65b 100644
--- a/drivers/pci/pcie/aer/Kconfig.debug
+++ b/drivers/pci/pcie/aer/Kconfig.debug
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
 #
 # PCI Express Root Port Device AER Debug Configuration
 #
diff --git a/drivers/pci/pcie/aer/aer_inject.c b/drivers/pci/pcie/aer/aer_inject.c
index 2b6a59266689..25e1feb962c5 100644
--- a/drivers/pci/pcie/aer/aer_inject.c
+++ b/drivers/pci/pcie/aer/aer_inject.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * PCIe AER software error injection support.
  *
@@ -9,12 +10,6 @@
  *
  * Copyright 2009 Intel Corporation.
  *     Huang Ying <ying.huang@intel.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; version 2
- * of the License.
- *
  */
 
 #include <linux/module.h>
@@ -344,14 +339,14 @@ static int aer_inject(struct aer_error_inj *einj)
                 return -ENODEV;
         rpdev = pcie_find_root_port(dev);
         if (!rpdev) {
-                dev_err(&dev->dev, "aer_inject: Root port not found\n");
+                pci_err(dev, "aer_inject: Root port not found\n");
                 ret = -ENODEV;
                 goto out_put;
         }
 
         pos_cap_err = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
         if (!pos_cap_err) {
-                dev_err(&dev->dev, "aer_inject: Device doesn't support AER\n");
+                pci_err(dev, "aer_inject: Device doesn't support AER\n");
                 ret = -EPROTONOSUPPORT;
                 goto out_put;
         }
@@ -362,8 +357,7 @@ static int aer_inject(struct aer_error_inj *einj)
 
         rp_pos_cap_err = pci_find_ext_capability(rpdev, PCI_EXT_CAP_ID_ERR);
         if (!rp_pos_cap_err) {
-                dev_err(&rpdev->dev,
-                        "aer_inject: Root port doesn't support AER\n");
+                pci_err(rpdev, "aer_inject: Root port doesn't support AER\n");
                 ret = -EPROTONOSUPPORT;
                 goto out_put;
         }
@@ -411,16 +405,14 @@ static int aer_inject(struct aer_error_inj *einj)
         if (!aer_mask_override && einj->cor_status &&
             !(einj->cor_status & ~cor_mask)) {
                 ret = -EINVAL;
-                dev_warn(&dev->dev,
-                         "aer_inject: The correctable error(s) is masked by device\n");
+                pci_warn(dev, "aer_inject: The correctable error(s) is masked by device\n");
                 spin_unlock_irqrestore(&inject_lock, flags);
                 goto out_put;
         }
         if (!aer_mask_override && einj->uncor_status &&
             !(einj->uncor_status & ~uncor_mask)) {
                 ret = -EINVAL;
-                dev_warn(&dev->dev,
-                         "aer_inject: The uncorrectable error(s) is masked by device\n");
+                pci_warn(dev, "aer_inject: The uncorrectable error(s) is masked by device\n");
                 spin_unlock_irqrestore(&inject_lock, flags);
                 goto out_put;
         }
@@ -483,7 +475,7 @@ static int aer_inject(struct aer_error_inj *einj)
                          einj->cor_status, einj->uncor_status, pci_name(dev));
                 aer_irq(-1, edev);
         } else {
-                dev_err(&rpdev->dev, "aer_inject: AER device not found\n");
+                pci_err(rpdev, "aer_inject: AER device not found\n");
                 ret = -ENODEV;
         }
 out_put:
diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c
index 6ff5f5b4f5e6..da8331f5684d 100644
--- a/drivers/pci/pcie/aer/aerdrv.c
+++ b/drivers/pci/pcie/aer/aerdrv.c
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * drivers/pci/pcie/aer/aerdrv.c
  *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * This file implements the AER root port service driver. The driver will
  * register an irq handler. When root port triggers an AER interrupt, the irq
  * handler will collect root port status and schedule a work.
@@ -326,7 +323,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
         pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32);
 
         pci_reset_bridge_secondary_bus(dev);
-        dev_printk(KERN_DEBUG, &dev->dev, "Root Port link has been reset\n");
+        pci_printk(KERN_DEBUG, dev, "Root Port link has been reset\n");
 
         /* Clear Root Error Status */
         pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &reg32);
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c
index 744805232155..a4bfea52e7d4 100644
--- a/drivers/pci/pcie/aer/aerdrv_core.c
+++ b/drivers/pci/pcie/aer/aerdrv_core.c
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * drivers/pci/pcie/aer/aerdrv_core.c
  *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * This file implements the core part of PCIe AER. When a PCIe
  * error is delivered, an error message will be collected and printed to
  * console, then, an error recovery procedure will be executed by following
@@ -226,9 +223,8 @@ static bool find_source_device(struct pci_dev *parent,
         pci_walk_bus(parent->subordinate, find_device_iter, e_info);
 
         if (!e_info->error_dev_num) {
-                dev_printk(KERN_DEBUG, &parent->dev,
-                                "can't find device of ID%04x\n",
-                                e_info->id);
+                pci_printk(KERN_DEBUG, parent, "can't find device of ID%04x\n",
+                           e_info->id);
                 return false;
         }
         return true;
@@ -256,7 +252,7 @@ static int report_error_detected(struct pci_dev *dev, void *data)
                          * of a driver for this device is unaware of
                          * its hw state.
                          */
-                        dev_printk(KERN_DEBUG, &dev->dev, "device has %s\n",
+                        pci_printk(KERN_DEBUG, dev, "device has %s\n",
                                    dev->driver ?
                                    "no AER-aware driver" : "no driver");
                 }
@@ -278,6 +274,7 @@ static int report_error_detected(struct pci_dev *dev, void *data)
         } else {
                 err_handler = dev->driver->err_handler;
                 vote = err_handler->error_detected(dev, result_data->state);
+                pci_uevent_ers(dev, PCI_ERS_RESULT_NONE);
         }
 
         result_data->result = merge_result(result_data->result, vote);
@@ -341,6 +338,7 @@ static int report_resume(struct pci_dev *dev, void *data)
 
         err_handler = dev->driver->err_handler;
         err_handler->resume(dev);
+        pci_uevent_ers(dev, PCI_ERS_RESULT_RECOVERED);
 out:
         device_unlock(&dev->dev);
         return 0;
@@ -364,7 +362,7 @@ static pci_ers_result_t broadcast_error_message(struct pci_dev *dev,
 {
         struct aer_broadcast_data result_data;
 
-        dev_printk(KERN_DEBUG, &dev->dev, "broadcast %s message\n", error_mesg);
+        pci_printk(KERN_DEBUG, dev, "broadcast %s message\n", error_mesg);
         result_data.state = state;
         if (cb == report_error_detected)
                 result_data.result = PCI_ERS_RESULT_CAN_RECOVER;
@@ -413,7 +411,7 @@ static pci_ers_result_t broadcast_error_message(struct pci_dev *dev,
 static pci_ers_result_t default_reset_link(struct pci_dev *dev)
 {
         pci_reset_bridge_secondary_bus(dev);
-        dev_printk(KERN_DEBUG, &dev->dev, "downstream link has been reset\n");
+        pci_printk(KERN_DEBUG, dev, "downstream link has been reset\n");
         return PCI_ERS_RESULT_RECOVERED;
 }
 
@@ -465,15 +463,13 @@ static pci_ers_result_t reset_link(struct pci_dev *dev)
         } else if (udev->has_secondary_link) {
                 status = default_reset_link(udev);
         } else {
-                dev_printk(KERN_DEBUG, &dev->dev,
-                        "no link-reset support at upstream device %s\n",
+                pci_printk(KERN_DEBUG, dev, "no link-reset support at upstream device %s\n",
                         pci_name(udev));
                 return PCI_ERS_RESULT_DISCONNECT;
         }
 
         if (status != PCI_ERS_RESULT_RECOVERED) {
-                dev_printk(KERN_DEBUG, &dev->dev,
-                        "link reset at upstream device %s failed\n",
+                pci_printk(KERN_DEBUG, dev, "link reset at upstream device %s failed\n",
                         pci_name(udev));
                 return PCI_ERS_RESULT_DISCONNECT;
         }
@@ -537,12 +533,13 @@ static void do_recovery(struct pci_dev *dev, int severity)
                                 "resume",
                                 report_resume);
 
-        dev_info(&dev->dev, "AER: Device recovery successful\n");
+        pci_info(dev, "AER: Device recovery successful\n");
         return;
 
 failed:
+        pci_uevent_ers(dev, PCI_ERS_RESULT_DISCONNECT);
         /* TODO: Should kernel panic here? */
-        dev_info(&dev->dev, "AER: Device recovery failed\n");
+        pci_info(dev, "AER: Device recovery failed\n");
 }
 
 /**
@@ -633,7 +630,8 @@ static void aer_recover_work_func(struct work_struct *work)
                         continue;
                 }
                 cper_print_aer(pdev, entry.severity, entry.regs);
-                do_recovery(pdev, entry.severity);
+                if (entry.severity != AER_CORRECTABLE)
+                        do_recovery(pdev, entry.severity);
                 pci_dev_put(pdev);
         }
 }
@@ -660,7 +658,7 @@ static int get_device_error_info(struct pci_dev *dev, struct aer_err_info *info)
 
         /* The device might not support AER */
         if (!pos)
-                return 1;
+                return 0;
 
         if (info->severity == AER_CORRECTABLE) {
                 pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS,
diff --git a/drivers/pci/pcie/aer/aerdrv_errprint.c b/drivers/pci/pcie/aer/aerdrv_errprint.c
index 54c4b691e51f..6a352e638699 100644
--- a/drivers/pci/pcie/aer/aerdrv_errprint.c
+++ b/drivers/pci/pcie/aer/aerdrv_errprint.c
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * drivers/pci/pcie/aer/aerdrv_errprint.c
  *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
  * Format error messages and print them to console.
  *
  * Copyright (C) 2006 Intel Corp.
@@ -132,7 +129,7 @@ static const char *aer_agent_string[] = {
 static void __print_tlp_header(struct pci_dev *dev,
                                struct aer_header_log_regs *t)
 {
-        dev_err(&dev->dev, "  TLP Header: %08x %08x %08x %08x\n",
+        pci_err(dev, "  TLP Header: %08x %08x %08x %08x\n",
                 t->dw0, t->dw1, t->dw2, t->dw3);
 }
 
@@ -155,10 +152,10 @@ static void __aer_print_error(struct pci_dev *dev,
                                 aer_uncorrectable_error_string[i] : NULL;
 
                 if (errmsg)
-                        dev_err(&dev->dev, "   [%2d] %-22s%s\n", i, errmsg,
+                        pci_err(dev, "   [%2d] %-22s%s\n", i, errmsg,
                                 info->first_error == i ? " (First)" : "");
                 else
-                        dev_err(&dev->dev, "   [%2d] Unknown Error Bit%s\n",
+                        pci_err(dev, "   [%2d] Unknown Error Bit%s\n",
                                 i, info->first_error == i ? " (First)" : "");
         }
 }
@@ -169,7 +166,7 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
         int id = ((dev->bus->number << 8) | dev->devfn);
 
         if (!info->status) {
-                dev_err(&dev->dev, "PCIe Bus Error: severity=%s, type=Unaccessible, id=%04x(Unregistered Agent ID)\n",
+                pci_err(dev, "PCIe Bus Error: severity=%s, type=Unaccessible, id=%04x(Unregistered Agent ID)\n",
                         aer_error_severity_string[info->severity], id);
                 goto out;
         }
@@ -177,11 +174,11 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
         layer = AER_GET_LAYER_ERROR(info->severity, info->status);
         agent = AER_GET_AGENT(info->severity, info->status);
 
-        dev_err(&dev->dev, "PCIe Bus Error: severity=%s, type=%s, id=%04x(%s)\n",
+        pci_err(dev, "PCIe Bus Error: severity=%s, type=%s, id=%04x(%s)\n",
                 aer_error_severity_string[info->severity],
                 aer_error_layer[layer], id, aer_agent_string[agent]);
 
-        dev_err(&dev->dev, "  device [%04x:%04x] error status/mask=%08x/%08x\n",
+        pci_err(dev, "  device [%04x:%04x] error status/mask=%08x/%08x\n",
                 dev->vendor, dev->device,
                 info->status, info->mask);
 
@@ -192,7 +189,7 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
 
 out:
         if (info->id && info->error_dev_num > 1 && info->id == id)
-                dev_err(&dev->dev, "  Error of this Agent(%04x) is reported first\n", id);
+                pci_err(dev, "  Error of this Agent(%04x) is reported first\n", id);
 
         trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask),
                         info->severity);
@@ -200,7 +197,7 @@ out:
 
 void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info)
 {
-        dev_info(&dev->dev, "AER: %s%s error received: id=%04x\n",
+        pci_info(dev, "AER: %s%s error received: id=%04x\n",
                 info->multi_error_valid ? "Multiple " : "",
                 aer_error_severity_string[info->severity], info->id);
 }
@@ -242,13 +239,13 @@ void cper_print_aer(struct pci_dev *dev, int aer_severity,
         layer = AER_GET_LAYER_ERROR(aer_severity, status);
         agent = AER_GET_AGENT(aer_severity, status);
 
-        dev_err(&dev->dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask);
+        pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask);
         cper_print_bits("", status, status_strs, status_strs_size);
-        dev_err(&dev->dev, "aer_layer=%s, aer_agent=%s\n",
+        pci_err(dev, "aer_layer=%s, aer_agent=%s\n",
                 aer_error_layer[layer], aer_agent_string[agent]);
 
         if (aer_severity != AER_CORRECTABLE)
-                dev_err(&dev->dev, "aer_uncor_severity: 0x%08x\n",
+                pci_err(dev, "aer_uncor_severity: 0x%08x\n",
                         aer->uncor_severity);
 
         if (tlp_header_valid)
diff --git a/drivers/pci/pcie/aer/ecrc.c b/drivers/pci/pcie/aer/ecrc.c
index a2747a663bc9..26d3cac9e635 100644
--- a/drivers/pci/pcie/aer/ecrc.c
+++ b/drivers/pci/pcie/aer/ecrc.c
@@ -1,23 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  *    Enables/disables PCIe ECRC checking.
  *
  *    (C) Copyright 2009 Hewlett-Packard Development Company, L.P.
  *    Andrew Patterson <andrew.patterson@hp.com>
- *
- *    This program is free software; you can redistribute it and/or modify
- *    it under the terms of the GNU General Public License as published by
- *    the Free Software Foundation; version 2 of the License.
- *
- *    This program is distributed in the hope that it will be useful,
- *    but WITHOUT ANY WARRANTY; without even the implied warranty of
- *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- *    General Public License for more details.
- *
- *    You should have received a copy of the GNU General Public License
- *    along with this program; if not, write to the Free Software
- *    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- *    02111-1307, USA.
- *
  */
 
 #include <linux/kernel.h>
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 9783e10da3a9..57feef2ecfe7 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -43,18 +43,6 @@
 #define ASPM_STATE_ALL          (ASPM_STATE_L0S | ASPM_STATE_L1 |       \
                                  ASPM_STATE_L1SS)
 
-/*
- * When L1 substates are enabled, the LTR L1.2 threshold is a timing parameter
- * that decides whether L1.1 or L1.2 is entered (Refer PCIe spec for details).
- * Not sure is there is a way to "calculate" this on the fly, but maybe we
- * could turn it into a parameter in future.  This value has been taken from
- * the following files from Intel's coreboot (which is the only code I found
- * to have used this):
- * https://www.coreboot.org/pipermail/coreboot-gerrit/2015-March/021134.html
- * https://review.coreboot.org/#/c/8832/
- */
-#define LTR_L1_2_THRESHOLD_BITS ((1 << 21) | (1 << 23) | (1 << 30))
-
 struct aspm_latency {
         u32 l0s;                        /* L0s latency (nsec) */
         u32 l1;                         /* L1 latency (nsec) */
@@ -278,7 +266,7 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
                 return;
 
         /* Training failed. Restore common clock configurations */
-        dev_err(&parent->dev, "ASPM: Could not configure common clock\n");
+        pci_err(parent, "ASPM: Could not configure common clock\n");
         list_for_each_entry(child, &linkbus->devices, bus_list)
                 pcie_capability_write_word(child, PCI_EXP_LNKCTL,
                                            child_reg[PCI_FUNC(child->devfn)]);
@@ -328,11 +316,36 @@ static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
         case 2:
                 return val * 100;
         }
-        dev_err(&pdev->dev, "%s: Invalid T_PwrOn scale: %u\n",
-                __func__, scale);
+        pci_err(pdev, "%s: Invalid T_PwrOn scale: %u\n", __func__, scale);
         return 0;
 }
 
+static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
+{
+        u64 threshold_ns = threshold_us * 1000;
+
+        /* See PCIe r3.1, sec 7.33.3 and sec 6.18 */
+        if (threshold_ns < 32) {
+                *scale = 0;
+                *value = threshold_ns;
+        } else if (threshold_ns < 1024) {
+                *scale = 1;
+                *value = threshold_ns >> 5;
+        } else if (threshold_ns < 32768) {
+                *scale = 2;
+                *value = threshold_ns >> 10;
+        } else if (threshold_ns < 1048576) {
+                *scale = 3;
+                *value = threshold_ns >> 15;
+        } else if (threshold_ns < 33554432) {
+                *scale = 4;
+                *value = threshold_ns >> 20;
+        } else {
+                *scale = 5;
+                *value = threshold_ns >> 25;
+        }
+}
+
 struct aspm_register_info {
         u32 support:2;
         u32 enabled:2;
@@ -443,6 +456,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
                                 struct aspm_register_info *dwreg)
 {
         u32 val1, val2, scale1, scale2;
+        u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
 
         link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr;
         link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr;
@@ -454,16 +468,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
         /* Choose the greater of the two Port Common_Mode_Restore_Times */
         val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
         val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
-        if (val1 > val2)
-                link->l1ss.ctl1 |= val1 << 8;
-        else
-                link->l1ss.ctl1 |= val2 << 8;
-
-        /*
-         * We currently use LTR L1.2 threshold to be fixed constant picked from
-         * Intel's coreboot.
-         */
-        link->l1ss.ctl1 |= LTR_L1_2_THRESHOLD_BITS;
+        t_common_mode = max(val1, val2);
 
         /* Choose the greater of the two Port T_POWER_ON times */
         val1   = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
@@ -472,10 +477,27 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
         scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
 
         if (calc_l1ss_pwron(link->pdev, scale1, val1) >
-            calc_l1ss_pwron(link->downstream, scale2, val2))
+            calc_l1ss_pwron(link->downstream, scale2, val2)) {
                 link->l1ss.ctl2 |= scale1 | (val1 << 3);
-        else
+                t_power_on = calc_l1ss_pwron(link->pdev, scale1, val1);
+        } else {
                 link->l1ss.ctl2 |= scale2 | (val2 << 3);
+                t_power_on = calc_l1ss_pwron(link->downstream, scale2, val2);
+        }
+
+        /*
+         * Set LTR_L1.2_THRESHOLD to the time required to transition the
+         * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
+         * downstream devices report (via LTR) that they can tolerate at
+         * least that much latency.
+         *
+         * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
+         * Table 5-11.  T(POWER_OFF) is at most 2us and T(L1.2) is at
+         * least 4us.
+         */
+        l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
+        encode_l12_threshold(l1_2_threshold, &scale, &value);
+        link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
 }
 
 static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
@@ -786,7 +808,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
                  */
                 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
                 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
-                        dev_info(&child->dev, "disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'\n");
+                        pci_info(child, "disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'\n");
                         return -EINVAL;
                 }
         }
@@ -1027,7 +1049,7 @@ static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
          * ignored in this situation.
          */
         if (aspm_disabled) {
-                dev_warn(&pdev->dev, "can't disable ASPM; OS doesn't have ASPM control\n");
+                pci_warn(pdev, "can't disable ASPM; OS doesn't have ASPM control\n");
                 return;
         }
 
diff --git a/drivers/pci/pcie/pcie-dpc.c b/drivers/pci/pcie/pcie-dpc.c
index 2d976a623ddc..38e40c6c576f 100644
--- a/drivers/pci/pcie/pcie-dpc.c
+++ b/drivers/pci/pcie/pcie-dpc.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * PCI Express Downstream Port Containment services driver
  * Author: Keith Busch <keith.busch@intel.com>
  *
  * Copyright (C) 2016 Intel Corp.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
  */
 
 #include <linux/delay.h>
@@ -15,34 +12,15 @@
 #include <linux/pci.h>
 #include <linux/pcieport_if.h>
 #include "../pci.h"
-
-struct rp_pio_header_log_regs {
-        u32 dw0;
-        u32 dw1;
-        u32 dw2;
-        u32 dw3;
-};
-
-struct dpc_rp_pio_regs {
-        u32 status;
-        u32 mask;
-        u32 severity;
-        u32 syserror;
-        u32 exception;
-
-        struct rp_pio_header_log_regs header_log;
-        u32 impspec_log;
-        u32 tlp_prefix_log[4];
-        u32 log_size;
-        u16 first_error;
-};
+#include "aer/aerdrv.h"
 
 struct dpc_dev {
         struct pcie_device      *dev;
         struct work_struct      work;
-        int                     cap_pos;
-        bool                    rp;
+        u16                     cap_pos;
+        bool                    rp_extensions;
         u32                     rp_pio_status;
+        u8                      rp_log_size;
 };
 
 static const char * const rp_pio_error_string[] = {
@@ -72,13 +50,13 @@ static int dpc_wait_rp_inactive(struct dpc_dev *dpc)
         unsigned long timeout = jiffies + HZ;
         struct pci_dev *pdev = dpc->dev->port;
         struct device *dev = &dpc->dev->device;
-        u16 status;
+        u16 cap = dpc->cap_pos, status;
 
-        pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
+        pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
         while (status & PCI_EXP_DPC_RP_BUSY &&
                                         !time_after(jiffies, timeout)) {
                 msleep(10);
-                pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
+                pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
         }
         if (status & PCI_EXP_DPC_RP_BUSY) {
                 dev_warn(dev, "DPC root port still busy\n");
@@ -104,11 +82,12 @@ static void dpc_wait_link_inactive(struct dpc_dev *dpc)
                 dev_warn(dev, "Link state not disabled for DPC event\n");
 }
 
-static void interrupt_event_handler(struct work_struct *work)
+static void dpc_work(struct work_struct *work)
 {
         struct dpc_dev *dpc = container_of(work, struct dpc_dev, work);
         struct pci_dev *dev, *temp, *pdev = dpc->dev->port;
         struct pci_bus *parent = pdev->subordinate;
+        u16 cap = dpc->cap_pos, ctl;
 
         pci_lock_rescan_remove();
         list_for_each_entry_safe_reverse(dev, temp, &parent->devices,
@@ -124,159 +103,127 @@ static void interrupt_event_handler(struct work_struct *work)
         pci_unlock_rescan_remove();
 
         dpc_wait_link_inactive(dpc);
-        if (dpc->rp && dpc_wait_rp_inactive(dpc))
+        if (dpc->rp_extensions && dpc_wait_rp_inactive(dpc))
                 return;
-        if (dpc->rp && dpc->rp_pio_status) {
-                pci_write_config_dword(pdev,
-                                      dpc->cap_pos + PCI_EXP_DPC_RP_PIO_STATUS,
-                                      dpc->rp_pio_status);
+        if (dpc->rp_extensions && dpc->rp_pio_status) {
+                pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS,
+                                       dpc->rp_pio_status);
                 dpc->rp_pio_status = 0;
         }
 
-        pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS,
+        pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
                 PCI_EXP_DPC_STATUS_TRIGGER | PCI_EXP_DPC_STATUS_INTERRUPT);
-}
 
-static void dpc_rp_pio_print_tlp_header(struct device *dev,
-                                        struct rp_pio_header_log_regs *t)
-{
-        dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n",
-                t->dw0, t->dw1, t->dw2, t->dw3);
+        pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl);
+        pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL,
+                              ctl | PCI_EXP_DPC_CTL_INT_EN);
 }
 
-static void dpc_rp_pio_print_error(struct dpc_dev *dpc,
-                                   struct dpc_rp_pio_regs *rp_pio)
+static void dpc_process_rp_pio_error(struct dpc_dev *dpc)
 {
         struct device *dev = &dpc->dev->device;
+        struct pci_dev *pdev = dpc->dev->port;
+        u16 cap = dpc->cap_pos, dpc_status, first_error;
+        u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix;
         int i;
-        u32 status;
 
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
         dev_err(dev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
-                rp_pio->status, rp_pio->mask);
+                status, mask);
 
+        dpc->rp_pio_status = status;
+
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
         dev_err(dev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
-                rp_pio->severity, rp_pio->syserror, rp_pio->exception);
+                sev, syserr, exc);
 
-        status = (rp_pio->status & ~rp_pio->mask);
+        /* Get First Error Pointer */
+        pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
+        first_error = (dpc_status & 0x1f00) >> 8;
 
+        status &= ~mask;
         for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
-                if (!(status & (1 << i)))
-                        continue;
-
-                dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
-                        rp_pio->first_error == i ? " (First)" : "");
+                if (status & (1 << i))
+                        dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
+                                first_error == i ? " (First)" : "");
         }
 
-        dpc_rp_pio_print_tlp_header(dev, &rp_pio->header_log);
-        if (rp_pio->log_size == 4)
+        if (dpc->rp_log_size < 4)
                 return;
-        dev_err(dev, "RP PIO ImpSpec Log %#010x\n", rp_pio->impspec_log);
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
+                              &dw0);
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
+                              &dw1);
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
+                              &dw2);
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
+                              &dw3);
+        dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n",
+                dw0, dw1, dw2, dw3);
+
+        if (dpc->rp_log_size < 5)
+                return;
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
+        dev_err(dev, "RP PIO ImpSpec Log %#010x\n", log);
 
-        for (i = 0; i < rp_pio->log_size - 5; i++)
-                dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i,
-                        rp_pio->tlp_prefix_log[i]);
+        for (i = 0; i < dpc->rp_log_size - 5; i++) {
+                pci_read_config_dword(pdev,
+                        cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix);
+                dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);
+        }
 }
 
-static void dpc_rp_pio_get_info(struct dpc_dev *dpc,
-                                struct dpc_rp_pio_regs *rp_pio)
+static irqreturn_t dpc_irq(int irq, void *context)
 {
+        struct dpc_dev *dpc = (struct dpc_dev *)context;
         struct pci_dev *pdev = dpc->dev->port;
         struct device *dev = &dpc->dev->device;
-        int i;
-        u16 cap;
-        u16 status;
-
-        pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_STATUS,
-                              &rp_pio->status);
-        pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_MASK,
-                              &rp_pio->mask);
-
-        pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_SEVERITY,
-                              &rp_pio->severity);
-        pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_SYSERROR,
-                              &rp_pio->syserror);
-        pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_EXCEPTION,
-                              &rp_pio->exception);
-
-        /* Get First Error Pointer */
-        pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
-        rp_pio->first_error = (status & 0x1f00) >> 8;
+        u16 cap = dpc->cap_pos, ctl, status, source, reason, ext_reason;
 
-        pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap);
-        rp_pio->log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
-        if (rp_pio->log_size < 4 || rp_pio->log_size > 9) {
-                dev_err(dev, "RP PIO log size %u is invalid\n",
-                        rp_pio->log_size);
-                return;
-        }
+        pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl);
 
-        pci_read_config_dword(pdev,
-                              dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
-                              &rp_pio->header_log.dw0);
-        pci_read_config_dword(pdev,
-                              dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
-                              &rp_pio->header_log.dw1);
-        pci_read_config_dword(pdev,
-                              dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
-                              &rp_pio->header_log.dw2);
-        pci_read_config_dword(pdev,
-                              dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
-                              &rp_pio->header_log.dw3);
-        if (rp_pio->log_size == 4)
-                return;
+        if (!(ctl & PCI_EXP_DPC_CTL_INT_EN) || ctl == (u16)(~0))
+                return IRQ_NONE;
 
-        pci_read_config_dword(pdev,
-                              dpc->cap_pos + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG,
-                              &rp_pio->impspec_log);
-        for (i = 0; i < rp_pio->log_size - 5; i++)
-                pci_read_config_dword(pdev,
-                        dpc->cap_pos + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG,
-                        &rp_pio->tlp_prefix_log[i]);
-}
+        pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
 
-static void dpc_process_rp_pio_error(struct dpc_dev *dpc)
-{
-        struct dpc_rp_pio_regs rp_pio_regs;
+        if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT))
+                return IRQ_NONE;
 
-        dpc_rp_pio_get_info(dpc, &rp_pio_regs);
-        dpc_rp_pio_print_error(dpc, &rp_pio_regs);
+        if (!(status & PCI_EXP_DPC_STATUS_TRIGGER)) {
+                pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
+                                      PCI_EXP_DPC_STATUS_INTERRUPT);
+                return IRQ_HANDLED;
+        }
 
-        dpc->rp_pio_status = rp_pio_regs.status;
-}
+        pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL,
+                              ctl & ~PCI_EXP_DPC_CTL_INT_EN);
 
-static irqreturn_t dpc_irq(int irq, void *context)
-{
-        struct dpc_dev *dpc = (struct dpc_dev *)context;
-        struct pci_dev *pdev = dpc->dev->port;
-        struct device *dev = &dpc->dev->device;
-        u16 status, source;
-
-        pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
-        pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_SOURCE_ID,
+        pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID,
                              &source);
-        if (!status || status == (u16)(~0))
-                return IRQ_NONE;
 
         dev_info(dev, "DPC containment event, status:%#06x source:%#06x\n",
                 status, source);
 
-        if (status & PCI_EXP_DPC_STATUS_TRIGGER) {
-                u16 reason = (status >> 1) & 0x3;
-                u16 ext_reason = (status >> 5) & 0x3;
-
-                dev_warn(dev, "DPC %s detected, remove downstream devices\n",
-                         (reason == 0) ? "unmasked uncorrectable error" :
-                         (reason == 1) ? "ERR_NONFATAL" :
-                         (reason == 2) ? "ERR_FATAL" :
-                         (ext_reason == 0) ? "RP PIO error" :
-                         (ext_reason == 1) ? "software trigger" :
-                                             "reserved error");
-                /* show RP PIO error detail information */
-                if (reason == 3 && ext_reason == 0)
-                        dpc_process_rp_pio_error(dpc);
-
-                schedule_work(&dpc->work);
-        }
+        reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1;
+        ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5;
+
+        dev_warn(dev, "DPC %s detected, remove downstream devices\n",
+                 (reason == 0) ? "unmasked uncorrectable error" :
+                 (reason == 1) ? "ERR_NONFATAL" :
+                 (reason == 2) ? "ERR_FATAL" :
+                 (ext_reason == 0) ? "RP PIO error" :
+                 (ext_reason == 1) ? "software trigger" :
+                                     "reserved error");
+        /* show RP PIO error detail information */
+        if (dpc->rp_extensions && reason == 3 && ext_reason == 0)
+                dpc_process_rp_pio_error(dpc);
+
+        schedule_work(&dpc->work);
+
         return IRQ_HANDLED;
 }
 
@@ -289,13 +236,16 @@ static int dpc_probe(struct pcie_device *dev)
         int status;
         u16 ctl, cap;
 
+        if (pcie_aer_get_firmware_first(pdev))
+                return -ENOTSUPP;
+
         dpc = devm_kzalloc(device, sizeof(*dpc), GFP_KERNEL);
         if (!dpc)
                 return -ENOMEM;
 
         dpc->cap_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
         dpc->dev = dev;
-        INIT_WORK(&dpc->work, interrupt_event_handler);
+        INIT_WORK(&dpc->work, dpc_work);
         set_service_data(dev, dpc);
 
         status = devm_request_irq(device, dev->irq, dpc_irq, IRQF_SHARED,
@@ -309,15 +259,23 @@ static int dpc_probe(struct pcie_device *dev)
         pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap);
         pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);
 
-        dpc->rp = (cap & PCI_EXP_DPC_CAP_RP_EXT);
+        dpc->rp_extensions = (cap & PCI_EXP_DPC_CAP_RP_EXT);
+        if (dpc->rp_extensions) {
+                dpc->rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
+                if (dpc->rp_log_size < 4 || dpc->rp_log_size > 9) {
+                        dev_err(device, "RP PIO log size %u is invalid\n",
+                                dpc->rp_log_size);
+                        dpc->rp_log_size = 0;
+                }
+        }
 
         ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN;
         pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
 
         dev_info(device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
-                cap & 0xf, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
+                cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
                 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
-                FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), (cap >> 8) & 0xf,
+                FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), dpc->rp_log_size,
                 FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE));
         return status;
 }
diff --git a/drivers/pci/pcie/pme.c b/drivers/pci/pcie/pme.c
index df290aa58dce..5480f54f7612 100644
--- a/drivers/pci/pcie/pme.c
+++ b/drivers/pci/pcie/pme.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * PCIe Native PME support
  *
  * Copyright (C) 2007 - 2009 Intel Corp
  * Copyright (C) 2007 - 2009 Shaohua Li <shaohua.li@intel.com>
  * Copyright (C) 2009 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License V2.  See the file "COPYING" in the main directory of this archive
- * for more details.
  */
 
 #include <linux/pci.h>
@@ -198,14 +195,14 @@ static void pcie_pme_handle_request(struct pci_dev *port, u16 req_id)
                  * assuming that the PME was reported by a PCIe-PCI bridge that
                  * used devfn different from zero.
                  */
-                dev_dbg(&port->dev, "PME interrupt generated for non-existent device %02x:%02x.%d\n",
+                pci_dbg(port, "PME interrupt generated for non-existent device %02x:%02x.%d\n",
                         busnr, PCI_SLOT(devfn), PCI_FUNC(devfn));
                 found = pcie_pme_from_pci_bridge(bus, 0);
         }
 
  out:
         if (!found)
-                dev_dbg(&port->dev, "Spurious native PME interrupt!\n");
+                pci_dbg(port, "Spurious native PME interrupt!\n");
 }
 
 /**
@@ -345,7 +342,7 @@ static int pcie_pme_probe(struct pcie_device *srv)
                 return ret;
         }
 
-        dev_info(&port->dev, "Signaling PME with IRQ %d\n", srv->irq);
+        pci_info(port, "Signaling PME with IRQ %d\n", srv->irq);
 
         pcie_pme_mark_devices(port);
         pcie_pme_interrupt_enable(port, true);
diff --git a/drivers/pci/pcie/portdrv_acpi.c b/drivers/pci/pcie/portdrv_acpi.c
index 6b8c2f1d0e71..319c94976873 100644
--- a/drivers/pci/pcie/portdrv_acpi.c
+++ b/drivers/pci/pcie/portdrv_acpi.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * PCIe Port Native Services Support, ACPI-Related Part
  *
  * Copyright (C) 2010 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License V2.  See the file "COPYING" in the main directory of this archive
- * for more details.
  */
 
 #include <linux/pci.h>
diff --git a/drivers/pci/pcie/portdrv_bus.c b/drivers/pci/pcie/portdrv_bus.c
index 87e79a6ffb5a..f0fba552a0e2 100644
--- a/drivers/pci/pcie/portdrv_bus.c
+++ b/drivers/pci/pcie/portdrv_bus.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * File:        portdrv_bus.c
  * Purpose:     PCI Express Port Bus Driver's Bus Overloading Functions
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index a59210350c44..ef3bad4ad010 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -216,9 +216,9 @@ static int get_port_device_capability(struct pci_dev *dev)
                 return 0;
 
         cap_mask = PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP
-                        | PCIE_PORT_SERVICE_VC | PCIE_PORT_SERVICE_DPC;
+                        | PCIE_PORT_SERVICE_VC;
         if (pci_aer_available())
-                cap_mask |= PCIE_PORT_SERVICE_AER;
+                cap_mask |= PCIE_PORT_SERVICE_AER | PCIE_PORT_SERVICE_DPC;
 
         if (pcie_ports_auto)
                 pcie_port_platform_notify(dev, &cap_mask);
diff --git a/drivers/pci/pcie/ptm.c b/drivers/pci/pcie/ptm.c
index bab8ac63c4f3..98cfa30f3fae 100644
--- a/drivers/pci/pcie/ptm.c
+++ b/drivers/pci/pcie/ptm.c
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * PCI Express Precision Time Measurement
  * Copyright (c) 2016, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
  */
 
 #include <linux/module.h>
@@ -33,7 +25,7 @@ static void pci_ptm_info(struct pci_dev *dev)
                          dev->ptm_granularity);
                 break;
         }
-        dev_info(&dev->dev, "PTM enabled%s, %s granularity\n",
+        pci_info(dev, "PTM enabled%s, %s granularity\n",
                  dev->ptm_root ? " (root)" : "", clock_desc);
 }
 
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 14e0ea1ff38b..ef5377438a1e 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * probe.c - PCI detection and setup code
  */
@@ -69,8 +70,8 @@ static int find_anything(struct device *dev, void *data)
 }
 
 /*
- * Some device drivers need know if pci is initiated.
- * Basically, we think pci is not initiated when there
+ * Some device drivers need know if PCI is initiated.
+ * Basically, we think PCI is not initiated when there
  * is no device to be found on the pci_bus_type.
  */
 int no_pci_devices(void)
@@ -116,12 +117,16 @@ static u64 pci_size(u64 base, u64 maxbase, u64 mask)
         if (!size)
                 return 0;
 
-        /* Get the lowest of them to find the decode size, and
-           from that the extent.  */
+        /*
+         * Get the lowest of them to find the decode size, and from that
+         * the extent.
+         */
         size = (size & ~(size-1)) - 1;
 
-        /* base == maxbase can be valid only if the BAR has
-           already been programmed with all 1s.  */
+        /*
+         * base == maxbase can be valid only if the BAR has already been
+         * programmed with all 1s.
+         */
         if (base == maxbase && ((base | size) & mask) != mask)
                 return 0;
 
@@ -164,7 +169,7 @@ static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
 #define PCI_COMMAND_DECODE_ENABLE       (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
 
 /**
- * pci_read_base - read a PCI BAR
+ * pci_read_base - Read a PCI BAR
  * @dev: the PCI device
  * @type: type of the BAR
  * @res: resource buffer to be filled in
@@ -253,7 +258,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
 
         sz64 = pci_size(l64, sz64, mask64);
         if (!sz64) {
-                dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
+                pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
                          pos);
                 goto fail;
         }
@@ -264,7 +269,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
                         res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
                         res->start = 0;
                         res->end = 0;
-                        dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
+                        pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
                                 pos, (unsigned long long)sz64);
                         goto out;
                 }
@@ -274,7 +279,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
                         res->flags |= IORESOURCE_UNSET;
                         res->start = 0;
                         res->end = sz64;
-                        dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
+                        pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
                                  pos, (unsigned long long)l64);
                         goto out;
                 }
@@ -301,7 +306,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
                 res->flags |= IORESOURCE_UNSET;
                 res->start = 0;
                 res->end = region.end - region.start;
-                dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
+                pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
                          pos, (unsigned long long)region.start);
         }
 
@@ -312,7 +317,7 @@ fail:
         res->flags = 0;
 out:
         if (res->flags)
-                dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
+                pci_printk(KERN_DEBUG, dev, "reg 0x%x: %pR\n", pos, res);
 
         return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
 }
@@ -375,7 +380,7 @@ static void pci_read_bridge_io(struct pci_bus *child)
                 region.start = base;
                 region.end = limit + io_granularity - 1;
                 pcibios_bus_to_resource(dev->bus, res, &region);
-                dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
+                pci_printk(KERN_DEBUG, dev, "  bridge window %pR\n", res);
         }
 }
 
@@ -397,7 +402,7 @@ static void pci_read_bridge_mmio(struct pci_bus *child)
                 region.start = base;
                 region.end = limit + 0xfffff;
                 pcibios_bus_to_resource(dev->bus, res, &region);
-                dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
+                pci_printk(KERN_DEBUG, dev, "  bridge window %pR\n", res);
         }
 }
 
@@ -437,7 +442,7 @@ static void pci_read_bridge_mmio_pref(struct pci_bus *child)
         limit = (pci_bus_addr_t) limit64;
 
         if (base != base64) {
-                dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
+                pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
                         (unsigned long long) base64);
                 return;
         }
@@ -450,7 +455,7 @@ static void pci_read_bridge_mmio_pref(struct pci_bus *child)
                 region.start = base;
                 region.end = limit + 0xfffff;
                 pcibios_bus_to_resource(dev->bus, res, &region);
-                dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
+                pci_printk(KERN_DEBUG, dev, "  bridge window %pR\n", res);
         }
 }
 
@@ -463,7 +468,7 @@ void pci_read_bridge_bases(struct pci_bus *child)
         if (pci_is_root_bus(child))     /* It's a host bus, nothing to read */
                 return;
 
-        dev_info(&dev->dev, "PCI bridge to %pR%s\n",
+        pci_info(dev, "PCI bridge to %pR%s\n",
                  &child->busn_res,
                  dev->transparent ? " (subtractive decode)" : "");
 
@@ -480,7 +485,7 @@ void pci_read_bridge_bases(struct pci_bus *child)
                         if (res && res->flags) {
                                 pci_bus_add_resource(child, res,
                                                      PCI_SUBTRACTIVE_DECODE);
-                                dev_printk(KERN_DEBUG, &dev->dev,
+                                pci_printk(KERN_DEBUG, dev,
                                            "  bridge window %pR (subtractive decode)\n",
                                            res);
                         }
@@ -764,7 +769,7 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
 
         bridge->bus = bus;
 
-        /* temporarily move resources off the list */
+        /* Temporarily move resources off the list */
         list_splice_init(&bridge->windows, &resources);
         bus->sysdata = bridge->sysdata;
         bus->msi = bridge->msi;
@@ -776,7 +781,7 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
 
         b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
         if (b) {
-                /* If we already got to this bus through a different bridge, ignore it */
+                /* Ignore it if we already got here via a different bridge */
                 dev_dbg(&b->dev, "bus already known\n");
                 err = -EEXIST;
                 goto free;
@@ -869,9 +874,7 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
         int i;
         int ret;
 
-        /*
-         * Allocate a new bus, and inherit stuff from the parent..
-         */
+        /* Allocate a new bus and inherit stuff from the parent */
         child = pci_alloc_bus(parent);
         if (!child)
                 return NULL;
@@ -882,16 +885,14 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
         child->sysdata = parent->sysdata;
         child->bus_flags = parent->bus_flags;
 
-        /* initialize some portions of the bus device, but don't register it
-         * now as the parent is not properly set up yet.
+        /*
+         * Initialize some portions of the bus device, but don't register
+         * it now as the parent is not properly set up yet.
          */
         child->dev.class = &pcibus_class;
         dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
 
-        /*
-         * Set up the primary, secondary and subordinate
-         * bus numbers.
-         */
+        /* Set up the primary, secondary and subordinate bus numbers */
         child->number = child->busn_res.start = busnr;
         child->primary = parent->busn_res.start;
         child->busn_res.end = 0xff;
@@ -907,7 +908,7 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
         pci_set_bus_of_node(child);
         pci_set_bus_speed(child);
 
-        /* Set up default resource pointers and names.. */
+        /* Set up default resource pointers and names */
         for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
                 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
                 child->resource[i]->name = child->name;
@@ -1005,11 +1006,11 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
         secondary = (buses >> 8) & 0xFF;
         subordinate = (buses >> 16) & 0xFF;
 
-        dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
+        pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
                 secondary, subordinate, pass);
 
         if (!primary && (primary != bus->number) && secondary && subordinate) {
-                dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
+                pci_warn(dev, "Primary bus is hard wired to 0\n");
                 primary = bus->number;
         }
 
@@ -1017,13 +1018,15 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
         if (!pass &&
             (primary != bus->number || secondary <= bus->number ||
              secondary > subordinate)) {
-                dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
+                pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
                          secondary, subordinate);
                 broken = 1;
         }
 
-        /* Disable MasterAbortMode during probing to avoid reporting
-           of bus errors (in some architectures) */
+        /*
+         * Disable Master-Abort Mode during probing to avoid reporting of
+         * bus errors in some architectures.
+         */
         pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
         pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
                               bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
@@ -1033,18 +1036,19 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
         if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
             !is_cardbus && !broken) {
                 unsigned int cmax;
+
                 /*
-                 * Bus already configured by firmware, process it in the first
-                 * pass and just note the configuration.
+                 * Bus already configured by firmware, process it in the
+                 * first pass and just note the configuration.
                  */
                 if (pass)
                         goto out;
 
                 /*
-                 * The bus might already exist for two reasons: Either we are
-                 * rescanning the bus or the bus is reachable through more than
-                 * one bridge. The second case can happen with the i450NX
-                 * chipset.
+                 * The bus might already exist for two reasons: Either we
+                 * are rescanning the bus or the bus is reachable through
+                 * more than one bridge. The second case can happen with
+                 * the i450NX chipset.
                  */
                 child = pci_find_bus(pci_domain_nr(bus), secondary);
                 if (!child) {
@@ -1058,24 +1062,29 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
 
                 cmax = pci_scan_child_bus(child);
                 if (cmax > subordinate)
-                        dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
+                        pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
                                  subordinate, cmax);
-                /* subordinate should equal child->busn_res.end */
+
+                /* Subordinate should equal child->busn_res.end */
                 if (subordinate > max)
                         max = subordinate;
         } else {
+
                 /*
                  * We need to assign a number to this bus which we always
                  * do in the second pass.
                  */
                 if (!pass) {
                         if (pcibios_assign_all_busses() || broken || is_cardbus)
-                                /* Temporarily disable forwarding of the
-                                   configuration cycles on all bridges in
-                                   this bus segment to avoid possible
-                                   conflicts in the second pass between two
-                                   bridges programmed with overlapping
-                                   bus ranges. */
+
+                                /*
+                                 * Temporarily disable forwarding of the
+                                 * configuration cycles on all bridges in
+                                 * this bus segment to avoid possible
+                                 * conflicts in the second pass between two
+                                 * bridges programmed with overlapping bus
+                                 * ranges.
+                                 */
                                 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
                                                        buses & ~0xffffff);
                         goto out;
@@ -1084,9 +1093,11 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
                 /* Clear errors */
                 pci_write_config_word(dev, PCI_STATUS, 0xffff);
 
-                /* Prevent assigning a bus number that already exists.
-                 * This can happen when a bridge is hot-plugged, so in
-                 * this case we only re-scan this bus. */
+                /*
+                 * Prevent assigning a bus number that already exists.
+                 * This can happen when a bridge is hot-plugged, so in this
+                 * case we only re-scan this bus.
+                 */
                 child = pci_find_bus(pci_domain_nr(bus), max+1);
                 if (!child) {
                         child = pci_add_new_bus(bus, dev, max+1);
@@ -1113,19 +1124,18 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
                         buses |= CARDBUS_LATENCY_TIMER << 24;
                 }
 
-                /*
-                 * We need to blast all three values with a single write.
-                 */
+                /* We need to blast all three values with a single write */
                 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
 
                 if (!is_cardbus) {
                         child->bridge_ctl = bctl;
                         max = pci_scan_child_bus_extend(child, available_buses);
                 } else {
+
                         /*
-                         * For CardBus bridges, we leave 4 bus numbers
-                         * as cards with a PCI-to-PCI bridge can be
-                         * inserted later.
+                         * For CardBus bridges, we leave 4 bus numbers as
+                         * cards with a PCI-to-PCI bridge can be inserted
+                         * later.
                          */
                         for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
                                 struct pci_bus *parent = bus;
@@ -1141,10 +1151,11 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
                                         parent = parent->parent;
                                 }
                                 if (j) {
+
                                         /*
-                                         * Often, there are two cardbus bridges
-                                         * -- try to leave one valid bus number
-                                         * for each one.
+                                         * Often, there are two CardBus
+                                         * bridges -- try to leave one
+                                         * valid bus number for each one.
                                          */
                                         i /= 2;
                                         break;
@@ -1152,9 +1163,8 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
                         }
                         max += i;
                 }
-                /*
-                 * Set the subordinate bus number to its real value.
-                 */
+
+                /* Set subordinate bus number to its real value */
                 pci_bus_update_busn_res_end(child, max);
                 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
         }
@@ -1295,7 +1305,7 @@ static void set_pcie_thunderbolt(struct pci_dev *dev)
 }
 
 /**
- * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
+ * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
  * @dev: PCI device
  *
  * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
@@ -1332,7 +1342,7 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
 }
 
 /**
- * pci_cfg_space_size - get the configuration space size of the PCI device.
+ * pci_cfg_space_size - Get the configuration space size of the PCI device
  * @dev: PCI device
  *
  * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
@@ -1398,7 +1408,7 @@ static void pci_msi_setup_pci_dev(struct pci_dev *dev)
 }
 
 /**
- * pci_intx_mask_broken - test PCI_COMMAND_INTX_DISABLE writability
+ * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
  * @dev: PCI device
  *
  * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev.  Check this
@@ -1426,11 +1436,11 @@ static int pci_intx_mask_broken(struct pci_dev *dev)
 }
 
 /**
- * pci_setup_device - fill in class and map information of a device
+ * pci_setup_device - Fill in class and map information of a device
  * @dev: the device structure to fill
  *
  * Initialize the device structure with information about the device's
- * vendor,class,memory and IO-space addresses,IRQ lines etc.
+ * vendor,class,memory and IO-space addresses, IRQ lines etc.
  * Called at initialisation of the PCI subsystem and by CardBus services.
  * Returns 0 on success and negative if unknown type of device (not normal,
  * bridge or CardBus).
@@ -1456,8 +1466,11 @@ int pci_setup_device(struct pci_dev *dev)
         set_pcie_port_type(dev);
 
         pci_dev_assign_slot(dev);
-        /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
-           set this higher, assuming the system even supports it.  */
+
+        /*
+         * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
+         * set this higher, assuming the system even supports it.
+         */
         dev->dma_mask = 0xffffffff;
 
         dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
@@ -1468,13 +1481,13 @@ int pci_setup_device(struct pci_dev *dev)
         dev->revision = class & 0xff;
         dev->class = class >> 8;                    /* upper 3 bytes */
 
-        dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
+        pci_printk(KERN_DEBUG, dev, "[%04x:%04x] type %02x class %#08x\n",
                    dev->vendor, dev->device, dev->hdr_type, dev->class);
 
-        /* need to have dev->class ready */
+        /* Need to have dev->class ready */
         dev->cfg_size = pci_cfg_space_size(dev);
 
-        /* need to have dev->cfg_size ready */
+        /* Need to have dev->cfg_size ready */
         set_pcie_thunderbolt(dev);
 
         /* "Unknown power state" */
@@ -1482,13 +1495,14 @@ int pci_setup_device(struct pci_dev *dev)
 
         /* Early fixups, before probing the BARs */
         pci_fixup_device(pci_fixup_early, dev);
-        /* device class may be changed after fixup */
+
+        /* Device class may be changed after fixup */
         class = dev->class >> 8;
 
         if (dev->non_compliant_bars) {
                 pci_read_config_word(dev, PCI_COMMAND, &cmd);
                 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
-                        dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
+                        pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
                         cmd &= ~PCI_COMMAND_IO;
                         cmd &= ~PCI_COMMAND_MEMORY;
                         pci_write_config_word(dev, PCI_COMMAND, cmd);
@@ -1521,14 +1535,14 @@ int pci_setup_device(struct pci_dev *dev)
                                 res = &dev->resource[0];
                                 res->flags = LEGACY_IO_RESOURCE;
                                 pcibios_bus_to_resource(dev->bus, res, &region);
-                                dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
+                                pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
                                          res);
                                 region.start = 0x3F6;
                                 region.end = 0x3F6;
                                 res = &dev->resource[1];
                                 res->flags = LEGACY_IO_RESOURCE;
                                 pcibios_bus_to_resource(dev->bus, res, &region);
-                                dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
+                                pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
                                          res);
                         }
                         if ((progif & 4) == 0) {
@@ -1537,14 +1551,14 @@ int pci_setup_device(struct pci_dev *dev)
                                 res = &dev->resource[2];
                                 res->flags = LEGACY_IO_RESOURCE;
                                 pcibios_bus_to_resource(dev->bus, res, &region);
-                                dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
+                                pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
                                          res);
                                 region.start = 0x376;
                                 region.end = 0x376;
                                 res = &dev->resource[3];
                                 res->flags = LEGACY_IO_RESOURCE;
                                 pcibios_bus_to_resource(dev->bus, res, &region);
-                                dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
+                                pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
                                          res);
                         }
                 }
@@ -1553,9 +1567,12 @@ int pci_setup_device(struct pci_dev *dev)
         case PCI_HEADER_TYPE_BRIDGE:                /* bridge header */
                 if (class != PCI_CLASS_BRIDGE_PCI)
                         goto bad;
-                /* The PCI-to-PCI bridge spec requires that subtractive
-                   decoding (i.e. transparent) bridge must have programming
-                   interface code of 0x01. */
+
+                /*
+                 * The PCI-to-PCI bridge spec requires that subtractive
+                 * decoding (i.e. transparent) bridge must have programming
+                 * interface code of 0x01.
+                 */
                 pci_read_irq(dev);
                 dev->transparent = ((dev->class & 0xff) == 1);
                 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
@@ -1577,12 +1594,12 @@ int pci_setup_device(struct pci_dev *dev)
                 break;
 
         default:                                    /* unknown header */
-                dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
+                pci_err(dev, "unknown header type %02x, ignoring device\n",
                         dev->hdr_type);
                 return -EIO;
 
         bad:
-                dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
+                pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
                         dev->class, dev->hdr_type);
                 dev->class = PCI_CLASS_NOT_DEFINED << 8;
         }
@@ -1606,7 +1623,7 @@ static void pci_configure_mps(struct pci_dev *dev)
                 return;
 
         if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
-                dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
+                pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
                          mps, pci_name(bridge), p_mps);
                 return;
         }
@@ -1620,12 +1637,12 @@ static void pci_configure_mps(struct pci_dev *dev)
 
         rc = pcie_set_mps(dev, p_mps);
         if (rc) {
-                dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
+                pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
                          p_mps);
                 return;
         }
 
-        dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
+        pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
                  p_mps, mps, 128 << dev->pcie_mpss);
 }
 
@@ -1645,8 +1662,7 @@ static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
                 hpp = &pci_default_type0;
 
         if (hpp->revision > 1) {
-                dev_warn(&dev->dev,
-                         "PCI settings rev %d not supported; using defaults\n",
+                pci_warn(dev, "PCI settings rev %d not supported; using defaults\n",
                          hpp->revision);
                 hpp = &pci_default_type0;
         }
@@ -1684,7 +1700,7 @@ static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
         if (!pos)
                 return;
 
-        dev_warn(&dev->dev, "PCI-X settings not supported\n");
+        pci_warn(dev, "PCI-X settings not supported\n");
 }
 
 static bool pcie_root_rcb_set(struct pci_dev *dev)
@@ -1714,7 +1730,7 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
                 return;
 
         if (hpp->revision > 1) {
-                dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
+                pci_warn(dev, "PCIe settings rev %d not supported\n",
                          hpp->revision);
                 return;
         }
@@ -1772,6 +1788,7 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
         /* Initialize Advanced Error Capabilities and Control Register */
         pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
         reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
+
         /* Don't enable ECRC generation or checking if unsupported */
         if (!(reg32 & PCI_ERR_CAP_ECRC_GENC))
                 reg32 &= ~PCI_ERR_CAP_ECRC_GENE;
@@ -1818,7 +1835,7 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
          */
         if (host->no_ext_tags) {
                 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
-                        dev_info(&dev->dev, "disabling Extended Tags\n");
+                        pci_info(dev, "disabling Extended Tags\n");
                         pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
                                                    PCI_EXP_DEVCTL_EXT_TAG);
                 }
@@ -1826,7 +1843,7 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
         }
 
         if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
-                dev_info(&dev->dev, "enabling Extended Tags\n");
+                pci_info(dev, "enabling Extended Tags\n");
                 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
                                          PCI_EXP_DEVCTL_EXT_TAG);
         }
@@ -1871,10 +1888,42 @@ static void pci_configure_relaxed_ordering(struct pci_dev *dev)
         if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
                 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
                                            PCI_EXP_DEVCTL_RELAX_EN);
-                dev_info(&dev->dev, "Disable Relaxed Ordering because the Root Port didn't support it\n");
+                pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
         }
 }
 
+static void pci_configure_ltr(struct pci_dev *dev)
+{
+#ifdef CONFIG_PCIEASPM
+        u32 cap;
+        struct pci_dev *bridge;
+
+        if (!pci_is_pcie(dev))
+                return;
+
+        pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
+        if (!(cap & PCI_EXP_DEVCAP2_LTR))
+                return;
+
+        /*
+         * Software must not enable LTR in an Endpoint unless the Root
+         * Complex and all intermediate Switches indicate support for LTR.
+         * PCIe r3.1, sec 6.18.
+         */
+        if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
+                dev->ltr_path = 1;
+        else {
+                bridge = pci_upstream_bridge(dev);
+                if (bridge && bridge->ltr_path)
+                        dev->ltr_path = 1;
+        }
+
+        if (dev->ltr_path)
+                pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
+                                         PCI_EXP_DEVCTL2_LTR_EN);
+#endif
+}
+
 static void pci_configure_device(struct pci_dev *dev)
 {
         struct hotplug_params hpp;
@@ -1883,6 +1932,7 @@ static void pci_configure_device(struct pci_dev *dev)
         pci_configure_mps(dev);
         pci_configure_extended_tags(dev, NULL);
         pci_configure_relaxed_ordering(dev);
+        pci_configure_ltr(dev);
 
         memset(&hpp, 0, sizeof(hpp));
         ret = pci_get_hp_params(dev, &hpp);
@@ -1902,10 +1952,11 @@ static void pci_release_capabilities(struct pci_dev *dev)
 }
 
 /**
- * pci_release_dev - free a pci device structure when all users of it are finished.
+ * pci_release_dev - Free a PCI device structure when all users of it are
+ *                   finished
  * @dev: device that's been disconnected
  *
- * Will be called only by the device core when all users of this pci device are
+ * Will be called only by the device core when all users of this PCI device are
  * done.
  */
 static void pci_release_dev(struct device *dev)
@@ -1993,7 +2044,7 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
         if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
                 return false;
 
-        /* some broken boards return 0 or ~0 if a slot is empty: */
+        /* Some broken boards return 0 or ~0 if a slot is empty: */
         if (*l == 0xffffffff || *l == 0x00000000 ||
             *l == 0x0000ffff || *l == 0xffff0000)
                 return false;
@@ -2006,8 +2057,8 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
 
 /*
- * Read the config data for a PCI device, sanity-check it
- * and fill in the dev structure...
+ * Read the config data for a PCI device, sanity-check it,
+ * and fill in the dev structure.
  */
 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
 {
@@ -2073,7 +2124,7 @@ static void pci_init_capabilities(struct pci_dev *dev)
 }
 
 /*
- * This is the equivalent of pci_host_bridge_msi_domain that acts on
+ * This is the equivalent of pci_host_bridge_msi_domain() that acts on
  * devices. Firmware interfaces that can select the MSI domain on a
  * per-device basis should be called from here.
  */
@@ -2082,7 +2133,7 @@ static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
         struct irq_domain *d;
 
         /*
-         * If a domain has been set through the pcibios_add_device
+         * If a domain has been set through the pcibios_add_device()
          * callback, then this is the one (platform code knows best).
          */
         d = dev_get_msi_domain(&dev->dev);
@@ -2136,10 +2187,10 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
         /* Fix up broken headers */
         pci_fixup_device(pci_fixup_header, dev);
 
-        /* moved out from quirk header fixup code */
+        /* Moved out from quirk header fixup code */
         pci_reassigndev_resource_alignment(dev);
 
-        /* Clear the state_saved flag. */
+        /* Clear the state_saved flag */
         dev->state_saved = false;
 
         /* Initialize various capabilities */
@@ -2156,7 +2207,7 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
         ret = pcibios_add_device(dev);
         WARN_ON(ret < 0);
 
-        /* Setup MSI irq domain */
+        /* Set up MSI IRQ domain */
         pci_set_msi_domain(dev);
 
         /* Notifier could use PCI capabilities */
@@ -2215,29 +2266,34 @@ static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
 
 static int only_one_child(struct pci_bus *bus)
 {
-        struct pci_dev *parent = bus->self;
+        struct pci_dev *bridge = bus->self;
 
-        if (!parent || !pci_is_pcie(parent))
+        /*
+         * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
+         * we scan for all possible devices, not just Device 0.
+         */
+        if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
                 return 0;
-        if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
-                return 1;
 
         /*
-         * PCIe downstream ports are bridges that normally lead to only a
-         * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all
-         * possible devices, not just device 0.  See PCIe spec r3.0,
-         * sec 7.3.1.
+         * A PCIe Downstream Port normally leads to a Link with only Device
+         * 0 on it (PCIe spec r3.1, sec 7.3.1).  As an optimization, scan
+         * only for Device 0 in that situation.
+         *
+         * Checking has_secondary_link is a hack to identify Downstream
+         * Ports because sometimes Switches are configured such that the
+         * PCIe Port Type labels are backwards.
          */
-        if (parent->has_secondary_link &&
-            !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
+        if (bridge && pci_is_pcie(bridge) && bridge->has_secondary_link)
                 return 1;
+
         return 0;
 }
 
 /**
- * pci_scan_slot - scan a PCI slot on a bus for devices.
+ * pci_scan_slot - Scan a PCI slot on a bus for devices
  * @bus: PCI bus to scan
- * @devfn: slot number to scan (must have zero function.)
+ * @devfn: slot number to scan (must have zero function)
  *
  * Scan a PCI slot on the specified PCI bus for devices, adding
  * discovered devices to the @bus->devices list.  New devices
@@ -2268,7 +2324,7 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
                 }
         }
 
-        /* only one slot has pcie device */
+        /* Only one slot has PCIe device */
         if (bus->self && nr)
                 pcie_aspm_init_link_state(bus->self);
 
@@ -2317,7 +2373,9 @@ static void pcie_write_mps(struct pci_dev *dev, int mps)
 
                 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
                     dev->bus->self)
-                        /* For "Performance", the assumption is made that
+
+                        /*
+                         * For "Performance", the assumption is made that
                          * downstream communication will never be larger than
                          * the MRRS.  So, the MPS only needs to be configured
                          * for the upstream communication.  This being the case,
@@ -2334,27 +2392,30 @@ static void pcie_write_mps(struct pci_dev *dev, int mps)
 
         rc = pcie_set_mps(dev, mps);
         if (rc)
-                dev_err(&dev->dev, "Failed attempting to set the MPS\n");
+                pci_err(dev, "Failed attempting to set the MPS\n");
 }
 
 static void pcie_write_mrrs(struct pci_dev *dev)
 {
         int rc, mrrs;
 
-        /* In the "safe" case, do not configure the MRRS.  There appear to be
+        /*
+         * In the "safe" case, do not configure the MRRS.  There appear to be
          * issues with setting MRRS to 0 on a number of devices.
          */
         if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
                 return;
 
-        /* For Max performance, the MRRS must be set to the largest supported
+        /*
+         * For max performance, the MRRS must be set to the largest supported
          * value.  However, it cannot be configured larger than the MPS the
          * device or the bus can support.  This should already be properly
-         * configured by a prior call to pcie_write_mps.
+         * configured by a prior call to pcie_write_mps().
          */
         mrrs = pcie_get_mps(dev);
 
-        /* MRRS is a R/W register.  Invalid values can be written, but a
+        /*
+         * MRRS is a R/W register.  Invalid values can be written, but a
          * subsequent read will verify if the value is acceptable or not.
          * If the MRRS value provided is not acceptable (e.g., too large),
          * shrink the value until it is acceptable to the HW.
@@ -2364,12 +2425,12 @@ static void pcie_write_mrrs(struct pci_dev *dev)
                 if (!rc)
                         break;
 
-                dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
+                pci_warn(dev, "Failed attempting to set the MRRS\n");
                 mrrs /= 2;
         }
 
         if (mrrs < 128)
-                dev_err(&dev->dev, "MRRS was unable to be configured with a safe value.  If problems are experienced, try running with pci=pcie_bus_safe\n");
+                pci_err(dev, "MRRS was unable to be configured with a safe value.  If problems are experienced, try running with pci=pcie_bus_safe\n");
 }
 
 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
@@ -2389,14 +2450,15 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
         pcie_write_mps(dev, mps);
         pcie_write_mrrs(dev);
 
-        dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
+        pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
                  pcie_get_mps(dev), 128 << dev->pcie_mpss,
                  orig_mps, pcie_get_readrq(dev));
 
         return 0;
 }
 
-/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
+/*
+ * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
  * parents then children fashion.  If this changes, then this code will not
  * work as designed.
  */
@@ -2410,7 +2472,8 @@ void pcie_bus_configure_settings(struct pci_bus *bus)
         if (!pci_is_pcie(bus->self))
                 return;
 
-        /* FIXME - Peer to peer DMA is possible, though the endpoint would need
+        /*
+         * FIXME - Peer to peer DMA is possible, though the endpoint would need
          * to be aware of the MPS of the destination.  To work around this,
          * simply force the MPS of the entire system to the smallest possible.
          */
@@ -2464,7 +2527,7 @@ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
         for (devfn = 0; devfn < 0x100; devfn += 8)
                 pci_scan_slot(bus, devfn);
 
-        /* Reserve buses for SR-IOV capability. */
+        /* Reserve buses for SR-IOV capability */
         used_buses = pci_iov_bus_range(bus);
         max += used_buses;
 
@@ -2506,6 +2569,7 @@ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
                 unsigned int buses = 0;
 
                 if (!hotplug_bridges && normal_bridges == 1) {
+
                         /*
                          * There is only one bridge on the bus (upstream
                          * port) so it gets all available buses which it
@@ -2514,6 +2578,7 @@ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
                          */
                         buses = available_buses;
                 } else if (dev->is_hotplug_bridge) {
+
                         /*
                          * Distribute the extra buses between hotplug
                          * bridges if any.
@@ -2572,8 +2637,8 @@ unsigned int pci_scan_child_bus(struct pci_bus *bus)
 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
 
 /**
- * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
- * @bridge: Host bridge to set up.
+ * pcibios_root_bridge_prepare - Platform-specific host bridge setup
+ * @bridge: Host bridge to set up
  *
  * Default empty implementation.  Replace with an architecture-specific setup
  * routine, if necessary.
@@ -2620,6 +2685,39 @@ err_out:
 }
 EXPORT_SYMBOL_GPL(pci_create_root_bus);
 
+int pci_host_probe(struct pci_host_bridge *bridge)
+{
+        struct pci_bus *bus, *child;
+        int ret;
+
+        ret = pci_scan_root_bus_bridge(bridge);
+        if (ret < 0) {
+                dev_err(bridge->dev.parent, "Scanning root bridge failed");
+                return ret;
+        }
+
+        bus = bridge->bus;
+
+        /*
+         * We insert PCI resources into the iomem_resource and
+         * ioport_resource trees in either pci_bus_claim_resources()
+         * or pci_bus_assign_resources().
+         */
+        if (pci_has_flag(PCI_PROBE_ONLY)) {
+                pci_bus_claim_resources(bus);
+        } else {
+                pci_bus_size_bridges(bus);
+                pci_bus_assign_resources(bus);
+
+                list_for_each_entry(child, &bus->children, node)
+                        pcie_bus_configure_settings(child);
+        }
+
+        pci_bus_add_devices(bus);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(pci_host_probe);
+
 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
 {
         struct resource *res = &b->busn_res;
@@ -2776,7 +2874,7 @@ struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
 EXPORT_SYMBOL(pci_scan_bus);
 
 /**
- * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
+ * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
  * @bridge: PCI bridge for the bus to scan
  *
  * Scan a PCI bus and child buses for new devices, add them,
@@ -2801,11 +2899,11 @@ unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
 }
 
 /**
- * pci_rescan_bus - scan a PCI bus for devices.
+ * pci_rescan_bus - Scan a PCI bus for devices
  * @bus: PCI bus to scan
  *
- * Scan a PCI bus and child buses for new devices, adds them,
- * and enables them.
+ * Scan a PCI bus and child buses for new devices, add them,
+ * and enable them.
  *
  * Returns the max number of subordinate bus discovered.
  */
@@ -2874,7 +2972,7 @@ int pci_hp_add_bridge(struct pci_dev *dev)
                         break;
         }
         if (busnr-- > end) {
-                dev_err(&dev->dev, "No bus number available for hot-added bridge\n");
+                pci_err(dev, "No bus number available for hot-added bridge\n");
                 return -1;
         }
 
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 10684b17d0bd..fc734014206f 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -19,7 +19,6 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/acpi.h>
-#include <linux/kallsyms.h>
 #include <linux/dmi.h>
 #include <linux/pci-aspm.h>
 #include <linux/ioport.h>
@@ -66,7 +65,7 @@ static void quirk_passive_release(struct pci_dev *dev)
         while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
                 pci_read_config_byte(d, 0x82, &dlc);
                 if (!(dlc & 1<<1)) {
-                        dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
+                        pci_info(d, "PIIX3: Enabling Passive Release\n");
                         dlc |= 1<<1;
                         pci_write_config_byte(d, 0x82, dlc);
                 }
@@ -86,7 +85,7 @@ static void quirk_isa_dma_hangs(struct pci_dev *dev)
 {
         if (!isa_dma_bridge_buggy) {
                 isa_dma_bridge_buggy = 1;
-                dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
+                pci_info(dev, "Activating ISA DMA hang workarounds\n");
         }
 }
         /*
@@ -115,7 +114,7 @@ static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
         pm1a = inw(pmbase);
 
         if (pm1a & 0x10) {
-                dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
+                pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
                 outw(0x10, pmbase);
         }
 }
@@ -127,7 +126,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk
 static void quirk_nopcipci(struct pci_dev *dev)
 {
         if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
-                dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
+                pci_info(dev, "Disabling direct PCI/PCI transfers\n");
                 pci_pci_problems |= PCIPCI_FAIL;
         }
 }
@@ -140,7 +139,7 @@ static void quirk_nopciamd(struct pci_dev *dev)
         pci_read_config_byte(dev, 0x08, &rev);
         if (rev == 0x13) {
                 /* Erratum 24 */
-                dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
+                pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
                 pci_pci_problems |= PCIAGP_FAIL;
         }
 }
@@ -152,7 +151,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8151_0,	quirk_nopci
 static void quirk_triton(struct pci_dev *dev)
 {
         if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
-                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
+                pci_info(dev, "Limiting direct PCI/PCI transfers\n");
                 pci_pci_problems |= PCIPCI_TRITON;
         }
 }
@@ -212,7 +211,7 @@ static void quirk_vialatency(struct pci_dev *dev)
         busarb &= ~(1<<5);
         busarb |= (1<<4);
         pci_write_config_byte(dev, 0x76, busarb);
-        dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
+        pci_info(dev, "Applying VIA southbridge workaround\n");
 exit:
         pci_dev_put(p);
 }
@@ -230,7 +229,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8361,		quirk_viala
 static void quirk_viaetbf(struct pci_dev *dev)
 {
         if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
-                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
+                pci_info(dev, "Limiting direct PCI/PCI transfers\n");
                 pci_pci_problems |= PCIPCI_VIAETBF;
         }
 }
@@ -239,7 +238,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C597_0,	quirk_via
 static void quirk_vsfx(struct pci_dev *dev)
 {
         if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
-                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
+                pci_info(dev, "Limiting direct PCI/PCI transfers\n");
                 pci_pci_problems |= PCIPCI_VSFX;
         }
 }
@@ -254,7 +253,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C576,	quirk_vsfx)
 static void quirk_alimagik(struct pci_dev *dev)
 {
         if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
-                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
+                pci_info(dev, "Limiting direct PCI/PCI transfers\n");
                 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
         }
 }
@@ -268,7 +267,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M1651,		quirk_alimagi
 static void quirk_natoma(struct pci_dev *dev)
 {
         if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
-                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
+                pci_info(dev, "Limiting direct PCI/PCI transfers\n");
                 pci_pci_problems |= PCIPCI_NATOMA;
         }
 }
@@ -313,7 +312,7 @@ static void quirk_extend_bar_to_page(struct pci_dev *dev)
                         r->end = PAGE_SIZE - 1;
                         r->start = 0;
                         r->flags |= IORESOURCE_UNSET;
-                        dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
+                        pci_info(dev, "expanded BAR %d to page size: %pR\n",
                                  i, r);
                 }
         }
@@ -360,7 +359,7 @@ static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
         bus_region.end = region + size - 1;
         pcibios_bus_to_resource(dev->bus, res, &bus_region);
 
-        dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
+        pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
                  name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
 }
 
@@ -381,7 +380,7 @@ static void quirk_cs5536_vsa(struct pci_dev *dev)
                 quirk_io(dev, 0,   8, name);    /* SMB */
                 quirk_io(dev, 1, 256, name);    /* GPIO */
                 quirk_io(dev, 2,  64, name);    /* MFGPT */
-                dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n",
+                pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
                          name);
         }
 }
@@ -409,7 +408,7 @@ static void quirk_io_region(struct pci_dev *dev, int port,
         pcibios_bus_to_resource(dev->bus, res, &bus_region);
 
         if (!pci_claim_resource(dev, nr))
-                dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
+                pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
 }
 
 /*
@@ -418,7 +417,7 @@ static void quirk_io_region(struct pci_dev *dev, int port,
  */
 static void quirk_ati_exploding_mce(struct pci_dev *dev)
 {
-        dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
+        pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
         /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
         request_region(0x3b0, 0x0C, "RadeonIGP");
         request_region(0x3d3, 0x01, "RadeonIGP");
@@ -441,7 +440,7 @@ static void quirk_amd_nl_class(struct pci_dev *pdev)
 
         /* Use "USB Device (not host controller)" class */
         pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
-        dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
+        pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
                  class, pdev->class);
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
@@ -488,8 +487,7 @@ static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int p
          * let's get enough confirmation reports first.
          */
         base &= -size;
-        dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base,
-                 base + size - 1);
+        pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
 }
 
 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
@@ -514,8 +512,7 @@ static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int
          * reserve it, but let's get enough confirmation reports first.
          */
         base &= -size;
-        dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base,
-                 base + size - 1);
+        pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
 }
 
 /*
@@ -644,7 +641,7 @@ static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const cha
         base &= ~(size-1);
 
         /* Just print it out for now. We should reserve it after more debugging */
-        dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
+        pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
 }
 
 static void quirk_ich6_lpc(struct pci_dev *dev)
@@ -679,7 +676,7 @@ static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const cha
         mask |= 3;
 
         /* Just print it out for now. We should reserve it after more debugging */
-        dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
+        pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
 }
 
 /* ICH7-10 has the same common LPC generic IO decode registers */
@@ -758,7 +755,7 @@ static void quirk_xio2000a(struct pci_dev *dev)
         struct pci_dev *pdev;
         u16 command;
 
-        dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
+        pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
         list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
                 pci_read_config_word(pdev, PCI_COMMAND, &command);
                 if (command & PCI_COMMAND_FAST_BACK)
@@ -788,7 +785,7 @@ static void quirk_via_ioapic(struct pci_dev *dev)
         else
                 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
 
-        dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
+        pci_info(dev, "%sbling VIA external APIC routing\n",
                tmp == 0 ? "Disa" : "Ena");
 
         /* Offset 0x58: External APIC IRQ output control */
@@ -810,7 +807,7 @@ static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
 
         pci_read_config_byte(dev, 0x5B, &misc_control2);
         if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
-                dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
+                pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
                 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
         }
 }
@@ -829,8 +826,8 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk
 static void quirk_amd_ioapic(struct pci_dev *dev)
 {
         if (dev->revision >= 0x02) {
-                dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
-                dev_warn(&dev->dev, "        : booting with the \"noapic\" option\n");
+                pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
+                pci_warn(dev, "        : booting with the \"noapic\" option\n");
         }
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_VIPER_7410,   quirk_amd_ioapic);
@@ -854,7 +851,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_lin
 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
 {
         if (dev->subordinate && dev->revision <= 0x12) {
-                dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
+                pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
                          dev->revision);
                 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
         }
@@ -962,7 +959,7 @@ static void quirk_via_vlink(struct pci_dev *dev)
 
         pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
         if (new_irq != irq) {
-                dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
+                pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
                         irq, new_irq);
                 udelay(15);     /* unknown if delay really needed */
                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
@@ -1011,7 +1008,7 @@ static void quirk_amd_ordering(struct pci_dev *dev)
         pci_read_config_dword(dev, 0x4C, &pcic);
         if ((pcic & 6) != 6) {
                 pcic |= 6;
-                dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
+                pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
                 pci_write_config_dword(dev, 0x4C, pcic);
                 pci_read_config_dword(dev, 0x84, &pcic);
                 pcic |= (1 << 23);      /* Required in this mode */
@@ -1064,7 +1061,7 @@ static void quirk_mediagx_master(struct pci_dev *dev)
         pci_read_config_byte(dev, 0x41, &reg);
         if (reg & 2) {
                 reg &= ~2;
-                dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
+                pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
                          reg);
                 pci_write_config_byte(dev, 0x41, reg);
         }
@@ -1087,7 +1084,7 @@ static void quirk_disable_pxb(struct pci_dev *pdev)
         if (config & (1<<6)) {
                 config &= ~(1<<6);
                 pci_write_config_word(pdev, 0x40, config);
-                dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
+                pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
         }
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82454NX,    quirk_disable_pxb);
@@ -1107,7 +1104,7 @@ static void quirk_amd_ide_mode(struct pci_dev *pdev)
                 pci_write_config_byte(pdev, 0x40, tmp);
 
                 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
-                dev_info(&pdev->dev, "set SATA to AHCI mode\n");
+                pci_info(pdev, "set SATA to AHCI mode\n");
         }
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
@@ -1145,7 +1142,7 @@ static void quirk_ide_samemode(struct pci_dev *pdev)
         pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
 
         if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
-                dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
+                pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
                 prog &= ~5;
                 pdev->class &= ~5;
                 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
@@ -1356,10 +1353,10 @@ static void asus_hides_smbus_lpc(struct pci_dev *dev)
                 pci_write_config_word(dev, 0xF2, val & (~0x8));
                 pci_read_config_word(dev, 0xF2, &val);
                 if (val & 0x8)
-                        dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
+                        pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
                                  val);
                 else
-                        dev_info(&dev->dev, "Enabled i801 SMBus device\n");
+                        pci_info(dev, "Enabled i801 SMBus device\n");
         }
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801AA_0,  asus_hides_smbus_lpc);
@@ -1411,7 +1408,7 @@ static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
                 return;
         iounmap(asus_rcba_base);
         asus_rcba_base = NULL;
-        dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
+        pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
 }
 
 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
@@ -1433,7 +1430,7 @@ static void quirk_sis_96x_smbus(struct pci_dev *dev)
         u8 val = 0;
         pci_read_config_byte(dev, 0x77, &val);
         if (val & 0x10) {
-                dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
+                pci_info(dev, "Enabling SiS 96x SMBus\n");
                 pci_write_config_byte(dev, 0x77, val & ~0x10);
         }
 }
@@ -1505,10 +1502,10 @@ static void asus_hides_ac97_lpc(struct pci_dev *dev)
                 pci_write_config_byte(dev, 0x50, val & (~0xc0));
                 pci_read_config_byte(dev, 0x50, &val);
                 if (val & 0xc0)
-                        dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
+                        pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
                                  val);
                 else
-                        dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
+                        pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
         }
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
@@ -1599,7 +1596,7 @@ static void quirk_jmicron_async_suspend(struct pci_dev *dev)
 {
         if (dev->multifunction) {
                 device_disable_async_suspend(&dev->dev);
-                dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
+                pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
         }
 }
 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
@@ -1636,8 +1633,8 @@ static void quirk_pcie_mch(struct pci_dev *pdev)
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7520_MCH,  quirk_pcie_mch);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7320_MCH,  quirk_pcie_mch);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7525_MCH,  quirk_pcie_mch);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI,   0x1610, quirk_pcie_mch);
 
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
 
 /*
  * It's possible for the MSI to get corrupted if shpc and acpi
@@ -1646,7 +1643,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI,	0x1610,	quirk_pcie_mch);
 static void quirk_pcie_pxh(struct pci_dev *dev)
 {
         dev->no_msi = 1;
-        dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
+        pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHD_0,     quirk_pcie_pxh);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHD_1,     quirk_pcie_pxh);
@@ -1692,7 +1689,7 @@ static void quirk_radeon_pm(struct pci_dev *dev)
             dev->subsystem_device == 0x00e2) {
                 if (dev->d3_delay < 20) {
                         dev->d3_delay = 20;
-                        dev_info(&dev->dev, "extending delay after power-on from D3 to %d msec\n",
+                        pci_info(dev, "extending delay after power-on from D3 to %d msec\n",
                                  dev->d3_delay);
                 }
         }
@@ -1736,7 +1733,7 @@ static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
                 return;
 
         dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
-        dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
+        pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
                  dev->vendor, dev->device);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80333_0,    quirk_reroute_to_boot_interrupts_intel);
@@ -1779,7 +1776,7 @@ static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
         pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
         pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
 
-        dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
+        pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
                  dev->vendor, dev->device);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10,      quirk_disable_intel_boot_interrupt);
@@ -1812,7 +1809,7 @@ static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
 
         pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
 
-        dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
+        pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
                  dev->vendor, dev->device);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,        quirk_disable_broadcom_boot_interrupt);
@@ -1845,7 +1842,7 @@ static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
         pci_config_dword &= ~AMD_813X_NOIOAMODE;
         pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
 
-        dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
+        pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
                  dev->vendor, dev->device);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_8131_BRIDGE,  quirk_disable_amd_813x_boot_interrupt);
@@ -1864,12 +1861,12 @@ static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
 
         pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
         if (!pci_config_word) {
-                dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n",
+                pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
                          dev->vendor, dev->device);
                 return;
         }
         pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
-        dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
+        pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
                  dev->vendor, dev->device);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,      quirk_disable_amd_8111_boot_interrupt);
@@ -1913,7 +1910,7 @@ static void quirk_plx_pci9050(struct pci_dev *dev)
                 if (pci_resource_len(dev, bar) == 0x80 &&
                     (pci_resource_start(dev, bar) & 0x80)) {
                         struct resource *r = &dev->resource[bar];
-                        dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
+                        pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
                                  bar);
                         r->flags |= IORESOURCE_UNSET;
                         r->start = 0;
@@ -1960,7 +1957,7 @@ static void quirk_netmos(struct pci_dev *dev)
         case PCI_DEVICE_ID_NETMOS_9845:
         case PCI_DEVICE_ID_NETMOS_9855:
                 if (num_parallel) {
-                        dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
+                        pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
                                 dev->device, num_parallel, num_serial);
                         dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
                             (dev->class & 0xff);
@@ -2046,13 +2043,13 @@ static void quirk_e100_interrupt(struct pci_dev *dev)
         /* Convert from PCI bus to resource space.  */
         csr = ioremap(pci_resource_start(dev, 0), 8);
         if (!csr) {
-                dev_warn(&dev->dev, "Can't map e100 registers\n");
+                pci_warn(dev, "Can't map e100 registers\n");
                 return;
         }
 
         cmd_hi = readb(csr + 3);
         if (cmd_hi == 0) {
-                dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n");
+                pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
                 writeb(1, csr + 3);
         }
 
@@ -2067,7 +2064,7 @@ DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
  */
 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
 {
-        dev_info(&dev->dev, "Disabling L0s\n");
+        pci_info(dev, "Disabling L0s\n");
         pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
@@ -2097,7 +2094,7 @@ static void fixup_rev1_53c810(struct pci_dev *dev)
                 return;
 
         dev->class = PCI_CLASS_STORAGE_SCSI << 8;
-        dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
+        pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
                  class, dev->class);
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
@@ -2110,7 +2107,7 @@ static void quirk_p64h2_1k_io(struct pci_dev *dev)
         pci_read_config_word(dev, 0x40, &en1k);
 
         if (en1k & 0x200) {
-                dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
+                pci_info(dev, "Enable I/O Space to 1KB granularity\n");
                 dev->io_window_1k = 1;
         }
 }
@@ -2126,7 +2123,7 @@ static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
         if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
                 if (!(b & 0x20)) {
                         pci_write_config_byte(dev, 0xf41, b | 0x20);
-                        dev_info(&dev->dev, "Linking AER extended capability\n");
+                        pci_info(dev, "Linking AER extended capability\n");
                 }
         }
 }
@@ -2164,7 +2161,7 @@ static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
                         /* Turn off PCI Bus Parking */
                         pci_write_config_byte(dev, 0x76, b ^ 0x40);
 
-                        dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n");
+                        pci_info(dev, "Disabling VIA CX700 PCI parking\n");
                 }
         }
 
@@ -2179,7 +2176,7 @@ static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
                         /* Disable "Read FIFO Timer" */
                         pci_write_config_byte(dev, 0x77, 0x0);
 
-                        dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n");
+                        pci_info(dev, "Disabling VIA CX700 PCI caching\n");
                 }
         }
 }
@@ -2196,7 +2193,7 @@ static void quirk_blacklist_vpd(struct pci_dev *dev)
 {
         if (dev->vpd) {
                 dev->vpd->len = 0;
-                dev_warn(&dev->dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
+                pci_warn(dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
         }
 }
 
@@ -2312,7 +2309,7 @@ static void quirk_unhide_mch_dev6(struct pci_dev *dev)
         u8 reg;
 
         if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
-                dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
+                pci_info(dev, "Enabling MCH 'Overflow' Device\n");
                 pci_write_config_byte(dev, 0xF4, reg | 0x02);
         }
 }
@@ -2351,7 +2348,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
 static void quirk_disable_all_msi(struct pci_dev *dev)
 {
         pci_no_msi();
-        dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
+        pci_warn(dev, "MSI quirk detected; MSI disabled\n");
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
@@ -2366,7 +2363,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
 static void quirk_disable_msi(struct pci_dev *dev)
 {
         if (dev->subordinate) {
-                dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
+                pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
                 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
         }
 }
@@ -2406,7 +2403,7 @@ static int msi_ht_cap_enabled(struct pci_dev *dev)
 
                 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
                                          &flags) == 0) {
-                        dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
+                        pci_info(dev, "Found %s HT MSI Mapping\n",
                                 flags & HT_MSI_FLAGS_ENABLE ?
                                 "enabled" : "disabled");
                         return (flags & HT_MSI_FLAGS_ENABLE) != 0;
@@ -2422,7 +2419,7 @@ static int msi_ht_cap_enabled(struct pci_dev *dev)
 static void quirk_msi_ht_cap(struct pci_dev *dev)
 {
         if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
-                dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
+                pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
                 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
         }
 }
@@ -2446,7 +2443,7 @@ static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
         if (!pdev)
                 return;
         if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
-                dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
+                pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
                 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
         }
         pci_dev_put(pdev);
@@ -2465,7 +2462,7 @@ static void ht_enable_msi_mapping(struct pci_dev *dev)
 
                 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
                                          &flags) == 0) {
-                        dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
+                        pci_info(dev, "Enabling HT MSI Mapping\n");
 
                         pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
                                               flags | HT_MSI_FLAGS_ENABLE);
@@ -2492,7 +2489,7 @@ static void nvenet_msi_disable(struct pci_dev *dev)
         if (board_name &&
             (strstr(board_name, "P5N32-SLI PREMIUM") ||
              strstr(board_name, "P5N32-E SLI"))) {
-                dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
+                pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
                 dev->no_msi = 1;
         }
 }
@@ -2669,7 +2666,7 @@ static void ht_disable_msi_mapping(struct pci_dev *dev)
 
                 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
                                          &flags) == 0) {
-                        dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
+                        pci_info(dev, "Disabling HT MSI Mapping\n");
 
                         pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
                                               flags & ~HT_MSI_FLAGS_ENABLE);
@@ -2699,9 +2696,10 @@ static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
          * HT MSI mapping should be disabled on devices that are below
          * a non-Hypertransport host bridge. Locate the host bridge...
          */
-        host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
+        host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
+                                                  PCI_DEVFN(0, 0));
         if (host_bridge == NULL) {
-                dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
+                pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
                 return;
         }
 
@@ -2770,7 +2768,7 @@ static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
 {
         /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
         if (dev->revision < 0x18) {
-                dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
+                pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
                 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
         }
 }
@@ -2899,8 +2897,8 @@ static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
         pci_write_config_byte(dev, 0x8E, write_enable);
         pci_write_config_byte(dev, 0x8D, write_target);
 
-        dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
-        dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
+        pci_notice(dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
+        pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
@@ -2935,7 +2933,7 @@ static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
                 pci_write_config_byte(dev, 0xe1, 0x32);
                 pci_write_config_byte(dev, 0xfc, 0x00);
 
-                dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
+                pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
         }
 
         pci_read_config_byte(dev, 0xCB, &disable);
@@ -2948,8 +2946,8 @@ static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
         pci_write_config_byte(dev, 0xCB, disable | 0x02);
         pci_write_config_byte(dev, 0xCA, write_enable);
 
-        dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
-        dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
+        pci_notice(dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
+        pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
 
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
@@ -2990,7 +2988,7 @@ static void fixup_ti816x_class(struct pci_dev *dev)
 
         /* TI 816x devices do not have class code set when in PCIe boot mode */
         dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
-        dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
+        pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
                  class, dev->class);
 }
 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
@@ -3032,7 +3030,7 @@ static void quirk_intel_mc_errata(struct pci_dev *dev)
          */
         err = pci_read_config_word(dev, 0x48, &rcc);
         if (err) {
-                dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n");
+                pci_err(dev, "Error attempting to read the read completion coalescing register\n");
                 return;
         }
 
@@ -3043,7 +3041,7 @@ static void quirk_intel_mc_errata(struct pci_dev *dev)
 
         err = pci_write_config_word(dev, 0x48, rcc);
         if (err) {
-                dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n");
+                pci_err(dev, "Error attempting to write the read completion coalescing register\n");
                 return;
         }
 
@@ -3108,7 +3106,7 @@ static ktime_t fixup_debug_start(struct pci_dev *dev,
 {
         ktime_t calltime = 0;
 
-        dev_dbg(&dev->dev, "calling %pF\n", fn);
+        pci_dbg(dev, "calling %pF\n", fn);
         if (initcall_debug) {
                 pr_debug("calling  %pF @ %i for %s\n",
                          fn, task_pid_nr(current), dev_name(&dev->dev));
@@ -3150,13 +3148,13 @@ static void disable_igfx_irq(struct pci_dev *dev)
 {
         void __iomem *regs = pci_iomap(dev, 0, 0);
         if (regs == NULL) {
-                dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
+                pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
                 return;
         }
 
         /* Check if any interrupt line is still enabled */
         if (readl(regs + I915_DEIER_REG) != 0) {
-                dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
+                pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
 
                 writel(0, regs + I915_DEIER_REG);
         }
@@ -3215,6 +3213,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
                         quirk_broken_intx_masking);
 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
                         quirk_broken_intx_masking);
+DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
+                        quirk_broken_intx_masking);
 
 /*
  * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
@@ -3317,13 +3317,13 @@ static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
 
         /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
         if (pci_enable_device_mem(pdev)) {
-                dev_warn(&pdev->dev, "Can't enable device memory\n");
+                pci_warn(pdev, "Can't enable device memory\n");
                 return;
         }
 
         fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
         if (!fw_ver) {
-                dev_warn(&pdev->dev, "Can't map ConnectX-4 initialization segment\n");
+                pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
                 goto out;
         }
 
@@ -3335,7 +3335,7 @@ static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
         fw_subminor = fw_sub_min & 0xffff;
         if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
             fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
-                dev_warn(&pdev->dev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
+                pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
                          fw_major, fw_minor, fw_subminor, pdev->device ==
                          PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
                 pdev->broken_intx_masking = 1;
@@ -3473,7 +3473,7 @@ static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
             || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
             || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
                 return;
-        dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n");
+        pci_info(dev, "quirk: cutting power to thunderbolt controller...\n");
 
         /* magic sequence */
         acpi_execute_simple_method(SXIO, NULL, 1);
@@ -3524,7 +3524,7 @@ static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
                         nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
                     || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
                 goto out;
-        dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
+        pci_info(dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
         device_pm_wait_for_dev(&dev->dev, &nhi->dev);
 out:
         pci_dev_put(nhi);
@@ -3740,7 +3740,7 @@ static int reset_ivb_igd(struct pci_dev *dev, int probe)
                         goto reset_complete;
                 msleep(10);
         } while (time_before(jiffies, timeout));
-        dev_warn(&dev->dev, "timeout during reset\n");
+        pci_warn(dev, "timeout during reset\n");
 
 reset_complete:
         iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
@@ -3879,6 +3879,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
                          quirk_dma_func1_alias);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
                          quirk_dma_func1_alias);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
+                         quirk_dma_func1_alias);
 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
                          quirk_dma_func1_alias);
@@ -4012,7 +4014,7 @@ static void quirk_tw686x_class(struct pci_dev *pdev)
 
         /* Use "Multimedia controller" class */
         pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
-        dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
+        pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
                  class, pdev->class);
 }
 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
@@ -4032,7 +4034,7 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
 static void quirk_relaxedordering_disable(struct pci_dev *dev)
 {
         dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
-        dev_info(&dev->dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
+        pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
 }
 
 /*
@@ -4141,11 +4143,11 @@ static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
         struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
 
         if (!root_port) {
-                dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n");
+                pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
                 return;
         }
 
-        dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
+        pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
                  dev_name(&pdev->dev));
         pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
                                            PCI_EXP_DEVCTL_RELAX_EN |
@@ -4339,7 +4341,7 @@ static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
         u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
         int ret = acs_flags & ~flags ? 0 : 1;
 
-        dev_info(&dev->dev, "Using QCOM ACS Quirk (%d)\n", ret);
+        pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret);
 
         return ret;
 }
@@ -4591,7 +4593,7 @@ static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
         if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
                 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
                 if (updcr & INTEL_UPDCR_REG_MASK) {
-                        dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
+                        pci_info(dev, "Disabling UPDCR peer decodes\n");
                         updcr &= ~INTEL_UPDCR_REG_MASK;
                         writel(updcr, rcba_mem + INTEL_UPDCR_REG);
                 }
@@ -4618,7 +4620,7 @@ static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
          */
         pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
         if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
-                dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
+                pci_info(dev, "Enabling MPC IRBNCE\n");
                 mpc |= INTEL_MPC_REG_IRBNCE;
                 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
         }
@@ -4630,7 +4632,7 @@ static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
                 return -ENOTTY;
 
         if (pci_quirk_enable_intel_lpc_acs(dev)) {
-                dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
+                pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
                 return 0;
         }
 
@@ -4638,7 +4640,7 @@ static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
 
         dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
 
-        dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
+        pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
 
         return 0;
 }
@@ -4665,7 +4667,7 @@ static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
 
         pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
 
-        dev_info(&dev->dev, "Intel SPT PCH root port ACS workaround enabled\n");
+        pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
 
         return 0;
 }
@@ -4800,7 +4802,7 @@ static void quirk_no_ext_tags(struct pci_dev *pdev)
                 return;
 
         bridge->no_ext_tags = 1;
-        dev_info(&pdev->dev, "disabling Extended Tags (this device can't handle them)\n");
+        pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
 
         pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
 }
@@ -4815,7 +4817,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
  */
 static void quirk_no_ats(struct pci_dev *pdev)
 {
-        dev_info(&pdev->dev, "disabling ATS (broken on this device)\n");
+        pci_info(pdev, "disabling ATS (broken on this device)\n");
         pdev->ats_cap = 0;
 }
 
diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c
index 2fa0dbde36b7..6f072eae4f7a 100644
--- a/drivers/pci/remove.c
+++ b/drivers/pci/remove.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 #include <linux/pci.h>
 #include <linux/module.h>
 #include <linux/pci-aspm.h>
diff --git a/drivers/pci/rom.c b/drivers/pci/rom.c
index 1f5e6af96c83..374a33443be9 100644
--- a/drivers/pci/rom.c
+++ b/drivers/pci/rom.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * drivers/pci/rom.c
  *
@@ -92,15 +93,15 @@ size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size)
                 void __iomem *pds;
                 /* Standard PCI ROMs start out with these bytes 55 AA */
                 if (readw(image) != 0xAA55) {
-                        dev_err(&pdev->dev, "Invalid PCI ROM header signature: expecting 0xaa55, got %#06x\n",
-                                readw(image));
+                        pci_info(pdev, "Invalid PCI ROM header signature: expecting 0xaa55, got %#06x\n",
+                                 readw(image));
                         break;
                 }
                 /* get the PCI data structure and check its "PCIR" signature */
                 pds = image + readw(image + 24);
                 if (readl(pds) != 0x52494350) {
-                        dev_err(&pdev->dev, "Invalid PCI ROM data signature: expecting 0x52494350, got %#010x\n",
-                                readl(pds));
+                        pci_info(pdev, "Invalid PCI ROM data signature: expecting 0x52494350, got %#010x\n",
+                                 readl(pds));
                         break;
                 }
                 last_image = readb(pds + 21) & 0x80;
diff --git a/drivers/pci/search.c b/drivers/pci/search.c
index 4c6044ad7368..bc1e023f1353 100644
--- a/drivers/pci/search.c
+++ b/drivers/pci/search.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  *      PCI searching functions.
  *
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index b1ad466199ad..3cce29a069e6 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  *      drivers/pci/setup-bus.c
  *
@@ -67,10 +68,8 @@ static int add_to_list(struct list_head *head,
         struct pci_dev_resource *tmp;
 
         tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
-        if (!tmp) {
-                pr_warn("add_to_list: kmalloc() failed!\n");
+        if (!tmp)
                 return -ENOMEM;
-        }
 
         tmp->res = res;
         tmp->dev = dev;
@@ -152,7 +151,7 @@ static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
 
                 r_align = pci_resource_alignment(dev, r);
                 if (!r_align) {
-                        dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
+                        pci_warn(dev, "BAR %d: %pR has bogus alignment\n",
                                  i, r);
                         continue;
                 }
@@ -260,7 +259,7 @@ static void reassign_resources_sorted(struct list_head *realloc_head,
                                  (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
                         if (pci_reassign_resource(add_res->dev, idx,
                                                   add_size, align))
-                                dev_printk(KERN_DEBUG, &add_res->dev->dev,
+                                pci_printk(KERN_DEBUG, add_res->dev,
                                            "failed to add %llx res[%d]=%pR\n",
                                            (unsigned long long)add_size,
                                            idx, res);
@@ -519,7 +518,7 @@ void pci_setup_cardbus(struct pci_bus *bus)
         struct resource *res;
         struct pci_bus_region region;
 
-        dev_info(&bridge->dev, "CardBus bridge to %pR\n",
+        pci_info(bridge, "CardBus bridge to %pR\n",
                  &bus->busn_res);
 
         res = bus->resource[0];
@@ -529,7 +528,7 @@ void pci_setup_cardbus(struct pci_bus *bus)
                  * The IO resource is allocated a range twice as large as it
                  * would normally need.  This allows us to set both IO regs.
                  */
-                dev_info(&bridge->dev, "  bridge window %pR\n", res);
+                pci_info(bridge, "  bridge window %pR\n", res);
                 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
                                         region.start);
                 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
@@ -539,7 +538,7 @@ void pci_setup_cardbus(struct pci_bus *bus)
         res = bus->resource[1];
         pcibios_resource_to_bus(bridge->bus, &region, res);
         if (res->flags & IORESOURCE_IO) {
-                dev_info(&bridge->dev, "  bridge window %pR\n", res);
+                pci_info(bridge, "  bridge window %pR\n", res);
                 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
                                         region.start);
                 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
@@ -549,7 +548,7 @@ void pci_setup_cardbus(struct pci_bus *bus)
         res = bus->resource[2];
         pcibios_resource_to_bus(bridge->bus, &region, res);
         if (res->flags & IORESOURCE_MEM) {
-                dev_info(&bridge->dev, "  bridge window %pR\n", res);
+                pci_info(bridge, "  bridge window %pR\n", res);
                 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
                                         region.start);
                 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
@@ -559,7 +558,7 @@ void pci_setup_cardbus(struct pci_bus *bus)
         res = bus->resource[3];
         pcibios_resource_to_bus(bridge->bus, &region, res);
         if (res->flags & IORESOURCE_MEM) {
-                dev_info(&bridge->dev, "  bridge window %pR\n", res);
+                pci_info(bridge, "  bridge window %pR\n", res);
                 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
                                         region.start);
                 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
@@ -602,7 +601,7 @@ static void pci_setup_bridge_io(struct pci_dev *bridge)
                 l = ((u16) io_limit_lo << 8) | io_base_lo;
                 /* Set up upper 16 bits of I/O base/limit. */
                 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
-                dev_info(&bridge->dev, "  bridge window %pR\n", res);
+                pci_info(bridge, "  bridge window %pR\n", res);
         } else {
                 /* Clear upper 16 bits of I/O base/limit. */
                 io_upper16 = 0;
@@ -628,7 +627,7 @@ static void pci_setup_bridge_mmio(struct pci_dev *bridge)
         if (res->flags & IORESOURCE_MEM) {
                 l = (region.start >> 16) & 0xfff0;
                 l |= region.end & 0xfff00000;
-                dev_info(&bridge->dev, "  bridge window %pR\n", res);
+                pci_info(bridge, "  bridge window %pR\n", res);
         } else {
                 l = 0x0000fff0;
         }
@@ -657,7 +656,7 @@ static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
                         bu = upper_32_bits(region.start);
                         lu = upper_32_bits(region.end);
                 }
-                dev_info(&bridge->dev, "  bridge window %pR\n", res);
+                pci_info(bridge, "  bridge window %pR\n", res);
         } else {
                 l = 0x0000fff0;
         }
@@ -672,7 +671,7 @@ static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
 {
         struct pci_dev *bridge = bus->self;
 
-        dev_info(&bridge->dev, "PCI bridge to %pR\n",
+        pci_info(bridge, "PCI bridge to %pR\n",
                  &bus->busn_res);
 
         if (type & IORESOURCE_IO)
@@ -944,7 +943,7 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
                         resource_size(b_res), min_align);
         if (!size0 && !size1) {
                 if (b_res->start || b_res->end)
-                        dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n",
+                        pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
                                  b_res, &bus->busn_res);
                 b_res->flags = 0;
                 return;
@@ -956,7 +955,7 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
         if (size1 > size0 && realloc_head) {
                 add_to_list(realloc_head, bus->self, b_res, size1-size0,
                             min_align);
-                dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx\n",
+                pci_printk(KERN_DEBUG, bus->self, "bridge window %pR to %pR add_size %llx\n",
                            b_res, &bus->busn_res,
                            (unsigned long long)size1-size0);
         }
@@ -1061,7 +1060,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
                         if (order < 0)
                                 order = 0;
                         if (order >= ARRAY_SIZE(aligns)) {
-                                dev_warn(&dev->dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
+                                pci_warn(dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
                                          i, r, (unsigned long long) align);
                                 r->flags = 0;
                                 continue;
@@ -1093,7 +1092,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
                                 resource_size(b_res), add_align);
         if (!size0 && !size1) {
                 if (b_res->start || b_res->end)
-                        dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n",
+                        pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
                                  b_res, &bus->busn_res);
                 b_res->flags = 0;
                 return 0;
@@ -1103,7 +1102,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
         b_res->flags |= IORESOURCE_STARTALIGN;
         if (size1 > size0 && realloc_head) {
                 add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
-                dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx add_align %llx\n",
+                pci_printk(KERN_DEBUG, bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n",
                            b_res, &bus->busn_res,
                            (unsigned long long) (size1 - size0),
                            (unsigned long long) add_align);
@@ -1407,7 +1406,7 @@ void __pci_bus_assign_resources(const struct pci_bus *bus,
                         break;
 
                 default:
-                        dev_info(&dev->dev, "not setting up bridge for bus %04x:%02x\n",
+                        pci_info(dev, "not setting up bridge for bus %04x:%02x\n",
                                  pci_domain_nr(b), b->number);
                         break;
                 }
@@ -1513,7 +1512,7 @@ static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
                 break;
 
         default:
-                dev_info(&bridge->dev, "not setting up bridge for bus %04x:%02x\n",
+                pci_info(bridge, "not setting up bridge for bus %04x:%02x\n",
                          pci_domain_nr(b), b->number);
                 break;
         }
@@ -1571,7 +1570,7 @@ static void pci_bridge_release_resources(struct pci_bus *bus,
         release_child_resources(r);
         if (!release_resource(r)) {
                 type = old_flags = r->flags & PCI_RES_TYPE_MASK;
-                dev_printk(KERN_DEBUG, &dev->dev, "resource %d %pR released\n",
+                pci_printk(KERN_DEBUG, dev, "resource %d %pR released\n",
                                         PCI_BRIDGE_RESOURCES + idx, r);
                 /* keep the old size */
                 r->end = resource_size(r) - 1;
@@ -1874,7 +1873,7 @@ static void extend_bridge_window(struct pci_dev *bridge, struct resource *res,
                 return;
 
         dev_res->add_size = available - resource_size(res);
-        dev_dbg(&bridge->dev, "bridge window %pR extended by %pa\n", res,
+        pci_dbg(bridge, "bridge window %pR extended by %pa\n", res,
                 &dev_res->add_size);
 }
 
@@ -2085,7 +2084,7 @@ again:
 enable_all:
         retval = pci_reenable_device(bridge);
         if (retval)
-                dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval);
+                pci_err(bridge, "Error reenabling bridge (%d)\n", retval);
         pci_set_master(bridge);
 }
 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
@@ -2119,7 +2118,7 @@ int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
                         if (ret)
                                 goto cleanup;
 
-                        dev_info(&bridge->dev, "BAR %d: releasing %pR\n",
+                        pci_info(bridge, "BAR %d: releasing %pR\n",
                                  i, res);
 
                         if (res->parent)
diff --git a/drivers/pci/setup-irq.c b/drivers/pci/setup-irq.c
index 86106c44ce94..5ad4ee7d7b1e 100644
--- a/drivers/pci/setup-irq.c
+++ b/drivers/pci/setup-irq.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  *      drivers/pci/setup-irq.c
  *
@@ -25,7 +26,7 @@ void pci_assign_irq(struct pci_dev *dev)
         struct pci_host_bridge *hbrg = pci_find_host_bridge(dev->bus);
 
         if (!(hbrg->map_irq)) {
-                dev_dbg(&dev->dev, "runtime IRQ mapping not provided by arch\n");
+                pci_dbg(dev, "runtime IRQ mapping not provided by arch\n");
                 return;
         }
 
@@ -55,7 +56,7 @@ void pci_assign_irq(struct pci_dev *dev)
         }
         dev->irq = irq;
 
-        dev_dbg(&dev->dev, "assign IRQ: got %d\n", dev->irq);
+        pci_dbg(dev, "assign IRQ: got %d\n", dev->irq);
 
         /* Always tell the device, so the driver knows what is
            the real IRQ to use; the device does not use it. */
diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
index e815111f3f81..369d48d6c6f1 100644
--- a/drivers/pci/setup-res.c
+++ b/drivers/pci/setup-res.c
@@ -103,7 +103,7 @@ static void pci_std_update_resource(struct pci_dev *dev, int resno)
         pci_read_config_dword(dev, reg, &check);
 
         if ((new ^ check) & mask) {
-                dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
+                pci_err(dev, "BAR %d: error updating (%#08x != %#08x)\n",
                         resno, new, check);
         }
 
@@ -112,7 +112,7 @@ static void pci_std_update_resource(struct pci_dev *dev, int resno)
                 pci_write_config_dword(dev, reg + 4, new);
                 pci_read_config_dword(dev, reg + 4, &check);
                 if (check != new) {
-                        dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n",
+                        pci_err(dev, "BAR %d: error updating (high %#08x != %#08x)\n",
                                 resno, new, check);
                 }
         }
@@ -137,7 +137,7 @@ int pci_claim_resource(struct pci_dev *dev, int resource)
         struct resource *root, *conflict;
 
         if (res->flags & IORESOURCE_UNSET) {
-                dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
+                pci_info(dev, "can't claim BAR %d %pR: no address assigned\n",
                          resource, res);
                 return -EINVAL;
         }
@@ -152,7 +152,7 @@ int pci_claim_resource(struct pci_dev *dev, int resource)
 
         root = pci_find_parent_resource(dev, res);
         if (!root) {
-                dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
+                pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n",
                          resource, res);
                 res->flags |= IORESOURCE_UNSET;
                 return -EINVAL;
@@ -160,7 +160,7 @@ int pci_claim_resource(struct pci_dev *dev, int resource)
 
         conflict = request_resource_conflict(root, res);
         if (conflict) {
-                dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
+                pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
                          resource, res, conflict->name, conflict);
                 res->flags |= IORESOURCE_UNSET;
                 return -EBUSY;
@@ -172,7 +172,7 @@ EXPORT_SYMBOL(pci_claim_resource);
 
 void pci_disable_bridge_window(struct pci_dev *dev)
 {
-        dev_info(&dev->dev, "disabling bridge mem windows\n");
+        pci_info(dev, "disabling bridge mem windows\n");
 
         /* MMIO Base/Limit */
         pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
@@ -221,11 +221,11 @@ static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
                         root = &iomem_resource;
         }
 
-        dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
+        pci_info(dev, "BAR %d: trying firmware assignment %pR\n",
                  resno, res);
         conflict = request_resource_conflict(root, res);
         if (conflict) {
-                dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n",
+                pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n",
                          resno, res, conflict->name, conflict);
                 res->start = start;
                 res->end = end;
@@ -324,7 +324,7 @@ int pci_assign_resource(struct pci_dev *dev, int resno)
         res->flags |= IORESOURCE_UNSET;
         align = pci_resource_alignment(dev, res);
         if (!align) {
-                dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n",
+                pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n",
                          resno, res);
                 return -EINVAL;
         }
@@ -338,19 +338,18 @@ int pci_assign_resource(struct pci_dev *dev, int resno)
          * working, which is better than just leaving it disabled.
          */
         if (ret < 0) {
-                dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res);
+                pci_info(dev, "BAR %d: no space for %pR\n", resno, res);
                 ret = pci_revert_fw_address(res, dev, resno, size);
         }
 
         if (ret < 0) {
-                dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno,
-                         res);
+                pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res);
                 return ret;
         }
 
         res->flags &= ~IORESOURCE_UNSET;
         res->flags &= ~IORESOURCE_STARTALIGN;
-        dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
+        pci_info(dev, "BAR %d: assigned %pR\n", resno, res);
         if (resno < PCI_BRIDGE_RESOURCES)
                 pci_update_resource(dev, resno);
 
@@ -372,7 +371,7 @@ int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsiz
         flags = res->flags;
         res->flags |= IORESOURCE_UNSET;
         if (!res->parent) {
-                dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n",
+                pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n",
                          resno, res);
                 return -EINVAL;
         }
@@ -382,14 +381,14 @@ int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsiz
         ret = _pci_assign_resource(dev, resno, new_size, min_align);
         if (ret) {
                 res->flags = flags;
-                dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n",
+                pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n",
                          resno, res, (unsigned long long) addsize);
                 return ret;
         }
 
         res->flags &= ~IORESOURCE_UNSET;
         res->flags &= ~IORESOURCE_STARTALIGN;
-        dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
+        pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
                  resno, res, (unsigned long long) addsize);
         if (resno < PCI_BRIDGE_RESOURCES)
                 pci_update_resource(dev, resno);
@@ -401,7 +400,7 @@ void pci_release_resource(struct pci_dev *dev, int resno)
 {
         struct resource *res = dev->resource + resno;
 
-        dev_info(&dev->dev, "BAR %d: releasing %pR\n", resno, res);
+        pci_info(dev, "BAR %d: releasing %pR\n", resno, res);
         release_resource(res);
         res->end = resource_size(res) - 1;
         res->start = 0;
@@ -477,13 +476,13 @@ int pci_enable_resources(struct pci_dev *dev, int mask)
                         continue;
 
                 if (r->flags & IORESOURCE_UNSET) {
-                        dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
+                        pci_err(dev, "can't enable device: BAR %d %pR not assigned\n",
                                 i, r);
                         return -EINVAL;
                 }
 
                 if (!r->parent) {
-                        dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
+                        pci_err(dev, "can't enable device: BAR %d %pR not claimed\n",
                                 i, r);
                         return -EINVAL;
                 }
@@ -495,8 +494,7 @@ int pci_enable_resources(struct pci_dev *dev, int mask)
         }
 
         if (cmd != old_cmd) {
-                dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
-                         old_cmd, cmd);
+                pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
                 pci_write_config_word(dev, PCI_COMMAND, cmd);
         }
         return 0;
diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c
index e42909524dee..d10f556dc03e 100644
--- a/drivers/pci/slot.c
+++ b/drivers/pci/slot.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * drivers/pci/slot.c
  * Copyright (C) 2006 Matthew Wilcox <matthew@wil.cx>
diff --git a/drivers/pci/switch/Kconfig b/drivers/pci/switch/Kconfig
index 4c49648e0646..aee28a5bb98f 100644
--- a/drivers/pci/switch/Kconfig
+++ b/drivers/pci/switch/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
 menu "PCI switch controller drivers"
         depends on PCI
 
diff --git a/drivers/pci/switch/Makefile b/drivers/pci/switch/Makefile
index 37d8cfb03f3f..acd56d3b4a35 100644
--- a/drivers/pci/switch/Makefile
+++ b/drivers/pci/switch/Makefile
@@ -1 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_PCI_SW_SWITCHTEC) += switchtec.o
diff --git a/drivers/pci/switch/switchtec.c b/drivers/pci/switch/switchtec.c
index 730cc897b94d..a60c0ab7883d 100644
--- a/drivers/pci/switch/switchtec.c
+++ b/drivers/pci/switch/switchtec.c
@@ -1,16 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Microsemi Switchtec(tm) PCIe Management Driver
  * Copyright (c) 2017, Microsemi Corporation
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
  */
 
 #include <linux/switchtec.h>
@@ -510,11 +501,11 @@ out:
                 return -EBADMSG;
 }
 
-static unsigned int switchtec_dev_poll(struct file *filp, poll_table *wait)
+static __poll_t switchtec_dev_poll(struct file *filp, poll_table *wait)
 {
         struct switchtec_user *stuser = filp->private_data;
         struct switchtec_dev *stdev = stuser->stdev;
-        int ret = 0;
+        __poll_t ret = 0;
 
         poll_wait(filp, &stuser->comp.wait, wait);
         poll_wait(filp, &stdev->event_wq, wait);
@@ -707,6 +698,7 @@ static const struct event_reg {
         EV_GLB(SWITCHTEC_IOCTL_EVENT_CLI_MRPC_COMP_ASYNC,
                cli_mrpc_comp_async_hdr),
         EV_GLB(SWITCHTEC_IOCTL_EVENT_GPIO_INT, gpio_interrupt_hdr),
+        EV_GLB(SWITCHTEC_IOCTL_EVENT_GFMS, gfms_event_hdr),
         EV_PAR(SWITCHTEC_IOCTL_EVENT_PART_RESET, part_reset_hdr),
         EV_PAR(SWITCHTEC_IOCTL_EVENT_MRPC_COMP, mrpc_comp_hdr),
         EV_PAR(SWITCHTEC_IOCTL_EVENT_MRPC_COMP_ASYNC, mrpc_comp_async_hdr),
@@ -1352,6 +1344,8 @@ static const struct pci_device_id switchtec_pci_tbl[] = {
         SWITCHTEC_PCI_DEVICE(0x8534),  //PFX 64xG3
         SWITCHTEC_PCI_DEVICE(0x8535),  //PFX 80xG3
         SWITCHTEC_PCI_DEVICE(0x8536),  //PFX 96xG3
+        SWITCHTEC_PCI_DEVICE(0x8541),  //PSX 24xG3
+        SWITCHTEC_PCI_DEVICE(0x8542),  //PSX 32xG3
         SWITCHTEC_PCI_DEVICE(0x8543),  //PSX 48xG3
         SWITCHTEC_PCI_DEVICE(0x8544),  //PSX 64xG3
         SWITCHTEC_PCI_DEVICE(0x8545),  //PSX 80xG3
diff --git a/drivers/pci/syscall.c b/drivers/pci/syscall.c
index 83efa001c2e7..e725f99b5479 100644
--- a/drivers/pci/syscall.c
+++ b/drivers/pci/syscall.c
@@ -28,7 +28,7 @@ SYSCALL_DEFINE5(pciconfig_read, unsigned long, bus, unsigned long, dfn,
                 return -EPERM;
 
         err = -ENODEV;
-        dev = pci_get_bus_and_slot(bus, dfn);
+        dev = pci_get_domain_bus_and_slot(0, bus, dfn);
         if (!dev)
                 goto error;
 
@@ -96,7 +96,7 @@ SYSCALL_DEFINE5(pciconfig_write, unsigned long, bus, unsigned long, dfn,
         if (!capable(CAP_SYS_ADMIN))
                 return -EPERM;
 
-        dev = pci_get_bus_and_slot(bus, dfn);
+        dev = pci_get_domain_bus_and_slot(0, bus, dfn);
         if (!dev)
                 return -ENODEV;
 
diff --git a/drivers/pci/vc.c b/drivers/pci/vc.c
index 1fa3a3219c45..5acd9c02683a 100644
--- a/drivers/pci/vc.c
+++ b/drivers/pci/vc.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * PCI Virtual Channel support
  *
  * Copyright (C) 2013 Red Hat, Inc.  All rights reserved.
  *     Author: Alex Williamson <alex.williamson@redhat.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include <linux/device.h>
@@ -57,7 +54,7 @@ static void pci_vc_load_arb_table(struct pci_dev *dev, int pos)
                                  PCI_VC_PORT_STATUS_TABLE))
                 return;
 
-        dev_err(&dev->dev, "VC arbitration table failed to load\n");
+        pci_err(dev, "VC arbitration table failed to load\n");
 }
 
 /**
@@ -85,7 +82,7 @@ static void pci_vc_load_port_arb_table(struct pci_dev *dev, int pos, int res)
         if (pci_wait_for_pending(dev, status_pos, PCI_VC_RES_STATUS_TABLE))
                 return;
 
-        dev_err(&dev->dev, "VC%d port arbitration table failed to load\n", res);
+        pci_err(dev, "VC%d port arbitration table failed to load\n", res);
 }
 
 /**
@@ -161,11 +158,11 @@ enable:
         pci_write_config_dword(dev, ctrl_pos, ctrl);
 
         if (!pci_wait_for_pending(dev, status_pos, PCI_VC_RES_STATUS_NEGO))
-                dev_err(&dev->dev, "VC%d negotiation stuck pending\n", id);
+                pci_err(dev, "VC%d negotiation stuck pending\n", id);
 
         if (link && !pci_wait_for_pending(link, status_pos2,
                                           PCI_VC_RES_STATUS_NEGO))
-                dev_err(&link->dev, "VC%d negotiation stuck pending\n", id);
+                pci_err(link, "VC%d negotiation stuck pending\n", id);
 }
 
 /**
@@ -195,8 +192,7 @@ static int pci_vc_do_save_buffer(struct pci_dev *dev, int pos,
         /* Sanity check buffer size for save/restore */
         if (buf && save_state->cap.size !=
             pci_vc_do_save_buffer(dev, pos, NULL, save)) {
-                dev_err(&dev->dev,
-                        "VC save buffer size does not match @0x%x\n", pos);
+                pci_err(dev, "VC save buffer size does not match @0x%x\n", pos);
                 return -ENOMEM;
         }
 
@@ -366,14 +362,14 @@ int pci_save_vc_state(struct pci_dev *dev)
 
                 save_state = pci_find_saved_ext_cap(dev, vc_caps[i].id);
                 if (!save_state) {
-                        dev_err(&dev->dev, "%s buffer not found in %s\n",
+                        pci_err(dev, "%s buffer not found in %s\n",
                                 vc_caps[i].name, __func__);
                         return -ENOMEM;
                 }
 
                 ret = pci_vc_do_save_buffer(dev, pos, save_state, true);
                 if (ret) {
-                        dev_err(&dev->dev, "%s save unsuccessful %s\n",
+                        pci_err(dev, "%s save unsuccessful %s\n",
                                 vc_caps[i].name, __func__);
                         return ret;
                 }
@@ -426,8 +422,7 @@ void pci_allocate_vc_save_buffers(struct pci_dev *dev)
 
                 len = pci_vc_do_save_buffer(dev, pos, NULL, false);
                 if (pci_add_ext_cap_save_buffer(dev, vc_caps[i].id, len))
-                        dev_err(&dev->dev,
-                                "unable to preallocate %s save buffer\n",
+                        pci_err(dev, "unable to preallocate %s save buffer\n",
                                 vc_caps[i].name);
         }
 }
diff --git a/drivers/pci/vpd.c b/drivers/pci/vpd.c
index 39b79070335d..70fba57d6103 100644
--- a/drivers/pci/vpd.c
+++ b/drivers/pci/vpd.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * File:        vpd.c
  * Purpose:     Provide PCI VPD support
diff --git a/drivers/pci/xen-pcifront.c b/drivers/pci/xen-pcifront.c
index 8fc2e9532575..8785014f656e 100644
--- a/drivers/pci/xen-pcifront.c
+++ b/drivers/pci/xen-pcifront.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Xen PCI Frontend.
  *
@@ -261,8 +262,8 @@ static int pci_frontend_enable_msix(struct pci_dev *dev,
         struct msi_desc *entry;
 
         if (nvec > SH_INFO_MAX_VEC) {
-                dev_err(&dev->dev, "too much vector for pci frontend: %x."
-                                   " Increase SH_INFO_MAX_VEC.\n", nvec);
+                pci_err(dev, "too many vectors (0x%x) for PCI frontend:"
+                                   " Increase SH_INFO_MAX_VEC\n", nvec);
                 return -EINVAL;
         }
 
@@ -281,7 +282,7 @@ static int pci_frontend_enable_msix(struct pci_dev *dev,
                         /* we get the result */
                         for (i = 0; i < nvec; i++) {
                                 if (op.msix_entries[i].vector <= 0) {
-                                        dev_warn(&dev->dev, "MSI-X entry %d is invalid: %d!\n",
+                                        pci_warn(dev, "MSI-X entry %d is invalid: %d!\n",
                                                 i, op.msix_entries[i].vector);
                                         err = -EINVAL;
                                         vector[i] = -1;
@@ -295,7 +296,7 @@ static int pci_frontend_enable_msix(struct pci_dev *dev,
                         err = op.value;
                 }
         } else {
-                dev_err(&dev->dev, "enable msix get err %x\n", err);
+                pci_err(dev, "enable msix get err %x\n", err);
         }
         return err;
 }
@@ -316,7 +317,7 @@ static void pci_frontend_disable_msix(struct pci_dev *dev)
 
         /* What should do for error ? */
         if (err)
-                dev_err(&dev->dev, "pci_disable_msix get err %x\n", err);
+                pci_err(dev, "pci_disable_msix get err %x\n", err);
 }
 
 static int pci_frontend_enable_msi(struct pci_dev *dev, int vector[])
@@ -335,13 +336,13 @@ static int pci_frontend_enable_msi(struct pci_dev *dev, int vector[])
         if (likely(!err)) {
                 vector[0] = op.value;
                 if (op.value <= 0) {
-                        dev_warn(&dev->dev, "MSI entry is invalid: %d!\n",
+                        pci_warn(dev, "MSI entry is invalid: %d!\n",
                                 op.value);
                         err = -EINVAL;
                         vector[0] = -1;
                 }
         } else {
-                dev_err(&dev->dev, "pci frontend enable msi failed for dev "
+                pci_err(dev, "pci frontend enable msi failed for dev "
                                     "%x:%x\n", op.bus, op.devfn);
                 err = -EINVAL;
         }
@@ -560,7 +561,7 @@ static void free_root_bus_devs(struct pci_bus *bus)
         while (!list_empty(&bus->devices)) {
                 dev = container_of(bus->devices.next, struct pci_dev,
                                    bus_list);
-                dev_dbg(&dev->dev, "removing device\n");
+                pci_dbg(dev, "removing device\n");
                 pci_stop_and_remove_bus_device(dev);
         }
 }
@@ -595,6 +596,7 @@ static pci_ers_result_t pcifront_common_process(int cmd,
         struct pci_driver *pdrv;
         int bus = pdev->sh_info->aer_op.bus;
         int devfn = pdev->sh_info->aer_op.devfn;
+        int domain = pdev->sh_info->aer_op.domain;
         struct pci_dev *pcidev;
         int flag = 0;
 
@@ -603,7 +605,7 @@ static pci_ers_result_t pcifront_common_process(int cmd,
                 cmd, bus, devfn);
         result = PCI_ERS_RESULT_NONE;
 
-        pcidev = pci_get_bus_and_slot(bus, devfn);
+        pcidev = pci_get_domain_bus_and_slot(domain, bus, devfn);
         if (!pcidev || !pcidev->driver) {
                 dev_err(&pdev->xdev->dev, "device or AER driver is NULL\n");
                 pci_dev_put(pcidev);
@@ -613,8 +615,7 @@ static pci_ers_result_t pcifront_common_process(int cmd,
 
         if (pdrv) {
                 if (pdrv->err_handler && pdrv->err_handler->error_detected) {
-                        dev_dbg(&pcidev->dev,
-                                "trying to call AER service\n");
+                        pci_dbg(pcidev, "trying to call AER service\n");
                         if (pcidev) {
                                 flag = 1;
                                 switch (cmd) {