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path: root/drivers/pci/quirks.c
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Diffstat (limited to 'drivers/pci/quirks.c')
-rw-r--r--drivers/pci/quirks.c210
1 files changed, 106 insertions, 104 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 10684b17d0bd..fc734014206f 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -19,7 +19,6 @@
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/delay.h> 20#include <linux/delay.h>
21#include <linux/acpi.h> 21#include <linux/acpi.h>
22#include <linux/kallsyms.h>
23#include <linux/dmi.h> 22#include <linux/dmi.h>
24#include <linux/pci-aspm.h> 23#include <linux/pci-aspm.h>
25#include <linux/ioport.h> 24#include <linux/ioport.h>
@@ -66,7 +65,7 @@ static void quirk_passive_release(struct pci_dev *dev)
66 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 65 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
67 pci_read_config_byte(d, 0x82, &dlc); 66 pci_read_config_byte(d, 0x82, &dlc);
68 if (!(dlc & 1<<1)) { 67 if (!(dlc & 1<<1)) {
69 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); 68 pci_info(d, "PIIX3: Enabling Passive Release\n");
70 dlc |= 1<<1; 69 dlc |= 1<<1;
71 pci_write_config_byte(d, 0x82, dlc); 70 pci_write_config_byte(d, 0x82, dlc);
72 } 71 }
@@ -86,7 +85,7 @@ static void quirk_isa_dma_hangs(struct pci_dev *dev)
86{ 85{
87 if (!isa_dma_bridge_buggy) { 86 if (!isa_dma_bridge_buggy) {
88 isa_dma_bridge_buggy = 1; 87 isa_dma_bridge_buggy = 1;
89 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); 88 pci_info(dev, "Activating ISA DMA hang workarounds\n");
90 } 89 }
91} 90}
92 /* 91 /*
@@ -115,7 +114,7 @@ static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
115 pm1a = inw(pmbase); 114 pm1a = inw(pmbase);
116 115
117 if (pm1a & 0x10) { 116 if (pm1a & 0x10) {
118 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); 117 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
119 outw(0x10, pmbase); 118 outw(0x10, pmbase);
120 } 119 }
121} 120}
@@ -127,7 +126,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk
127static void quirk_nopcipci(struct pci_dev *dev) 126static void quirk_nopcipci(struct pci_dev *dev)
128{ 127{
129 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 128 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
130 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); 129 pci_info(dev, "Disabling direct PCI/PCI transfers\n");
131 pci_pci_problems |= PCIPCI_FAIL; 130 pci_pci_problems |= PCIPCI_FAIL;
132 } 131 }
133} 132}
@@ -140,7 +139,7 @@ static void quirk_nopciamd(struct pci_dev *dev)
140 pci_read_config_byte(dev, 0x08, &rev); 139 pci_read_config_byte(dev, 0x08, &rev);
141 if (rev == 0x13) { 140 if (rev == 0x13) {
142 /* Erratum 24 */ 141 /* Erratum 24 */
143 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 142 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
144 pci_pci_problems |= PCIAGP_FAIL; 143 pci_pci_problems |= PCIAGP_FAIL;
145 } 144 }
146} 145}
@@ -152,7 +151,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopci
152static void quirk_triton(struct pci_dev *dev) 151static void quirk_triton(struct pci_dev *dev)
153{ 152{
154 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 153 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
155 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 154 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
156 pci_pci_problems |= PCIPCI_TRITON; 155 pci_pci_problems |= PCIPCI_TRITON;
157 } 156 }
158} 157}
@@ -212,7 +211,7 @@ static void quirk_vialatency(struct pci_dev *dev)
212 busarb &= ~(1<<5); 211 busarb &= ~(1<<5);
213 busarb |= (1<<4); 212 busarb |= (1<<4);
214 pci_write_config_byte(dev, 0x76, busarb); 213 pci_write_config_byte(dev, 0x76, busarb);
215 dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); 214 pci_info(dev, "Applying VIA southbridge workaround\n");
216exit: 215exit:
217 pci_dev_put(p); 216 pci_dev_put(p);
218} 217}
@@ -230,7 +229,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_viala
230static void quirk_viaetbf(struct pci_dev *dev) 229static void quirk_viaetbf(struct pci_dev *dev)
231{ 230{
232 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 231 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
233 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 232 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
234 pci_pci_problems |= PCIPCI_VIAETBF; 233 pci_pci_problems |= PCIPCI_VIAETBF;
235 } 234 }
236} 235}
@@ -239,7 +238,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_via
239static void quirk_vsfx(struct pci_dev *dev) 238static void quirk_vsfx(struct pci_dev *dev)
240{ 239{
241 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 240 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
242 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 241 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
243 pci_pci_problems |= PCIPCI_VSFX; 242 pci_pci_problems |= PCIPCI_VSFX;
244 } 243 }
245} 244}
@@ -254,7 +253,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx)
254static void quirk_alimagik(struct pci_dev *dev) 253static void quirk_alimagik(struct pci_dev *dev)
255{ 254{
256 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 255 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
257 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 256 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
258 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 257 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
259 } 258 }
260} 259}
@@ -268,7 +267,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagi
268static void quirk_natoma(struct pci_dev *dev) 267static void quirk_natoma(struct pci_dev *dev)
269{ 268{
270 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 269 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
271 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 270 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
272 pci_pci_problems |= PCIPCI_NATOMA; 271 pci_pci_problems |= PCIPCI_NATOMA;
273 } 272 }
274} 273}
@@ -313,7 +312,7 @@ static void quirk_extend_bar_to_page(struct pci_dev *dev)
313 r->end = PAGE_SIZE - 1; 312 r->end = PAGE_SIZE - 1;
314 r->start = 0; 313 r->start = 0;
315 r->flags |= IORESOURCE_UNSET; 314 r->flags |= IORESOURCE_UNSET;
316 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n", 315 pci_info(dev, "expanded BAR %d to page size: %pR\n",
317 i, r); 316 i, r);
318 } 317 }
319 } 318 }
@@ -360,7 +359,7 @@ static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
360 bus_region.end = region + size - 1; 359 bus_region.end = region + size - 1;
361 pcibios_bus_to_resource(dev->bus, res, &bus_region); 360 pcibios_bus_to_resource(dev->bus, res, &bus_region);
362 361
363 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", 362 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
364 name, PCI_BASE_ADDRESS_0 + (pos << 2), res); 363 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
365} 364}
366 365
@@ -381,7 +380,7 @@ static void quirk_cs5536_vsa(struct pci_dev *dev)
381 quirk_io(dev, 0, 8, name); /* SMB */ 380 quirk_io(dev, 0, 8, name); /* SMB */
382 quirk_io(dev, 1, 256, name); /* GPIO */ 381 quirk_io(dev, 1, 256, name); /* GPIO */
383 quirk_io(dev, 2, 64, name); /* MFGPT */ 382 quirk_io(dev, 2, 64, name); /* MFGPT */
384 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n", 383 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
385 name); 384 name);
386 } 385 }
387} 386}
@@ -409,7 +408,7 @@ static void quirk_io_region(struct pci_dev *dev, int port,
409 pcibios_bus_to_resource(dev->bus, res, &bus_region); 408 pcibios_bus_to_resource(dev->bus, res, &bus_region);
410 409
411 if (!pci_claim_resource(dev, nr)) 410 if (!pci_claim_resource(dev, nr))
412 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name); 411 pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
413} 412}
414 413
415/* 414/*
@@ -418,7 +417,7 @@ static void quirk_io_region(struct pci_dev *dev, int port,
418 */ 417 */
419static void quirk_ati_exploding_mce(struct pci_dev *dev) 418static void quirk_ati_exploding_mce(struct pci_dev *dev)
420{ 419{
421 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 420 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
422 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 421 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
423 request_region(0x3b0, 0x0C, "RadeonIGP"); 422 request_region(0x3b0, 0x0C, "RadeonIGP");
424 request_region(0x3d3, 0x01, "RadeonIGP"); 423 request_region(0x3d3, 0x01, "RadeonIGP");
@@ -441,7 +440,7 @@ static void quirk_amd_nl_class(struct pci_dev *pdev)
441 440
442 /* Use "USB Device (not host controller)" class */ 441 /* Use "USB Device (not host controller)" class */
443 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 442 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
444 dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 443 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
445 class, pdev->class); 444 class, pdev->class);
446} 445}
447DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 446DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
@@ -488,8 +487,7 @@ static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int p
488 * let's get enough confirmation reports first. 487 * let's get enough confirmation reports first.
489 */ 488 */
490 base &= -size; 489 base &= -size;
491 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, 490 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
492 base + size - 1);
493} 491}
494 492
495static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 493static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
@@ -514,8 +512,7 @@ static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int
514 * reserve it, but let's get enough confirmation reports first. 512 * reserve it, but let's get enough confirmation reports first.
515 */ 513 */
516 base &= -size; 514 base &= -size;
517 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, 515 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
518 base + size - 1);
519} 516}
520 517
521/* 518/*
@@ -644,7 +641,7 @@ static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const cha
644 base &= ~(size-1); 641 base &= ~(size-1);
645 642
646 /* Just print it out for now. We should reserve it after more debugging */ 643 /* Just print it out for now. We should reserve it after more debugging */
647 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 644 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
648} 645}
649 646
650static void quirk_ich6_lpc(struct pci_dev *dev) 647static void quirk_ich6_lpc(struct pci_dev *dev)
@@ -679,7 +676,7 @@ static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const cha
679 mask |= 3; 676 mask |= 3;
680 677
681 /* Just print it out for now. We should reserve it after more debugging */ 678 /* Just print it out for now. We should reserve it after more debugging */
682 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 679 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
683} 680}
684 681
685/* ICH7-10 has the same common LPC generic IO decode registers */ 682/* ICH7-10 has the same common LPC generic IO decode registers */
@@ -758,7 +755,7 @@ static void quirk_xio2000a(struct pci_dev *dev)
758 struct pci_dev *pdev; 755 struct pci_dev *pdev;
759 u16 command; 756 u16 command;
760 757
761 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 758 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
762 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 759 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
763 pci_read_config_word(pdev, PCI_COMMAND, &command); 760 pci_read_config_word(pdev, PCI_COMMAND, &command);
764 if (command & PCI_COMMAND_FAST_BACK) 761 if (command & PCI_COMMAND_FAST_BACK)
@@ -788,7 +785,7 @@ static void quirk_via_ioapic(struct pci_dev *dev)
788 else 785 else
789 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 786 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
790 787
791 dev_info(&dev->dev, "%sbling VIA external APIC routing\n", 788 pci_info(dev, "%sbling VIA external APIC routing\n",
792 tmp == 0 ? "Disa" : "Ena"); 789 tmp == 0 ? "Disa" : "Ena");
793 790
794 /* Offset 0x58: External APIC IRQ output control */ 791 /* Offset 0x58: External APIC IRQ output control */
@@ -810,7 +807,7 @@ static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
810 807
811 pci_read_config_byte(dev, 0x5B, &misc_control2); 808 pci_read_config_byte(dev, 0x5B, &misc_control2);
812 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 809 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
813 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 810 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
814 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 811 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
815 } 812 }
816} 813}
@@ -829,8 +826,8 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk
829static void quirk_amd_ioapic(struct pci_dev *dev) 826static void quirk_amd_ioapic(struct pci_dev *dev)
830{ 827{
831 if (dev->revision >= 0x02) { 828 if (dev->revision >= 0x02) {
832 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 829 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
833 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); 830 pci_warn(dev, " : booting with the \"noapic\" option\n");
834 } 831 }
835} 832}
836DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 833DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
@@ -854,7 +851,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_lin
854static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 851static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
855{ 852{
856 if (dev->subordinate && dev->revision <= 0x12) { 853 if (dev->subordinate && dev->revision <= 0x12) {
857 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 854 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
858 dev->revision); 855 dev->revision);
859 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 856 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
860 } 857 }
@@ -962,7 +959,7 @@ static void quirk_via_vlink(struct pci_dev *dev)
962 959
963 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 960 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
964 if (new_irq != irq) { 961 if (new_irq != irq) {
965 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", 962 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
966 irq, new_irq); 963 irq, new_irq);
967 udelay(15); /* unknown if delay really needed */ 964 udelay(15); /* unknown if delay really needed */
968 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 965 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
@@ -1011,7 +1008,7 @@ static void quirk_amd_ordering(struct pci_dev *dev)
1011 pci_read_config_dword(dev, 0x4C, &pcic); 1008 pci_read_config_dword(dev, 0x4C, &pcic);
1012 if ((pcic & 6) != 6) { 1009 if ((pcic & 6) != 6) {
1013 pcic |= 6; 1010 pcic |= 6;
1014 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1011 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1015 pci_write_config_dword(dev, 0x4C, pcic); 1012 pci_write_config_dword(dev, 0x4C, pcic);
1016 pci_read_config_dword(dev, 0x84, &pcic); 1013 pci_read_config_dword(dev, 0x84, &pcic);
1017 pcic |= (1 << 23); /* Required in this mode */ 1014 pcic |= (1 << 23); /* Required in this mode */
@@ -1064,7 +1061,7 @@ static void quirk_mediagx_master(struct pci_dev *dev)
1064 pci_read_config_byte(dev, 0x41, &reg); 1061 pci_read_config_byte(dev, 0x41, &reg);
1065 if (reg & 2) { 1062 if (reg & 2) {
1066 reg &= ~2; 1063 reg &= ~2;
1067 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1064 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1068 reg); 1065 reg);
1069 pci_write_config_byte(dev, 0x41, reg); 1066 pci_write_config_byte(dev, 0x41, reg);
1070 } 1067 }
@@ -1087,7 +1084,7 @@ static void quirk_disable_pxb(struct pci_dev *pdev)
1087 if (config & (1<<6)) { 1084 if (config & (1<<6)) {
1088 config &= ~(1<<6); 1085 config &= ~(1<<6);
1089 pci_write_config_word(pdev, 0x40, config); 1086 pci_write_config_word(pdev, 0x40, config);
1090 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1087 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1091 } 1088 }
1092} 1089}
1093DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1090DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
@@ -1107,7 +1104,7 @@ static void quirk_amd_ide_mode(struct pci_dev *pdev)
1107 pci_write_config_byte(pdev, 0x40, tmp); 1104 pci_write_config_byte(pdev, 0x40, tmp);
1108 1105
1109 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1106 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1110 dev_info(&pdev->dev, "set SATA to AHCI mode\n"); 1107 pci_info(pdev, "set SATA to AHCI mode\n");
1111 } 1108 }
1112} 1109}
1113DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1110DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
@@ -1145,7 +1142,7 @@ static void quirk_ide_samemode(struct pci_dev *pdev)
1145 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1142 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1146 1143
1147 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1144 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1148 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); 1145 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1149 prog &= ~5; 1146 prog &= ~5;
1150 pdev->class &= ~5; 1147 pdev->class &= ~5;
1151 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1148 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
@@ -1356,10 +1353,10 @@ static void asus_hides_smbus_lpc(struct pci_dev *dev)
1356 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1353 pci_write_config_word(dev, 0xF2, val & (~0x8));
1357 pci_read_config_word(dev, 0xF2, &val); 1354 pci_read_config_word(dev, 0xF2, &val);
1358 if (val & 0x8) 1355 if (val & 0x8)
1359 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1356 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1360 val); 1357 val);
1361 else 1358 else
1362 dev_info(&dev->dev, "Enabled i801 SMBus device\n"); 1359 pci_info(dev, "Enabled i801 SMBus device\n");
1363 } 1360 }
1364} 1361}
1365DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1362DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
@@ -1411,7 +1408,7 @@ static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1411 return; 1408 return;
1412 iounmap(asus_rcba_base); 1409 iounmap(asus_rcba_base);
1413 asus_rcba_base = NULL; 1410 asus_rcba_base = NULL;
1414 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); 1411 pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1415} 1412}
1416 1413
1417static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1414static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
@@ -1433,7 +1430,7 @@ static void quirk_sis_96x_smbus(struct pci_dev *dev)
1433 u8 val = 0; 1430 u8 val = 0;
1434 pci_read_config_byte(dev, 0x77, &val); 1431 pci_read_config_byte(dev, 0x77, &val);
1435 if (val & 0x10) { 1432 if (val & 0x10) {
1436 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); 1433 pci_info(dev, "Enabling SiS 96x SMBus\n");
1437 pci_write_config_byte(dev, 0x77, val & ~0x10); 1434 pci_write_config_byte(dev, 0x77, val & ~0x10);
1438 } 1435 }
1439} 1436}
@@ -1505,10 +1502,10 @@ static void asus_hides_ac97_lpc(struct pci_dev *dev)
1505 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1502 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1506 pci_read_config_byte(dev, 0x50, &val); 1503 pci_read_config_byte(dev, 0x50, &val);
1507 if (val & 0xc0) 1504 if (val & 0xc0)
1508 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1505 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1509 val); 1506 val);
1510 else 1507 else
1511 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); 1508 pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1512 } 1509 }
1513} 1510}
1514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1511DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
@@ -1599,7 +1596,7 @@ static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1599{ 1596{
1600 if (dev->multifunction) { 1597 if (dev->multifunction) {
1601 device_disable_async_suspend(&dev->dev); 1598 device_disable_async_suspend(&dev->dev);
1602 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1599 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1603 } 1600 }
1604} 1601}
1605DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1602DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
@@ -1636,8 +1633,8 @@ static void quirk_pcie_mch(struct pci_dev *pdev)
1636DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1633DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1637DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1634DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1638DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1635DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1639DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, quirk_pcie_mch);
1640 1636
1637DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1641 1638
1642/* 1639/*
1643 * It's possible for the MSI to get corrupted if shpc and acpi 1640 * It's possible for the MSI to get corrupted if shpc and acpi
@@ -1646,7 +1643,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, quirk_pcie_mch);
1646static void quirk_pcie_pxh(struct pci_dev *dev) 1643static void quirk_pcie_pxh(struct pci_dev *dev)
1647{ 1644{
1648 dev->no_msi = 1; 1645 dev->no_msi = 1;
1649 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1646 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
1650} 1647}
1651DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1648DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1652DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1649DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
@@ -1692,7 +1689,7 @@ static void quirk_radeon_pm(struct pci_dev *dev)
1692 dev->subsystem_device == 0x00e2) { 1689 dev->subsystem_device == 0x00e2) {
1693 if (dev->d3_delay < 20) { 1690 if (dev->d3_delay < 20) {
1694 dev->d3_delay = 20; 1691 dev->d3_delay = 20;
1695 dev_info(&dev->dev, "extending delay after power-on from D3 to %d msec\n", 1692 pci_info(dev, "extending delay after power-on from D3 to %d msec\n",
1696 dev->d3_delay); 1693 dev->d3_delay);
1697 } 1694 }
1698 } 1695 }
@@ -1736,7 +1733,7 @@ static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1736 return; 1733 return;
1737 1734
1738 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 1735 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1739 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n", 1736 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
1740 dev->vendor, dev->device); 1737 dev->vendor, dev->device);
1741} 1738}
1742DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1739DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
@@ -1779,7 +1776,7 @@ static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1779 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 1776 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1780 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); 1777 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1781 1778
1782 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1779 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1783 dev->vendor, dev->device); 1780 dev->vendor, dev->device);
1784} 1781}
1785DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1782DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
@@ -1812,7 +1809,7 @@ static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1812 1809
1813 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 1810 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1814 1811
1815 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1812 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1816 dev->vendor, dev->device); 1813 dev->vendor, dev->device);
1817} 1814}
1818DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1815DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
@@ -1845,7 +1842,7 @@ static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1845 pci_config_dword &= ~AMD_813X_NOIOAMODE; 1842 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1846 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 1843 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1847 1844
1848 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1845 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1849 dev->vendor, dev->device); 1846 dev->vendor, dev->device);
1850} 1847}
1851DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1848DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
@@ -1864,12 +1861,12 @@ static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1864 1861
1865 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 1862 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1866 if (!pci_config_word) { 1863 if (!pci_config_word) {
1867 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n", 1864 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1868 dev->vendor, dev->device); 1865 dev->vendor, dev->device);
1869 return; 1866 return;
1870 } 1867 }
1871 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 1868 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1872 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1869 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1873 dev->vendor, dev->device); 1870 dev->vendor, dev->device);
1874} 1871}
1875DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1872DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
@@ -1913,7 +1910,7 @@ static void quirk_plx_pci9050(struct pci_dev *dev)
1913 if (pci_resource_len(dev, bar) == 0x80 && 1910 if (pci_resource_len(dev, bar) == 0x80 &&
1914 (pci_resource_start(dev, bar) & 0x80)) { 1911 (pci_resource_start(dev, bar) & 0x80)) {
1915 struct resource *r = &dev->resource[bar]; 1912 struct resource *r = &dev->resource[bar];
1916 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 1913 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1917 bar); 1914 bar);
1918 r->flags |= IORESOURCE_UNSET; 1915 r->flags |= IORESOURCE_UNSET;
1919 r->start = 0; 1916 r->start = 0;
@@ -1960,7 +1957,7 @@ static void quirk_netmos(struct pci_dev *dev)
1960 case PCI_DEVICE_ID_NETMOS_9845: 1957 case PCI_DEVICE_ID_NETMOS_9845:
1961 case PCI_DEVICE_ID_NETMOS_9855: 1958 case PCI_DEVICE_ID_NETMOS_9855:
1962 if (num_parallel) { 1959 if (num_parallel) {
1963 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 1960 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
1964 dev->device, num_parallel, num_serial); 1961 dev->device, num_parallel, num_serial);
1965 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1962 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1966 (dev->class & 0xff); 1963 (dev->class & 0xff);
@@ -2046,13 +2043,13 @@ static void quirk_e100_interrupt(struct pci_dev *dev)
2046 /* Convert from PCI bus to resource space. */ 2043 /* Convert from PCI bus to resource space. */
2047 csr = ioremap(pci_resource_start(dev, 0), 8); 2044 csr = ioremap(pci_resource_start(dev, 0), 8);
2048 if (!csr) { 2045 if (!csr) {
2049 dev_warn(&dev->dev, "Can't map e100 registers\n"); 2046 pci_warn(dev, "Can't map e100 registers\n");
2050 return; 2047 return;
2051 } 2048 }
2052 2049
2053 cmd_hi = readb(csr + 3); 2050 cmd_hi = readb(csr + 3);
2054 if (cmd_hi == 0) { 2051 if (cmd_hi == 0) {
2055 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n"); 2052 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2056 writeb(1, csr + 3); 2053 writeb(1, csr + 3);
2057 } 2054 }
2058 2055
@@ -2067,7 +2064,7 @@ DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2067 */ 2064 */
2068static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2065static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2069{ 2066{
2070 dev_info(&dev->dev, "Disabling L0s\n"); 2067 pci_info(dev, "Disabling L0s\n");
2071 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 2068 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2072} 2069}
2073DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2070DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
@@ -2097,7 +2094,7 @@ static void fixup_rev1_53c810(struct pci_dev *dev)
2097 return; 2094 return;
2098 2095
2099 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2096 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2100 dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2097 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2101 class, dev->class); 2098 class, dev->class);
2102} 2099}
2103DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2100DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
@@ -2110,7 +2107,7 @@ static void quirk_p64h2_1k_io(struct pci_dev *dev)
2110 pci_read_config_word(dev, 0x40, &en1k); 2107 pci_read_config_word(dev, 0x40, &en1k);
2111 2108
2112 if (en1k & 0x200) { 2109 if (en1k & 0x200) {
2113 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); 2110 pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2114 dev->io_window_1k = 1; 2111 dev->io_window_1k = 1;
2115 } 2112 }
2116} 2113}
@@ -2126,7 +2123,7 @@ static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2126 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2123 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2127 if (!(b & 0x20)) { 2124 if (!(b & 0x20)) {
2128 pci_write_config_byte(dev, 0xf41, b | 0x20); 2125 pci_write_config_byte(dev, 0xf41, b | 0x20);
2129 dev_info(&dev->dev, "Linking AER extended capability\n"); 2126 pci_info(dev, "Linking AER extended capability\n");
2130 } 2127 }
2131 } 2128 }
2132} 2129}
@@ -2164,7 +2161,7 @@ static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2164 /* Turn off PCI Bus Parking */ 2161 /* Turn off PCI Bus Parking */
2165 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2162 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2166 2163
2167 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n"); 2164 pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2168 } 2165 }
2169 } 2166 }
2170 2167
@@ -2179,7 +2176,7 @@ static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2179 /* Disable "Read FIFO Timer" */ 2176 /* Disable "Read FIFO Timer" */
2180 pci_write_config_byte(dev, 0x77, 0x0); 2177 pci_write_config_byte(dev, 0x77, 0x0);
2181 2178
2182 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n"); 2179 pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2183 } 2180 }
2184 } 2181 }
2185} 2182}
@@ -2196,7 +2193,7 @@ static void quirk_blacklist_vpd(struct pci_dev *dev)
2196{ 2193{
2197 if (dev->vpd) { 2194 if (dev->vpd) {
2198 dev->vpd->len = 0; 2195 dev->vpd->len = 0;
2199 dev_warn(&dev->dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n"); 2196 pci_warn(dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
2200 } 2197 }
2201} 2198}
2202 2199
@@ -2312,7 +2309,7 @@ static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2312 u8 reg; 2309 u8 reg;
2313 2310
2314 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) { 2311 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2315 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); 2312 pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2316 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2313 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2317 } 2314 }
2318} 2315}
@@ -2351,7 +2348,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2351static void quirk_disable_all_msi(struct pci_dev *dev) 2348static void quirk_disable_all_msi(struct pci_dev *dev)
2352{ 2349{
2353 pci_no_msi(); 2350 pci_no_msi();
2354 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); 2351 pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2355} 2352}
2356DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2353DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2357DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2354DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
@@ -2366,7 +2363,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2366static void quirk_disable_msi(struct pci_dev *dev) 2363static void quirk_disable_msi(struct pci_dev *dev)
2367{ 2364{
2368 if (dev->subordinate) { 2365 if (dev->subordinate) {
2369 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2366 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2370 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2367 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2371 } 2368 }
2372} 2369}
@@ -2406,7 +2403,7 @@ static int msi_ht_cap_enabled(struct pci_dev *dev)
2406 2403
2407 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2404 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2408 &flags) == 0) { 2405 &flags) == 0) {
2409 dev_info(&dev->dev, "Found %s HT MSI Mapping\n", 2406 pci_info(dev, "Found %s HT MSI Mapping\n",
2410 flags & HT_MSI_FLAGS_ENABLE ? 2407 flags & HT_MSI_FLAGS_ENABLE ?
2411 "enabled" : "disabled"); 2408 "enabled" : "disabled");
2412 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2409 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
@@ -2422,7 +2419,7 @@ static int msi_ht_cap_enabled(struct pci_dev *dev)
2422static void quirk_msi_ht_cap(struct pci_dev *dev) 2419static void quirk_msi_ht_cap(struct pci_dev *dev)
2423{ 2420{
2424 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2421 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2425 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2422 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2426 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2423 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2427 } 2424 }
2428} 2425}
@@ -2446,7 +2443,7 @@ static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2446 if (!pdev) 2443 if (!pdev)
2447 return; 2444 return;
2448 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2445 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2449 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2446 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2450 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2447 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2451 } 2448 }
2452 pci_dev_put(pdev); 2449 pci_dev_put(pdev);
@@ -2465,7 +2462,7 @@ static void ht_enable_msi_mapping(struct pci_dev *dev)
2465 2462
2466 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2463 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2467 &flags) == 0) { 2464 &flags) == 0) {
2468 dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); 2465 pci_info(dev, "Enabling HT MSI Mapping\n");
2469 2466
2470 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2467 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2471 flags | HT_MSI_FLAGS_ENABLE); 2468 flags | HT_MSI_FLAGS_ENABLE);
@@ -2492,7 +2489,7 @@ static void nvenet_msi_disable(struct pci_dev *dev)
2492 if (board_name && 2489 if (board_name &&
2493 (strstr(board_name, "P5N32-SLI PREMIUM") || 2490 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2494 strstr(board_name, "P5N32-E SLI"))) { 2491 strstr(board_name, "P5N32-E SLI"))) {
2495 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n"); 2492 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2496 dev->no_msi = 1; 2493 dev->no_msi = 1;
2497 } 2494 }
2498} 2495}
@@ -2669,7 +2666,7 @@ static void ht_disable_msi_mapping(struct pci_dev *dev)
2669 2666
2670 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2667 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2671 &flags) == 0) { 2668 &flags) == 0) {
2672 dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); 2669 pci_info(dev, "Disabling HT MSI Mapping\n");
2673 2670
2674 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2671 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2675 flags & ~HT_MSI_FLAGS_ENABLE); 2672 flags & ~HT_MSI_FLAGS_ENABLE);
@@ -2699,9 +2696,10 @@ static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2699 * HT MSI mapping should be disabled on devices that are below 2696 * HT MSI mapping should be disabled on devices that are below
2700 * a non-Hypertransport host bridge. Locate the host bridge... 2697 * a non-Hypertransport host bridge. Locate the host bridge...
2701 */ 2698 */
2702 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); 2699 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
2700 PCI_DEVFN(0, 0));
2703 if (host_bridge == NULL) { 2701 if (host_bridge == NULL) {
2704 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2702 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2705 return; 2703 return;
2706 } 2704 }
2707 2705
@@ -2770,7 +2768,7 @@ static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2770{ 2768{
2771 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 2769 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2772 if (dev->revision < 0x18) { 2770 if (dev->revision < 0x18) {
2773 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n"); 2771 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
2774 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2772 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2775 } 2773 }
2776} 2774}
@@ -2899,8 +2897,8 @@ static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2899 pci_write_config_byte(dev, 0x8E, write_enable); 2897 pci_write_config_byte(dev, 0x8E, write_enable);
2900 pci_write_config_byte(dev, 0x8D, write_target); 2898 pci_write_config_byte(dev, 0x8D, write_target);
2901 2899
2902 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); 2900 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2903 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2901 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
2904} 2902}
2905DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2903DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2906DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2904DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
@@ -2935,7 +2933,7 @@ static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2935 pci_write_config_byte(dev, 0xe1, 0x32); 2933 pci_write_config_byte(dev, 0xe1, 0x32);
2936 pci_write_config_byte(dev, 0xfc, 0x00); 2934 pci_write_config_byte(dev, 0xfc, 0x00);
2937 2935
2938 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n"); 2936 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
2939 } 2937 }
2940 2938
2941 pci_read_config_byte(dev, 0xCB, &disable); 2939 pci_read_config_byte(dev, 0xCB, &disable);
@@ -2948,8 +2946,8 @@ static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2948 pci_write_config_byte(dev, 0xCB, disable | 0x02); 2946 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2949 pci_write_config_byte(dev, 0xCA, write_enable); 2947 pci_write_config_byte(dev, 0xCA, write_enable);
2950 2948
2951 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); 2949 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2952 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2950 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
2953 2951
2954} 2952}
2955DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2953DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
@@ -2990,7 +2988,7 @@ static void fixup_ti816x_class(struct pci_dev *dev)
2990 2988
2991 /* TI 816x devices do not have class code set when in PCIe boot mode */ 2989 /* TI 816x devices do not have class code set when in PCIe boot mode */
2992 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 2990 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
2993 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n", 2991 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
2994 class, dev->class); 2992 class, dev->class);
2995} 2993}
2996DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 2994DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
@@ -3032,7 +3030,7 @@ static void quirk_intel_mc_errata(struct pci_dev *dev)
3032 */ 3030 */
3033 err = pci_read_config_word(dev, 0x48, &rcc); 3031 err = pci_read_config_word(dev, 0x48, &rcc);
3034 if (err) { 3032 if (err) {
3035 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n"); 3033 pci_err(dev, "Error attempting to read the read completion coalescing register\n");
3036 return; 3034 return;
3037 } 3035 }
3038 3036
@@ -3043,7 +3041,7 @@ static void quirk_intel_mc_errata(struct pci_dev *dev)
3043 3041
3044 err = pci_write_config_word(dev, 0x48, rcc); 3042 err = pci_write_config_word(dev, 0x48, rcc);
3045 if (err) { 3043 if (err) {
3046 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n"); 3044 pci_err(dev, "Error attempting to write the read completion coalescing register\n");
3047 return; 3045 return;
3048 } 3046 }
3049 3047
@@ -3108,7 +3106,7 @@ static ktime_t fixup_debug_start(struct pci_dev *dev,
3108{ 3106{
3109 ktime_t calltime = 0; 3107 ktime_t calltime = 0;
3110 3108
3111 dev_dbg(&dev->dev, "calling %pF\n", fn); 3109 pci_dbg(dev, "calling %pF\n", fn);
3112 if (initcall_debug) { 3110 if (initcall_debug) {
3113 pr_debug("calling %pF @ %i for %s\n", 3111 pr_debug("calling %pF @ %i for %s\n",
3114 fn, task_pid_nr(current), dev_name(&dev->dev)); 3112 fn, task_pid_nr(current), dev_name(&dev->dev));
@@ -3150,13 +3148,13 @@ static void disable_igfx_irq(struct pci_dev *dev)
3150{ 3148{
3151 void __iomem *regs = pci_iomap(dev, 0, 0); 3149 void __iomem *regs = pci_iomap(dev, 0, 0);
3152 if (regs == NULL) { 3150 if (regs == NULL) {
3153 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n"); 3151 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3154 return; 3152 return;
3155 } 3153 }
3156 3154
3157 /* Check if any interrupt line is still enabled */ 3155 /* Check if any interrupt line is still enabled */
3158 if (readl(regs + I915_DEIER_REG) != 0) { 3156 if (readl(regs + I915_DEIER_REG) != 0) {
3159 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3157 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3160 3158
3161 writel(0, regs + I915_DEIER_REG); 3159 writel(0, regs + I915_DEIER_REG);
3162 } 3160 }
@@ -3215,6 +3213,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3215 quirk_broken_intx_masking); 3213 quirk_broken_intx_masking);
3216DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3214DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3217 quirk_broken_intx_masking); 3215 quirk_broken_intx_masking);
3216DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3217 quirk_broken_intx_masking);
3218 3218
3219/* 3219/*
3220 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3220 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
@@ -3317,13 +3317,13 @@ static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3317 3317
3318 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3318 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3319 if (pci_enable_device_mem(pdev)) { 3319 if (pci_enable_device_mem(pdev)) {
3320 dev_warn(&pdev->dev, "Can't enable device memory\n"); 3320 pci_warn(pdev, "Can't enable device memory\n");
3321 return; 3321 return;
3322 } 3322 }
3323 3323
3324 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3324 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3325 if (!fw_ver) { 3325 if (!fw_ver) {
3326 dev_warn(&pdev->dev, "Can't map ConnectX-4 initialization segment\n"); 3326 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3327 goto out; 3327 goto out;
3328 } 3328 }
3329 3329
@@ -3335,7 +3335,7 @@ static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3335 fw_subminor = fw_sub_min & 0xffff; 3335 fw_subminor = fw_sub_min & 0xffff;
3336 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3336 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3337 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3337 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3338 dev_warn(&pdev->dev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3338 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3339 fw_major, fw_minor, fw_subminor, pdev->device == 3339 fw_major, fw_minor, fw_subminor, pdev->device ==
3340 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3340 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3341 pdev->broken_intx_masking = 1; 3341 pdev->broken_intx_masking = 1;
@@ -3473,7 +3473,7 @@ static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3473 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3473 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3474 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3474 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3475 return; 3475 return;
3476 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n"); 3476 pci_info(dev, "quirk: cutting power to thunderbolt controller...\n");
3477 3477
3478 /* magic sequence */ 3478 /* magic sequence */
3479 acpi_execute_simple_method(SXIO, NULL, 1); 3479 acpi_execute_simple_method(SXIO, NULL, 1);
@@ -3524,7 +3524,7 @@ static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3524 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI) 3524 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3525 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8) 3525 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3526 goto out; 3526 goto out;
3527 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n"); 3527 pci_info(dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
3528 device_pm_wait_for_dev(&dev->dev, &nhi->dev); 3528 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3529out: 3529out:
3530 pci_dev_put(nhi); 3530 pci_dev_put(nhi);
@@ -3740,7 +3740,7 @@ static int reset_ivb_igd(struct pci_dev *dev, int probe)
3740 goto reset_complete; 3740 goto reset_complete;
3741 msleep(10); 3741 msleep(10);
3742 } while (time_before(jiffies, timeout)); 3742 } while (time_before(jiffies, timeout));
3743 dev_warn(&dev->dev, "timeout during reset\n"); 3743 pci_warn(dev, "timeout during reset\n");
3744 3744
3745reset_complete: 3745reset_complete:
3746 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3746 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
@@ -3879,6 +3879,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3879 quirk_dma_func1_alias); 3879 quirk_dma_func1_alias);
3880DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 3880DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3881 quirk_dma_func1_alias); 3881 quirk_dma_func1_alias);
3882DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
3883 quirk_dma_func1_alias);
3882/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 3884/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3883DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 3885DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3884 quirk_dma_func1_alias); 3886 quirk_dma_func1_alias);
@@ -4012,7 +4014,7 @@ static void quirk_tw686x_class(struct pci_dev *pdev)
4012 4014
4013 /* Use "Multimedia controller" class */ 4015 /* Use "Multimedia controller" class */
4014 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 4016 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4015 dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 4017 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4016 class, pdev->class); 4018 class, pdev->class);
4017} 4019}
4018DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 4020DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
@@ -4032,7 +4034,7 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4032static void quirk_relaxedordering_disable(struct pci_dev *dev) 4034static void quirk_relaxedordering_disable(struct pci_dev *dev)
4033{ 4035{
4034 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 4036 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4035 dev_info(&dev->dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 4037 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4036} 4038}
4037 4039
4038/* 4040/*
@@ -4141,11 +4143,11 @@ static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4141 struct pci_dev *root_port = pci_find_pcie_root_port(pdev); 4143 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4142 4144
4143 if (!root_port) { 4145 if (!root_port) {
4144 dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n"); 4146 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4145 return; 4147 return;
4146 } 4148 }
4147 4149
4148 dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4150 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4149 dev_name(&pdev->dev)); 4151 dev_name(&pdev->dev));
4150 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL, 4152 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4151 PCI_EXP_DEVCTL_RELAX_EN | 4153 PCI_EXP_DEVCTL_RELAX_EN |
@@ -4339,7 +4341,7 @@ static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4339 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV); 4341 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
4340 int ret = acs_flags & ~flags ? 0 : 1; 4342 int ret = acs_flags & ~flags ? 0 : 1;
4341 4343
4342 dev_info(&dev->dev, "Using QCOM ACS Quirk (%d)\n", ret); 4344 pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret);
4343 4345
4344 return ret; 4346 return ret;
4345} 4347}
@@ -4591,7 +4593,7 @@ static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4591 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 4593 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4592 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 4594 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4593 if (updcr & INTEL_UPDCR_REG_MASK) { 4595 if (updcr & INTEL_UPDCR_REG_MASK) {
4594 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n"); 4596 pci_info(dev, "Disabling UPDCR peer decodes\n");
4595 updcr &= ~INTEL_UPDCR_REG_MASK; 4597 updcr &= ~INTEL_UPDCR_REG_MASK;
4596 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 4598 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4597 } 4599 }
@@ -4618,7 +4620,7 @@ static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4618 */ 4620 */
4619 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 4621 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4620 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 4622 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4621 dev_info(&dev->dev, "Enabling MPC IRBNCE\n"); 4623 pci_info(dev, "Enabling MPC IRBNCE\n");
4622 mpc |= INTEL_MPC_REG_IRBNCE; 4624 mpc |= INTEL_MPC_REG_IRBNCE;
4623 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 4625 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4624 } 4626 }
@@ -4630,7 +4632,7 @@ static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4630 return -ENOTTY; 4632 return -ENOTTY;
4631 4633
4632 if (pci_quirk_enable_intel_lpc_acs(dev)) { 4634 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4633 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n"); 4635 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
4634 return 0; 4636 return 0;
4635 } 4637 }
4636 4638
@@ -4638,7 +4640,7 @@ static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4638 4640
4639 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 4641 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4640 4642
4641 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n"); 4643 pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
4642 4644
4643 return 0; 4645 return 0;
4644} 4646}
@@ -4665,7 +4667,7 @@ static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4665 4667
4666 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 4668 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4667 4669
4668 dev_info(&dev->dev, "Intel SPT PCH root port ACS workaround enabled\n"); 4670 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
4669 4671
4670 return 0; 4672 return 0;
4671} 4673}
@@ -4800,7 +4802,7 @@ static void quirk_no_ext_tags(struct pci_dev *pdev)
4800 return; 4802 return;
4801 4803
4802 bridge->no_ext_tags = 1; 4804 bridge->no_ext_tags = 1;
4803 dev_info(&pdev->dev, "disabling Extended Tags (this device can't handle them)\n"); 4805 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
4804 4806
4805 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 4807 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
4806} 4808}
@@ -4815,7 +4817,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
4815 */ 4817 */
4816static void quirk_no_ats(struct pci_dev *pdev) 4818static void quirk_no_ats(struct pci_dev *pdev)
4817{ 4819{
4818 dev_info(&pdev->dev, "disabling ATS (broken on this device)\n"); 4820 pci_info(pdev, "disabling ATS (broken on this device)\n");
4819 pdev->ats_cap = 0; 4821 pdev->ats_cap = 0;
4820} 4822}
4821 4823
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-27 10:49:51 -0400