aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/pci/quirks.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/pci/quirks.c')
-rw-r--r--drivers/pci/quirks.c94
1 files changed, 92 insertions, 2 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 3821c11c9add..a2afb44fad10 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -25,6 +25,7 @@
25#include <linux/sched.h> 25#include <linux/sched.h>
26#include <linux/ktime.h> 26#include <linux/ktime.h>
27#include <linux/mm.h> 27#include <linux/mm.h>
28#include <linux/platform_data/x86/apple.h>
28#include <asm/dma.h> /* isa_dma_bridge_buggy */ 29#include <asm/dma.h> /* isa_dma_bridge_buggy */
29#include "pci.h" 30#include "pci.h"
30 31
@@ -3447,7 +3448,7 @@ static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3447{ 3448{
3448 acpi_handle bridge, SXIO, SXFP, SXLV; 3449 acpi_handle bridge, SXIO, SXFP, SXLV;
3449 3450
3450 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc.")) 3451 if (!x86_apple_machine)
3451 return; 3452 return;
3452 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3453 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3453 return; 3454 return;
@@ -3492,7 +3493,7 @@ static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3492 struct pci_dev *sibling = NULL; 3493 struct pci_dev *sibling = NULL;
3493 struct pci_dev *nhi = NULL; 3494 struct pci_dev *nhi = NULL;
3494 3495
3495 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc.")) 3496 if (!x86_apple_machine)
3496 return; 3497 return;
3497 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM) 3498 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3498 return; 3499 return;
@@ -4016,6 +4017,95 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4016 quirk_tw686x_class); 4017 quirk_tw686x_class);
4017 4018
4018/* 4019/*
4020 * Some devices have problems with Transaction Layer Packets with the Relaxed
4021 * Ordering Attribute set. Such devices should mark themselves and other
4022 * Device Drivers should check before sending TLPs with RO set.
4023 */
4024static void quirk_relaxedordering_disable(struct pci_dev *dev)
4025{
4026 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4027 dev_info(&dev->dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4028}
4029
4030/*
4031 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4032 * Complex has a Flow Control Credit issue which can cause performance
4033 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4034 */
4035DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4036 quirk_relaxedordering_disable);
4037DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4038 quirk_relaxedordering_disable);
4039DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4040 quirk_relaxedordering_disable);
4041DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4042 quirk_relaxedordering_disable);
4043DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4044 quirk_relaxedordering_disable);
4045DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4046 quirk_relaxedordering_disable);
4047DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4048 quirk_relaxedordering_disable);
4049DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4050 quirk_relaxedordering_disable);
4051DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4052 quirk_relaxedordering_disable);
4053DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4054 quirk_relaxedordering_disable);
4055DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4056 quirk_relaxedordering_disable);
4057DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4058 quirk_relaxedordering_disable);
4059DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4060 quirk_relaxedordering_disable);
4061DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4062 quirk_relaxedordering_disable);
4063DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4064 quirk_relaxedordering_disable);
4065DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4066 quirk_relaxedordering_disable);
4067DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4068 quirk_relaxedordering_disable);
4069DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4070 quirk_relaxedordering_disable);
4071DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4072 quirk_relaxedordering_disable);
4073DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4074 quirk_relaxedordering_disable);
4075DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4076 quirk_relaxedordering_disable);
4077DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4078 quirk_relaxedordering_disable);
4079DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4080 quirk_relaxedordering_disable);
4081DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4082 quirk_relaxedordering_disable);
4083DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4084 quirk_relaxedordering_disable);
4085DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4086 quirk_relaxedordering_disable);
4087DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4088 quirk_relaxedordering_disable);
4089DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4090 quirk_relaxedordering_disable);
4091
4092/*
4093 * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex
4094 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4095 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4096 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4097 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4098 * November 10, 2010). As a result, on this platform we can't use Relaxed
4099 * Ordering for Upstream TLPs.
4100 */
4101DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4102 quirk_relaxedordering_disable);
4103DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4104 quirk_relaxedordering_disable);
4105DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4106 quirk_relaxedordering_disable);
4107
4108/*
4019 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4109 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4020 * values for the Attribute as were supplied in the header of the 4110 * values for the Attribute as were supplied in the header of the
4021 * corresponding Request, except as explicitly allowed when IDO is used." 4111 * corresponding Request, except as explicitly allowed when IDO is used."
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-04 04:21:53 -0500