1 files changed, 235 insertions, 137 deletions

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 14e0ea1ff38b..ef5377438a1e 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * probe.c - PCI detection and setup code
  */
@@ -69,8 +70,8 @@ static int find_anything(struct device *dev, void *data)
 }
 
 /*
- * Some device drivers need know if pci is initiated.
- * Basically, we think pci is not initiated when there
+ * Some device drivers need know if PCI is initiated.
+ * Basically, we think PCI is not initiated when there
  * is no device to be found on the pci_bus_type.
  */
 int no_pci_devices(void)
@@ -116,12 +117,16 @@ static u64 pci_size(u64 base, u64 maxbase, u64 mask)
         if (!size)
                 return 0;
 
-        /* Get the lowest of them to find the decode size, and
-           from that the extent.  */
+        /*
+         * Get the lowest of them to find the decode size, and from that
+         * the extent.
+         */
         size = (size & ~(size-1)) - 1;
 
-        /* base == maxbase can be valid only if the BAR has
-           already been programmed with all 1s.  */
+        /*
+         * base == maxbase can be valid only if the BAR has already been
+         * programmed with all 1s.
+         */
         if (base == maxbase && ((base | size) & mask) != mask)
                 return 0;
 
@@ -164,7 +169,7 @@ static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
 #define PCI_COMMAND_DECODE_ENABLE       (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
 
 /**
- * pci_read_base - read a PCI BAR
+ * pci_read_base - Read a PCI BAR
  * @dev: the PCI device
  * @type: type of the BAR
  * @res: resource buffer to be filled in
@@ -253,7 +258,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
 
         sz64 = pci_size(l64, sz64, mask64);
         if (!sz64) {
-                dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
+                pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
                          pos);
                 goto fail;
         }
@@ -264,7 +269,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
                         res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
                         res->start = 0;
                         res->end = 0;
-                        dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
+                        pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
                                 pos, (unsigned long long)sz64);
                         goto out;
                 }
@@ -274,7 +279,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
                         res->flags |= IORESOURCE_UNSET;
                         res->start = 0;
                         res->end = sz64;
-                        dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
+                        pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
                                  pos, (unsigned long long)l64);
                         goto out;
                 }
@@ -301,7 +306,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
                 res->flags |= IORESOURCE_UNSET;
                 res->start = 0;
                 res->end = region.end - region.start;
-                dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
+                pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
                          pos, (unsigned long long)region.start);
         }
 
@@ -312,7 +317,7 @@ fail:
         res->flags = 0;
 out:
         if (res->flags)
-                dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
+                pci_printk(KERN_DEBUG, dev, "reg 0x%x: %pR\n", pos, res);
 
         return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
 }
@@ -375,7 +380,7 @@ static void pci_read_bridge_io(struct pci_bus *child)
                 region.start = base;
                 region.end = limit + io_granularity - 1;
                 pcibios_bus_to_resource(dev->bus, res, &region);
-                dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
+                pci_printk(KERN_DEBUG, dev, "  bridge window %pR\n", res);
         }
 }
 
@@ -397,7 +402,7 @@ static void pci_read_bridge_mmio(struct pci_bus *child)
                 region.start = base;
                 region.end = limit + 0xfffff;
                 pcibios_bus_to_resource(dev->bus, res, &region);
-                dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
+                pci_printk(KERN_DEBUG, dev, "  bridge window %pR\n", res);
         }
 }
 
@@ -437,7 +442,7 @@ static void pci_read_bridge_mmio_pref(struct pci_bus *child)
         limit = (pci_bus_addr_t) limit64;
 
         if (base != base64) {
-                dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
+                pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
                         (unsigned long long) base64);
                 return;
         }
@@ -450,7 +455,7 @@ static void pci_read_bridge_mmio_pref(struct pci_bus *child)
                 region.start = base;
                 region.end = limit + 0xfffff;
                 pcibios_bus_to_resource(dev->bus, res, &region);
-                dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
+                pci_printk(KERN_DEBUG, dev, "  bridge window %pR\n", res);
         }
 }
 
@@ -463,7 +468,7 @@ void pci_read_bridge_bases(struct pci_bus *child)
         if (pci_is_root_bus(child))     /* It's a host bus, nothing to read */
                 return;
 
-        dev_info(&dev->dev, "PCI bridge to %pR%s\n",
+        pci_info(dev, "PCI bridge to %pR%s\n",
                  &child->busn_res,
                  dev->transparent ? " (subtractive decode)" : "");
 
@@ -480,7 +485,7 @@ void pci_read_bridge_bases(struct pci_bus *child)
                         if (res && res->flags) {
                                 pci_bus_add_resource(child, res,
                                                      PCI_SUBTRACTIVE_DECODE);
-                                dev_printk(KERN_DEBUG, &dev->dev,
+                                pci_printk(KERN_DEBUG, dev,
                                            "  bridge window %pR (subtractive decode)\n",
                                            res);
                         }
@@ -764,7 +769,7 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
 
         bridge->bus = bus;
 
-        /* temporarily move resources off the list */
+        /* Temporarily move resources off the list */
         list_splice_init(&bridge->windows, &resources);
         bus->sysdata = bridge->sysdata;
         bus->msi = bridge->msi;
@@ -776,7 +781,7 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
 
         b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
         if (b) {
-                /* If we already got to this bus through a different bridge, ignore it */
+                /* Ignore it if we already got here via a different bridge */
                 dev_dbg(&b->dev, "bus already known\n");
                 err = -EEXIST;
                 goto free;
@@ -869,9 +874,7 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
         int i;
         int ret;
 
-        /*
-         * Allocate a new bus, and inherit stuff from the parent..
-         */
+        /* Allocate a new bus and inherit stuff from the parent */
         child = pci_alloc_bus(parent);
         if (!child)
                 return NULL;
@@ -882,16 +885,14 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
         child->sysdata = parent->sysdata;
         child->bus_flags = parent->bus_flags;
 
-        /* initialize some portions of the bus device, but don't register it
-         * now as the parent is not properly set up yet.
+        /*
+         * Initialize some portions of the bus device, but don't register
+         * it now as the parent is not properly set up yet.
          */
         child->dev.class = &pcibus_class;
         dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
 
-        /*
-         * Set up the primary, secondary and subordinate
-         * bus numbers.
-         */
+        /* Set up the primary, secondary and subordinate bus numbers */
         child->number = child->busn_res.start = busnr;
         child->primary = parent->busn_res.start;
         child->busn_res.end = 0xff;
@@ -907,7 +908,7 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
         pci_set_bus_of_node(child);
         pci_set_bus_speed(child);
 
-        /* Set up default resource pointers and names.. */
+        /* Set up default resource pointers and names */
         for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
                 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
                 child->resource[i]->name = child->name;
@@ -1005,11 +1006,11 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
         secondary = (buses >> 8) & 0xFF;
         subordinate = (buses >> 16) & 0xFF;
 
-        dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
+        pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
                 secondary, subordinate, pass);
 
         if (!primary && (primary != bus->number) && secondary && subordinate) {
-                dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
+                pci_warn(dev, "Primary bus is hard wired to 0\n");
                 primary = bus->number;
         }
 
@@ -1017,13 +1018,15 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
         if (!pass &&
             (primary != bus->number || secondary <= bus->number ||
              secondary > subordinate)) {
-                dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
+                pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
                          secondary, subordinate);
                 broken = 1;
         }
 
-        /* Disable MasterAbortMode during probing to avoid reporting
-           of bus errors (in some architectures) */
+        /*
+         * Disable Master-Abort Mode during probing to avoid reporting of
+         * bus errors in some architectures.
+         */
         pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
         pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
                               bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
@@ -1033,18 +1036,19 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
         if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
             !is_cardbus && !broken) {
                 unsigned int cmax;
+
                 /*
-                 * Bus already configured by firmware, process it in the first
-                 * pass and just note the configuration.
+                 * Bus already configured by firmware, process it in the
+                 * first pass and just note the configuration.
                  */
                 if (pass)
                         goto out;
 
                 /*
-                 * The bus might already exist for two reasons: Either we are
-                 * rescanning the bus or the bus is reachable through more than
-                 * one bridge. The second case can happen with the i450NX
-                 * chipset.
+                 * The bus might already exist for two reasons: Either we
+                 * are rescanning the bus or the bus is reachable through
+                 * more than one bridge. The second case can happen with
+                 * the i450NX chipset.
                  */
                 child = pci_find_bus(pci_domain_nr(bus), secondary);
                 if (!child) {
@@ -1058,24 +1062,29 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
 
                 cmax = pci_scan_child_bus(child);
                 if (cmax > subordinate)
-                        dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
+                        pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
                                  subordinate, cmax);
-                /* subordinate should equal child->busn_res.end */
+
+                /* Subordinate should equal child->busn_res.end */
                 if (subordinate > max)
                         max = subordinate;
         } else {
+
                 /*
                  * We need to assign a number to this bus which we always
                  * do in the second pass.
                  */
                 if (!pass) {
                         if (pcibios_assign_all_busses() || broken || is_cardbus)
-                                /* Temporarily disable forwarding of the
-                                   configuration cycles on all bridges in
-                                   this bus segment to avoid possible
-                                   conflicts in the second pass between two
-                                   bridges programmed with overlapping
-                                   bus ranges. */
+
+                                /*
+                                 * Temporarily disable forwarding of the
+                                 * configuration cycles on all bridges in
+                                 * this bus segment to avoid possible
+                                 * conflicts in the second pass between two
+                                 * bridges programmed with overlapping bus
+                                 * ranges.
+                                 */
                                 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
                                                        buses & ~0xffffff);
                         goto out;
@@ -1084,9 +1093,11 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
                 /* Clear errors */
                 pci_write_config_word(dev, PCI_STATUS, 0xffff);
 
-                /* Prevent assigning a bus number that already exists.
-                 * This can happen when a bridge is hot-plugged, so in
-                 * this case we only re-scan this bus. */
+                /*
+                 * Prevent assigning a bus number that already exists.
+                 * This can happen when a bridge is hot-plugged, so in this
+                 * case we only re-scan this bus.
+                 */
                 child = pci_find_bus(pci_domain_nr(bus), max+1);
                 if (!child) {
                         child = pci_add_new_bus(bus, dev, max+1);
@@ -1113,19 +1124,18 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
                         buses |= CARDBUS_LATENCY_TIMER << 24;
                 }
 
-                /*
-                 * We need to blast all three values with a single write.
-                 */
+                /* We need to blast all three values with a single write */
                 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
 
                 if (!is_cardbus) {
                         child->bridge_ctl = bctl;
                         max = pci_scan_child_bus_extend(child, available_buses);
                 } else {
+
                         /*
-                         * For CardBus bridges, we leave 4 bus numbers
-                         * as cards with a PCI-to-PCI bridge can be
-                         * inserted later.
+                         * For CardBus bridges, we leave 4 bus numbers as
+                         * cards with a PCI-to-PCI bridge can be inserted
+                         * later.
                          */
                         for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
                                 struct pci_bus *parent = bus;
@@ -1141,10 +1151,11 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
                                         parent = parent->parent;
                                 }
                                 if (j) {
+
                                         /*
-                                         * Often, there are two cardbus bridges
-                                         * -- try to leave one valid bus number
-                                         * for each one.
+                                         * Often, there are two CardBus
+                                         * bridges -- try to leave one
+                                         * valid bus number for each one.
                                          */
                                         i /= 2;
                                         break;
@@ -1152,9 +1163,8 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
                         }
                         max += i;
                 }
-                /*
-                 * Set the subordinate bus number to its real value.
-                 */
+
+                /* Set subordinate bus number to its real value */
                 pci_bus_update_busn_res_end(child, max);
                 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
         }
@@ -1295,7 +1305,7 @@ static void set_pcie_thunderbolt(struct pci_dev *dev)
 }
 
 /**
- * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
+ * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
  * @dev: PCI device
  *
  * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
@@ -1332,7 +1342,7 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
 }
 
 /**
- * pci_cfg_space_size - get the configuration space size of the PCI device.
+ * pci_cfg_space_size - Get the configuration space size of the PCI device
  * @dev: PCI device
  *
  * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
@@ -1398,7 +1408,7 @@ static void pci_msi_setup_pci_dev(struct pci_dev *dev)
 }
 
 /**
- * pci_intx_mask_broken - test PCI_COMMAND_INTX_DISABLE writability
+ * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
  * @dev: PCI device
  *
  * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev.  Check this
@@ -1426,11 +1436,11 @@ static int pci_intx_mask_broken(struct pci_dev *dev)
 }
 
 /**
- * pci_setup_device - fill in class and map information of a device
+ * pci_setup_device - Fill in class and map information of a device
  * @dev: the device structure to fill
  *
  * Initialize the device structure with information about the device's
- * vendor,class,memory and IO-space addresses,IRQ lines etc.
+ * vendor,class,memory and IO-space addresses, IRQ lines etc.
  * Called at initialisation of the PCI subsystem and by CardBus services.
  * Returns 0 on success and negative if unknown type of device (not normal,
  * bridge or CardBus).
@@ -1456,8 +1466,11 @@ int pci_setup_device(struct pci_dev *dev)
         set_pcie_port_type(dev);
 
         pci_dev_assign_slot(dev);
-        /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
-           set this higher, assuming the system even supports it.  */
+
+        /*
+         * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
+         * set this higher, assuming the system even supports it.
+         */
         dev->dma_mask = 0xffffffff;
 
         dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
@@ -1468,13 +1481,13 @@ int pci_setup_device(struct pci_dev *dev)
         dev->revision = class & 0xff;
         dev->class = class >> 8;                    /* upper 3 bytes */
 
-        dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
+        pci_printk(KERN_DEBUG, dev, "[%04x:%04x] type %02x class %#08x\n",
                    dev->vendor, dev->device, dev->hdr_type, dev->class);
 
-        /* need to have dev->class ready */
+        /* Need to have dev->class ready */
         dev->cfg_size = pci_cfg_space_size(dev);
 
-        /* need to have dev->cfg_size ready */
+        /* Need to have dev->cfg_size ready */
         set_pcie_thunderbolt(dev);
 
         /* "Unknown power state" */
@@ -1482,13 +1495,14 @@ int pci_setup_device(struct pci_dev *dev)
 
         /* Early fixups, before probing the BARs */
         pci_fixup_device(pci_fixup_early, dev);
-        /* device class may be changed after fixup */
+
+        /* Device class may be changed after fixup */
         class = dev->class >> 8;
 
         if (dev->non_compliant_bars) {
                 pci_read_config_word(dev, PCI_COMMAND, &cmd);
                 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
-                        dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
+                        pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
                         cmd &= ~PCI_COMMAND_IO;
                         cmd &= ~PCI_COMMAND_MEMORY;
                         pci_write_config_word(dev, PCI_COMMAND, cmd);
@@ -1521,14 +1535,14 @@ int pci_setup_device(struct pci_dev *dev)
                                 res = &dev->resource[0];
                                 res->flags = LEGACY_IO_RESOURCE;
                                 pcibios_bus_to_resource(dev->bus, res, &region);
-                                dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
+                                pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
                                          res);
                                 region.start = 0x3F6;
                                 region.end = 0x3F6;
                                 res = &dev->resource[1];
                                 res->flags = LEGACY_IO_RESOURCE;
                                 pcibios_bus_to_resource(dev->bus, res, &region);
-                                dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
+                                pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
                                          res);
                         }
                         if ((progif & 4) == 0) {
@@ -1537,14 +1551,14 @@ int pci_setup_device(struct pci_dev *dev)
                                 res = &dev->resource[2];
                                 res->flags = LEGACY_IO_RESOURCE;
                                 pcibios_bus_to_resource(dev->bus, res, &region);
-                                dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
+                                pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
                                          res);
                                 region.start = 0x376;
                                 region.end = 0x376;
                                 res = &dev->resource[3];
                                 res->flags = LEGACY_IO_RESOURCE;
                                 pcibios_bus_to_resource(dev->bus, res, &region);
-                                dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
+                                pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
                                          res);
                         }
                 }
@@ -1553,9 +1567,12 @@ int pci_setup_device(struct pci_dev *dev)
         case PCI_HEADER_TYPE_BRIDGE:                /* bridge header */
                 if (class != PCI_CLASS_BRIDGE_PCI)
                         goto bad;
-                /* The PCI-to-PCI bridge spec requires that subtractive
-                   decoding (i.e. transparent) bridge must have programming
-                   interface code of 0x01. */
+
+                /*
+                 * The PCI-to-PCI bridge spec requires that subtractive
+                 * decoding (i.e. transparent) bridge must have programming
+                 * interface code of 0x01.
+                 */
                 pci_read_irq(dev);
                 dev->transparent = ((dev->class & 0xff) == 1);
                 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
@@ -1577,12 +1594,12 @@ int pci_setup_device(struct pci_dev *dev)
                 break;
 
         default:                                    /* unknown header */
-                dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
+                pci_err(dev, "unknown header type %02x, ignoring device\n",
                         dev->hdr_type);
                 return -EIO;
 
         bad:
-                dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
+                pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
                         dev->class, dev->hdr_type);
                 dev->class = PCI_CLASS_NOT_DEFINED << 8;
         }
@@ -1606,7 +1623,7 @@ static void pci_configure_mps(struct pci_dev *dev)
                 return;
 
         if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
-                dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
+                pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
                          mps, pci_name(bridge), p_mps);
                 return;
         }
@@ -1620,12 +1637,12 @@ static void pci_configure_mps(struct pci_dev *dev)
 
         rc = pcie_set_mps(dev, p_mps);
         if (rc) {
-                dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
+                pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
                          p_mps);
                 return;
         }
 
-        dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
+        pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
                  p_mps, mps, 128 << dev->pcie_mpss);
 }
 
@@ -1645,8 +1662,7 @@ static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
                 hpp = &pci_default_type0;
 
         if (hpp->revision > 1) {
-                dev_warn(&dev->dev,
-                         "PCI settings rev %d not supported; using defaults\n",
+                pci_warn(dev, "PCI settings rev %d not supported; using defaults\n",
                          hpp->revision);
                 hpp = &pci_default_type0;
         }
@@ -1684,7 +1700,7 @@ static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
         if (!pos)
                 return;
 
-        dev_warn(&dev->dev, "PCI-X settings not supported\n");
+        pci_warn(dev, "PCI-X settings not supported\n");
 }
 
 static bool pcie_root_rcb_set(struct pci_dev *dev)
@@ -1714,7 +1730,7 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
                 return;
 
         if (hpp->revision > 1) {
-                dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
+                pci_warn(dev, "PCIe settings rev %d not supported\n",
                          hpp->revision);
                 return;
         }
@@ -1772,6 +1788,7 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
         /* Initialize Advanced Error Capabilities and Control Register */
         pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
         reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
+
         /* Don't enable ECRC generation or checking if unsupported */
         if (!(reg32 & PCI_ERR_CAP_ECRC_GENC))
                 reg32 &= ~PCI_ERR_CAP_ECRC_GENE;
@@ -1818,7 +1835,7 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
          */
         if (host->no_ext_tags) {
                 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
-                        dev_info(&dev->dev, "disabling Extended Tags\n");
+                        pci_info(dev, "disabling Extended Tags\n");
                         pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
                                                    PCI_EXP_DEVCTL_EXT_TAG);
                 }
@@ -1826,7 +1843,7 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
         }
 
         if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
-                dev_info(&dev->dev, "enabling Extended Tags\n");
+                pci_info(dev, "enabling Extended Tags\n");
                 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
                                          PCI_EXP_DEVCTL_EXT_TAG);
         }
@@ -1871,10 +1888,42 @@ static void pci_configure_relaxed_ordering(struct pci_dev *dev)
         if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
                 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
                                            PCI_EXP_DEVCTL_RELAX_EN);
-                dev_info(&dev->dev, "Disable Relaxed Ordering because the Root Port didn't support it\n");
+                pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
         }
 }
 
+static void pci_configure_ltr(struct pci_dev *dev)
+{
+#ifdef CONFIG_PCIEASPM
+        u32 cap;
+        struct pci_dev *bridge;
+
+        if (!pci_is_pcie(dev))
+                return;
+
+        pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
+        if (!(cap & PCI_EXP_DEVCAP2_LTR))
+                return;
+
+        /*
+         * Software must not enable LTR in an Endpoint unless the Root
+         * Complex and all intermediate Switches indicate support for LTR.
+         * PCIe r3.1, sec 6.18.
+         */
+        if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
+                dev->ltr_path = 1;
+        else {
+                bridge = pci_upstream_bridge(dev);
+                if (bridge && bridge->ltr_path)
+                        dev->ltr_path = 1;
+        }
+
+        if (dev->ltr_path)
+                pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
+                                         PCI_EXP_DEVCTL2_LTR_EN);
+#endif
+}
+
 static void pci_configure_device(struct pci_dev *dev)
 {
         struct hotplug_params hpp;
@@ -1883,6 +1932,7 @@ static void pci_configure_device(struct pci_dev *dev)
         pci_configure_mps(dev);
         pci_configure_extended_tags(dev, NULL);
         pci_configure_relaxed_ordering(dev);
+        pci_configure_ltr(dev);
 
         memset(&hpp, 0, sizeof(hpp));
         ret = pci_get_hp_params(dev, &hpp);
@@ -1902,10 +1952,11 @@ static void pci_release_capabilities(struct pci_dev *dev)
 }
 
 /**
- * pci_release_dev - free a pci device structure when all users of it are finished.
+ * pci_release_dev - Free a PCI device structure when all users of it are
+ *                   finished
  * @dev: device that's been disconnected
  *
- * Will be called only by the device core when all users of this pci device are
+ * Will be called only by the device core when all users of this PCI device are
  * done.
  */
 static void pci_release_dev(struct device *dev)
@@ -1993,7 +2044,7 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
         if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
                 return false;
 
-        /* some broken boards return 0 or ~0 if a slot is empty: */
+        /* Some broken boards return 0 or ~0 if a slot is empty: */
         if (*l == 0xffffffff || *l == 0x00000000 ||
             *l == 0x0000ffff || *l == 0xffff0000)
                 return false;
@@ -2006,8 +2057,8 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
 
 /*
- * Read the config data for a PCI device, sanity-check it
- * and fill in the dev structure...
+ * Read the config data for a PCI device, sanity-check it,
+ * and fill in the dev structure.
  */
 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
 {
@@ -2073,7 +2124,7 @@ static void pci_init_capabilities(struct pci_dev *dev)
 }
 
 /*
- * This is the equivalent of pci_host_bridge_msi_domain that acts on
+ * This is the equivalent of pci_host_bridge_msi_domain() that acts on
  * devices. Firmware interfaces that can select the MSI domain on a
  * per-device basis should be called from here.
  */
@@ -2082,7 +2133,7 @@ static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
         struct irq_domain *d;
 
         /*
-         * If a domain has been set through the pcibios_add_device
+         * If a domain has been set through the pcibios_add_device()
          * callback, then this is the one (platform code knows best).
          */
         d = dev_get_msi_domain(&dev->dev);
@@ -2136,10 +2187,10 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
         /* Fix up broken headers */
         pci_fixup_device(pci_fixup_header, dev);
 
-        /* moved out from quirk header fixup code */
+        /* Moved out from quirk header fixup code */
         pci_reassigndev_resource_alignment(dev);
 
-        /* Clear the state_saved flag. */
+        /* Clear the state_saved flag */
         dev->state_saved = false;
 
         /* Initialize various capabilities */
@@ -2156,7 +2207,7 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
         ret = pcibios_add_device(dev);
         WARN_ON(ret < 0);
 
-        /* Setup MSI irq domain */
+        /* Set up MSI IRQ domain */
         pci_set_msi_domain(dev);
 
         /* Notifier could use PCI capabilities */
@@ -2215,29 +2266,34 @@ static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
 
 static int only_one_child(struct pci_bus *bus)
 {
-        struct pci_dev *parent = bus->self;
+        struct pci_dev *bridge = bus->self;
 
-        if (!parent || !pci_is_pcie(parent))
+        /*
+         * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
+         * we scan for all possible devices, not just Device 0.
+         */
+        if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
                 return 0;
-        if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
-                return 1;
 
         /*
-         * PCIe downstream ports are bridges that normally lead to only a
-         * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all
-         * possible devices, not just device 0.  See PCIe spec r3.0,
-         * sec 7.3.1.
+         * A PCIe Downstream Port normally leads to a Link with only Device
+         * 0 on it (PCIe spec r3.1, sec 7.3.1).  As an optimization, scan
+         * only for Device 0 in that situation.
+         *
+         * Checking has_secondary_link is a hack to identify Downstream
+         * Ports because sometimes Switches are configured such that the
+         * PCIe Port Type labels are backwards.
          */
-        if (parent->has_secondary_link &&
-            !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
+        if (bridge && pci_is_pcie(bridge) && bridge->has_secondary_link)
                 return 1;
+
         return 0;
 }
 
 /**
- * pci_scan_slot - scan a PCI slot on a bus for devices.
+ * pci_scan_slot - Scan a PCI slot on a bus for devices
  * @bus: PCI bus to scan
- * @devfn: slot number to scan (must have zero function.)
+ * @devfn: slot number to scan (must have zero function)
  *
  * Scan a PCI slot on the specified PCI bus for devices, adding
  * discovered devices to the @bus->devices list.  New devices
@@ -2268,7 +2324,7 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
                 }
         }
 
-        /* only one slot has pcie device */
+        /* Only one slot has PCIe device */
         if (bus->self && nr)
                 pcie_aspm_init_link_state(bus->self);
 
@@ -2317,7 +2373,9 @@ static void pcie_write_mps(struct pci_dev *dev, int mps)
 
                 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
                     dev->bus->self)
-                        /* For "Performance", the assumption is made that
+
+                        /*
+                         * For "Performance", the assumption is made that
                          * downstream communication will never be larger than
                          * the MRRS.  So, the MPS only needs to be configured
                          * for the upstream communication.  This being the case,
@@ -2334,27 +2392,30 @@ static void pcie_write_mps(struct pci_dev *dev, int mps)
 
         rc = pcie_set_mps(dev, mps);
         if (rc)
-                dev_err(&dev->dev, "Failed attempting to set the MPS\n");
+                pci_err(dev, "Failed attempting to set the MPS\n");
 }
 
 static void pcie_write_mrrs(struct pci_dev *dev)
 {
         int rc, mrrs;
 
-        /* In the "safe" case, do not configure the MRRS.  There appear to be
+        /*
+         * In the "safe" case, do not configure the MRRS.  There appear to be
          * issues with setting MRRS to 0 on a number of devices.
          */
         if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
                 return;
 
-        /* For Max performance, the MRRS must be set to the largest supported
+        /*
+         * For max performance, the MRRS must be set to the largest supported
          * value.  However, it cannot be configured larger than the MPS the
          * device or the bus can support.  This should already be properly
-         * configured by a prior call to pcie_write_mps.
+         * configured by a prior call to pcie_write_mps().
          */
         mrrs = pcie_get_mps(dev);
 
-        /* MRRS is a R/W register.  Invalid values can be written, but a
+        /*
+         * MRRS is a R/W register.  Invalid values can be written, but a
          * subsequent read will verify if the value is acceptable or not.
          * If the MRRS value provided is not acceptable (e.g., too large),
          * shrink the value until it is acceptable to the HW.
@@ -2364,12 +2425,12 @@ static void pcie_write_mrrs(struct pci_dev *dev)
                 if (!rc)
                         break;
 
-                dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
+                pci_warn(dev, "Failed attempting to set the MRRS\n");
                 mrrs /= 2;
         }
 
         if (mrrs < 128)
-                dev_err(&dev->dev, "MRRS was unable to be configured with a safe value.  If problems are experienced, try running with pci=pcie_bus_safe\n");
+                pci_err(dev, "MRRS was unable to be configured with a safe value.  If problems are experienced, try running with pci=pcie_bus_safe\n");
 }
 
 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
@@ -2389,14 +2450,15 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
         pcie_write_mps(dev, mps);
         pcie_write_mrrs(dev);
 
-        dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
+        pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
                  pcie_get_mps(dev), 128 << dev->pcie_mpss,
                  orig_mps, pcie_get_readrq(dev));
 
         return 0;
 }
 
-/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
+/*
+ * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
  * parents then children fashion.  If this changes, then this code will not
  * work as designed.
  */
@@ -2410,7 +2472,8 @@ void pcie_bus_configure_settings(struct pci_bus *bus)
         if (!pci_is_pcie(bus->self))
                 return;
 
-        /* FIXME - Peer to peer DMA is possible, though the endpoint would need
+        /*
+         * FIXME - Peer to peer DMA is possible, though the endpoint would need
          * to be aware of the MPS of the destination.  To work around this,
          * simply force the MPS of the entire system to the smallest possible.
          */
@@ -2464,7 +2527,7 @@ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
         for (devfn = 0; devfn < 0x100; devfn += 8)
                 pci_scan_slot(bus, devfn);
 
-        /* Reserve buses for SR-IOV capability. */
+        /* Reserve buses for SR-IOV capability */
         used_buses = pci_iov_bus_range(bus);
         max += used_buses;
 
@@ -2506,6 +2569,7 @@ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
                 unsigned int buses = 0;
 
                 if (!hotplug_bridges && normal_bridges == 1) {
+
                         /*
                          * There is only one bridge on the bus (upstream
                          * port) so it gets all available buses which it
@@ -2514,6 +2578,7 @@ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
                          */
                         buses = available_buses;
                 } else if (dev->is_hotplug_bridge) {
+
                         /*
                          * Distribute the extra buses between hotplug
                          * bridges if any.
@@ -2572,8 +2637,8 @@ unsigned int pci_scan_child_bus(struct pci_bus *bus)
 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
 
 /**
- * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
- * @bridge: Host bridge to set up.
+ * pcibios_root_bridge_prepare - Platform-specific host bridge setup
+ * @bridge: Host bridge to set up
  *
  * Default empty implementation.  Replace with an architecture-specific setup
  * routine, if necessary.
@@ -2620,6 +2685,39 @@ err_out:
 }
 EXPORT_SYMBOL_GPL(pci_create_root_bus);
 
+int pci_host_probe(struct pci_host_bridge *bridge)
+{
+        struct pci_bus *bus, *child;
+        int ret;
+
+        ret = pci_scan_root_bus_bridge(bridge);
+        if (ret < 0) {
+                dev_err(bridge->dev.parent, "Scanning root bridge failed");
+                return ret;
+        }
+
+        bus = bridge->bus;
+
+        /*
+         * We insert PCI resources into the iomem_resource and
+         * ioport_resource trees in either pci_bus_claim_resources()
+         * or pci_bus_assign_resources().
+         */
+        if (pci_has_flag(PCI_PROBE_ONLY)) {
+                pci_bus_claim_resources(bus);
+        } else {
+                pci_bus_size_bridges(bus);
+                pci_bus_assign_resources(bus);
+
+                list_for_each_entry(child, &bus->children, node)
+                        pcie_bus_configure_settings(child);
+        }
+
+        pci_bus_add_devices(bus);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(pci_host_probe);
+
 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
 {
         struct resource *res = &b->busn_res;
@@ -2776,7 +2874,7 @@ struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
 EXPORT_SYMBOL(pci_scan_bus);
 
 /**
- * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
+ * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
  * @bridge: PCI bridge for the bus to scan
  *
  * Scan a PCI bus and child buses for new devices, add them,
@@ -2801,11 +2899,11 @@ unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
 }
 
 /**
- * pci_rescan_bus - scan a PCI bus for devices.
+ * pci_rescan_bus - Scan a PCI bus for devices
  * @bus: PCI bus to scan
  *
- * Scan a PCI bus and child buses for new devices, adds them,
- * and enables them.
+ * Scan a PCI bus and child buses for new devices, add them,
+ * and enable them.
  *
  * Returns the max number of subordinate bus discovered.
  */
@@ -2874,7 +2972,7 @@ int pci_hp_add_bridge(struct pci_dev *dev)
                         break;
         }
         if (busnr-- > end) {
-                dev_err(&dev->dev, "No bus number available for hot-added bridge\n");
+                pci_err(dev, "No bus number available for hot-added bridge\n");
                 return -1;
         }