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path: root/drivers/pci/host/pcie-designware.c
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Diffstat (limited to 'drivers/pci/host/pcie-designware.c')
-rw-r--r--drivers/pci/host/pcie-designware.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 035f50c03281..bed19994c1e9 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -637,8 +637,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
637 } 637 }
638 } 638 }
639 639
640 pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp);
641
642 if (pp->ops->host_init) 640 if (pp->ops->host_init)
643 pp->ops->host_init(pp); 641 pp->ops->host_init(pp);
644 642
@@ -809,6 +807,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
809{ 807{
810 u32 val; 808 u32 val;
811 809
810 /* get iATU unroll support */
811 pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp);
812 dev_dbg(pp->dev, "iATU unroll: %s\n",
813 pp->iatu_unroll_enabled ? "enabled" : "disabled");
814
812 /* set the number of lanes */ 815 /* set the number of lanes */
813 val = dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL); 816 val = dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL);
814 val &= ~PORT_LINK_MODE_MASK; 817 val &= ~PORT_LINK_MODE_MASK;