1 files changed, 31 insertions, 10 deletions

diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index e5d9d77b778e..11b13864a406 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Synopsys DesignWare PCIe host controller driver
  *
@@ -5,15 +6,12 @@
  *              http://www.samsung.com
  *
  * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #ifndef _PCIE_DESIGNWARE_H
 #define _PCIE_DESIGNWARE_H
 
+#include <linux/dma-mapping.h>
 #include <linux/irq.h>
 #include <linux/msi.h>
 #include <linux/pci.h>
@@ -100,10 +98,14 @@
 
 #define MSI_MESSAGE_CONTROL             0x52
 #define MSI_CAP_MMC_SHIFT               1
+#define MSI_CAP_MMC_MASK                (7 << MSI_CAP_MMC_SHIFT)
 #define MSI_CAP_MME_SHIFT               4
+#define MSI_CAP_MSI_EN_MASK             0x1
 #define MSI_CAP_MME_MASK                (7 << MSI_CAP_MME_SHIFT)
 #define MSI_MESSAGE_ADDR_L32            0x54
 #define MSI_MESSAGE_ADDR_U32            0x58
+#define MSI_MESSAGE_DATA_32             0x58
+#define MSI_MESSAGE_DATA_64             0x5C
 
 /*
  * Maximum number of MSI IRQs can be 256 per controller. But keep
@@ -113,6 +115,10 @@
 #define MAX_MSI_IRQS                    32
 #define MAX_MSI_CTRLS                   (MAX_MSI_IRQS / 32)
 
+/* Maximum number of inbound/outbound iATUs */
+#define MAX_IATU_IN                     256
+#define MAX_IATU_OUT                    256
+
 struct pcie_port;
 struct dw_pcie;
 struct dw_pcie_ep;
@@ -168,7 +174,7 @@ struct pcie_port {
         const struct dw_pcie_host_ops *ops;
         int                     msi_irq;
         struct irq_domain       *irq_domain;
-        unsigned long           msi_data;
+        dma_addr_t              msi_data;
         DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
 };
 
@@ -180,8 +186,8 @@ enum dw_pcie_as_type {
 
 struct dw_pcie_ep_ops {
         void    (*ep_init)(struct dw_pcie_ep *ep);
-        int     (*raise_irq)(struct dw_pcie_ep *ep, enum pci_epc_irq_type type,
-                             u8 interrupt_num);
+        int     (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
+                             enum pci_epc_irq_type type, u8 interrupt_num);
 };
 
 struct dw_pcie_ep {
@@ -192,14 +198,16 @@ struct dw_pcie_ep {
         size_t                  page_size;
         u8                      bar_to_atu[6];
         phys_addr_t             *outbound_addr;
-        unsigned long           ib_window_map;
-        unsigned long           ob_window_map;
+        unsigned long           *ib_window_map;
+        unsigned long           *ob_window_map;
         u32                     num_ib_windows;
         u32                     num_ob_windows;
+        void __iomem            *msi_mem;
+        phys_addr_t             msi_mem_phys;
 };
 
 struct dw_pcie_ops {
-        u64     (*cpu_addr_fixup)(u64 cpu_addr);
+        u64     (*cpu_addr_fixup)(struct dw_pcie *pcie, u64 cpu_addr);
         u32     (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
                             size_t size);
         void    (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
@@ -334,6 +342,9 @@ static inline int dw_pcie_host_init(struct pcie_port *pp)
 void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
 int dw_pcie_ep_init(struct dw_pcie_ep *ep);
 void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
+int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
+                             u8 interrupt_num);
+void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
 #else
 static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
 {
@@ -347,5 +358,15 @@ static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
 {
 }
+
+static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
+                                           u8 interrupt_num)
+{
+        return 0;
+}
+
+static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
+{
+}
 #endif
 #endif /* _PCIE_DESIGNWARE_H */