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-rw-r--r--drivers/pci/controller/dwc/Kconfig4
-rw-r--r--drivers/pci/controller/dwc/pci-dra7xx.c81
-rw-r--r--drivers/pci/controller/dwc/pci-imx6.c224
-rw-r--r--drivers/pci/controller/dwc/pcie-designware-ep.c4
-rw-r--r--drivers/pci/controller/dwc/pcie-designware-host.c115
-rw-r--r--drivers/pci/controller/dwc/pcie-designware-plat.c2
-rw-r--r--drivers/pci/controller/dwc/pcie-designware.c6
-rw-r--r--drivers/pci/controller/dwc/pcie-designware.h59
-rw-r--r--drivers/pci/controller/dwc/pcie-qcom.c2
9 files changed, 373 insertions, 124 deletions
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index 548c58223868..6ea74b1c0d94 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -89,8 +89,8 @@ config PCI_EXYNOS
89 select PCIE_DW_HOST 89 select PCIE_DW_HOST
90 90
91config PCI_IMX6 91config PCI_IMX6
92 bool "Freescale i.MX6/7 PCIe controller" 92 bool "Freescale i.MX6/7/8 PCIe controller"
93 depends on SOC_IMX6Q || SOC_IMX7D || (ARM && COMPILE_TEST) 93 depends on SOC_IMX6Q || SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
94 depends on PCI_MSI_IRQ_DOMAIN 94 depends on PCI_MSI_IRQ_DOMAIN
95 select PCIE_DW_HOST 95 select PCIE_DW_HOST
96 96
diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
index 15620cfa617b..ae84a69ae63a 100644
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -81,6 +81,10 @@
81#define MSI_REQ_GRANT BIT(0) 81#define MSI_REQ_GRANT BIT(0)
82#define MSI_VECTOR_SHIFT 7 82#define MSI_VECTOR_SHIFT 7
83 83
84#define PCIE_1LANE_2LANE_SELECTION BIT(13)
85#define PCIE_B1C0_MODE_SEL BIT(2)
86#define PCIE_B0_B1_TSYNCEN BIT(0)
87
84struct dra7xx_pcie { 88struct dra7xx_pcie {
85 struct dw_pcie *pci; 89 struct dw_pcie *pci;
86 void __iomem *base; /* DT ti_conf */ 90 void __iomem *base; /* DT ti_conf */
@@ -93,6 +97,7 @@ struct dra7xx_pcie {
93 97
94struct dra7xx_pcie_of_data { 98struct dra7xx_pcie_of_data {
95 enum dw_pcie_device_mode mode; 99 enum dw_pcie_device_mode mode;
100 u32 b1co_mode_sel_mask;
96}; 101};
97 102
98#define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev) 103#define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
@@ -512,6 +517,10 @@ static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
512 int i; 517 int i;
513 518
514 for (i = 0; i < phy_count; i++) { 519 for (i = 0; i < phy_count; i++) {
520 ret = phy_set_mode(dra7xx->phy[i], PHY_MODE_PCIE);
521 if (ret < 0)
522 goto err_phy;
523
515 ret = phy_init(dra7xx->phy[i]); 524 ret = phy_init(dra7xx->phy[i]);
516 if (ret < 0) 525 if (ret < 0)
517 goto err_phy; 526 goto err_phy;
@@ -542,6 +551,26 @@ static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = {
542 .mode = DW_PCIE_EP_TYPE, 551 .mode = DW_PCIE_EP_TYPE,
543}; 552};
544 553
554static const struct dra7xx_pcie_of_data dra746_pcie_rc_of_data = {
555 .b1co_mode_sel_mask = BIT(2),
556 .mode = DW_PCIE_RC_TYPE,
557};
558
559static const struct dra7xx_pcie_of_data dra726_pcie_rc_of_data = {
560 .b1co_mode_sel_mask = GENMASK(3, 2),
561 .mode = DW_PCIE_RC_TYPE,
562};
563
564static const struct dra7xx_pcie_of_data dra746_pcie_ep_of_data = {
565 .b1co_mode_sel_mask = BIT(2),
566 .mode = DW_PCIE_EP_TYPE,
567};
568
569static const struct dra7xx_pcie_of_data dra726_pcie_ep_of_data = {
570 .b1co_mode_sel_mask = GENMASK(3, 2),
571 .mode = DW_PCIE_EP_TYPE,
572};
573
545static const struct of_device_id of_dra7xx_pcie_match[] = { 574static const struct of_device_id of_dra7xx_pcie_match[] = {
546 { 575 {
547 .compatible = "ti,dra7-pcie", 576 .compatible = "ti,dra7-pcie",
@@ -551,6 +580,22 @@ static const struct of_device_id of_dra7xx_pcie_match[] = {
551 .compatible = "ti,dra7-pcie-ep", 580 .compatible = "ti,dra7-pcie-ep",
552 .data = &dra7xx_pcie_ep_of_data, 581 .data = &dra7xx_pcie_ep_of_data,
553 }, 582 },
583 {
584 .compatible = "ti,dra746-pcie-rc",
585 .data = &dra746_pcie_rc_of_data,
586 },
587 {
588 .compatible = "ti,dra726-pcie-rc",
589 .data = &dra726_pcie_rc_of_data,
590 },
591 {
592 .compatible = "ti,dra746-pcie-ep",
593 .data = &dra746_pcie_ep_of_data,
594 },
595 {
596 .compatible = "ti,dra726-pcie-ep",
597 .data = &dra726_pcie_ep_of_data,
598 },
554 {}, 599 {},
555}; 600};
556 601
@@ -596,6 +641,34 @@ static int dra7xx_pcie_unaligned_memaccess(struct device *dev)
596 return ret; 641 return ret;
597} 642}
598 643
644static int dra7xx_pcie_configure_two_lane(struct device *dev,
645 u32 b1co_mode_sel_mask)
646{
647 struct device_node *np = dev->of_node;
648 struct regmap *pcie_syscon;
649 unsigned int pcie_reg;
650 u32 mask;
651 u32 val;
652
653 pcie_syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-lane-sel");
654 if (IS_ERR(pcie_syscon)) {
655 dev_err(dev, "unable to get ti,syscon-lane-sel\n");
656 return -EINVAL;
657 }
658
659 if (of_property_read_u32_index(np, "ti,syscon-lane-sel", 1,
660 &pcie_reg)) {
661 dev_err(dev, "couldn't get lane selection reg offset\n");
662 return -EINVAL;
663 }
664
665 mask = b1co_mode_sel_mask | PCIE_B0_B1_TSYNCEN;
666 val = PCIE_B1C0_MODE_SEL | PCIE_B0_B1_TSYNCEN;
667 regmap_update_bits(pcie_syscon, pcie_reg, mask, val);
668
669 return 0;
670}
671
599static int __init dra7xx_pcie_probe(struct platform_device *pdev) 672static int __init dra7xx_pcie_probe(struct platform_device *pdev)
600{ 673{
601 u32 reg; 674 u32 reg;
@@ -616,6 +689,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
616 const struct of_device_id *match; 689 const struct of_device_id *match;
617 const struct dra7xx_pcie_of_data *data; 690 const struct dra7xx_pcie_of_data *data;
618 enum dw_pcie_device_mode mode; 691 enum dw_pcie_device_mode mode;
692 u32 b1co_mode_sel_mask;
619 693
620 match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev); 694 match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev);
621 if (!match) 695 if (!match)
@@ -623,6 +697,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
623 697
624 data = (struct dra7xx_pcie_of_data *)match->data; 698 data = (struct dra7xx_pcie_of_data *)match->data;
625 mode = (enum dw_pcie_device_mode)data->mode; 699 mode = (enum dw_pcie_device_mode)data->mode;
700 b1co_mode_sel_mask = data->b1co_mode_sel_mask;
626 701
627 dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL); 702 dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
628 if (!dra7xx) 703 if (!dra7xx)
@@ -678,6 +753,12 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
678 dra7xx->pci = pci; 753 dra7xx->pci = pci;
679 dra7xx->phy_count = phy_count; 754 dra7xx->phy_count = phy_count;
680 755
756 if (phy_count == 2) {
757 ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask);
758 if (ret < 0)
759 dra7xx->phy_count = 1; /* Fallback to x1 lane mode */
760 }
761
681 ret = dra7xx_pcie_enable_phy(dra7xx); 762 ret = dra7xx_pcie_enable_phy(dra7xx);
682 if (ret) { 763 if (ret) {
683 dev_err(dev, "failed to enable phy\n"); 764 dev_err(dev, "failed to enable phy\n");
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 52e47dac028f..5ae75f25c6fc 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -8,6 +8,7 @@
8 * Author: Sean Cross <xobs@kosagi.com> 8 * Author: Sean Cross <xobs@kosagi.com>
9 */ 9 */
10 10
11#include <linux/bitfield.h>
11#include <linux/clk.h> 12#include <linux/clk.h>
12#include <linux/delay.h> 13#include <linux/delay.h>
13#include <linux/gpio.h> 14#include <linux/gpio.h>
@@ -18,6 +19,7 @@
18#include <linux/module.h> 19#include <linux/module.h>
19#include <linux/of_gpio.h> 20#include <linux/of_gpio.h>
20#include <linux/of_device.h> 21#include <linux/of_device.h>
22#include <linux/of_address.h>
21#include <linux/pci.h> 23#include <linux/pci.h>
22#include <linux/platform_device.h> 24#include <linux/platform_device.h>
23#include <linux/regmap.h> 25#include <linux/regmap.h>
@@ -32,6 +34,12 @@
32 34
33#include "pcie-designware.h" 35#include "pcie-designware.h"
34 36
37#define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
38#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
39#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
40#define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
41#define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000
42
35#define to_imx6_pcie(x) dev_get_drvdata((x)->dev) 43#define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
36 44
37enum imx6_pcie_variants { 45enum imx6_pcie_variants {
@@ -39,6 +47,15 @@ enum imx6_pcie_variants {
39 IMX6SX, 47 IMX6SX,
40 IMX6QP, 48 IMX6QP,
41 IMX7D, 49 IMX7D,
50 IMX8MQ,
51};
52
53#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
54#define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1)
55
56struct imx6_pcie_drvdata {
57 enum imx6_pcie_variants variant;
58 u32 flags;
42}; 59};
43 60
44struct imx6_pcie { 61struct imx6_pcie {
@@ -49,11 +66,12 @@ struct imx6_pcie {
49 struct clk *pcie_phy; 66 struct clk *pcie_phy;
50 struct clk *pcie_inbound_axi; 67 struct clk *pcie_inbound_axi;
51 struct clk *pcie; 68 struct clk *pcie;
69 struct clk *pcie_aux;
52 struct regmap *iomuxc_gpr; 70 struct regmap *iomuxc_gpr;
71 u32 controller_id;
53 struct reset_control *pciephy_reset; 72 struct reset_control *pciephy_reset;
54 struct reset_control *apps_reset; 73 struct reset_control *apps_reset;
55 struct reset_control *turnoff_reset; 74 struct reset_control *turnoff_reset;
56 enum imx6_pcie_variants variant;
57 u32 tx_deemph_gen1; 75 u32 tx_deemph_gen1;
58 u32 tx_deemph_gen2_3p5db; 76 u32 tx_deemph_gen2_3p5db;
59 u32 tx_deemph_gen2_6db; 77 u32 tx_deemph_gen2_6db;
@@ -61,11 +79,13 @@ struct imx6_pcie {
61 u32 tx_swing_low; 79 u32 tx_swing_low;
62 int link_gen; 80 int link_gen;
63 struct regulator *vpcie; 81 struct regulator *vpcie;
82 void __iomem *phy_base;
64 83
65 /* power domain for pcie */ 84 /* power domain for pcie */
66 struct device *pd_pcie; 85 struct device *pd_pcie;
67 /* power domain for pcie phy */ 86 /* power domain for pcie phy */
68 struct device *pd_pcie_phy; 87 struct device *pd_pcie_phy;
88 const struct imx6_pcie_drvdata *drvdata;
69}; 89};
70 90
71/* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ 91/* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
@@ -101,7 +121,6 @@ struct imx6_pcie {
101#define PCIE_PHY_STAT_ACK_LOC 16 121#define PCIE_PHY_STAT_ACK_LOC 16
102 122
103#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C 123#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
104#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
105 124
106/* PHY registers (not memory-mapped) */ 125/* PHY registers (not memory-mapped) */
107#define PCIE_PHY_ATEOVRD 0x10 126#define PCIE_PHY_ATEOVRD 0x10
@@ -117,6 +136,23 @@ struct imx6_pcie {
117#define PCIE_PHY_RX_ASIC_OUT 0x100D 136#define PCIE_PHY_RX_ASIC_OUT 0x100D
118#define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0) 137#define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
119 138
139/* iMX7 PCIe PHY registers */
140#define PCIE_PHY_CMN_REG4 0x14
141/* These are probably the bits that *aren't* DCC_FB_EN */
142#define PCIE_PHY_CMN_REG4_DCC_FB_EN 0x29
143
144#define PCIE_PHY_CMN_REG15 0x54
145#define PCIE_PHY_CMN_REG15_DLY_4 BIT(2)
146#define PCIE_PHY_CMN_REG15_PLL_PD BIT(5)
147#define PCIE_PHY_CMN_REG15_OVRD_PLL_PD BIT(7)
148
149#define PCIE_PHY_CMN_REG24 0x90
150#define PCIE_PHY_CMN_REG24_RX_EQ BIT(6)
151#define PCIE_PHY_CMN_REG24_RX_EQ_SEL BIT(3)
152
153#define PCIE_PHY_CMN_REG26 0x98
154#define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC
155
120#define PHY_RX_OVRD_IN_LO 0x1005 156#define PHY_RX_OVRD_IN_LO 0x1005
121#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) 157#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
122#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) 158#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
@@ -251,6 +287,9 @@ static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
251{ 287{
252 u32 tmp; 288 u32 tmp;
253 289
290 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
291 return;
292
254 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 293 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
255 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | 294 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
256 PHY_RX_OVRD_IN_LO_RX_PLL_EN); 295 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
@@ -264,6 +303,7 @@ static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
264 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 303 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
265} 304}
266 305
306#ifdef CONFIG_ARM
267/* Added for PCI abort handling */ 307/* Added for PCI abort handling */
268static int imx6q_pcie_abort_handler(unsigned long addr, 308static int imx6q_pcie_abort_handler(unsigned long addr,
269 unsigned int fsr, struct pt_regs *regs) 309 unsigned int fsr, struct pt_regs *regs)
@@ -297,6 +337,7 @@ static int imx6q_pcie_abort_handler(unsigned long addr,
297 337
298 return 1; 338 return 1;
299} 339}
340#endif
300 341
301static int imx6_pcie_attach_pd(struct device *dev) 342static int imx6_pcie_attach_pd(struct device *dev)
302{ 343{
@@ -339,8 +380,9 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
339{ 380{
340 struct device *dev = imx6_pcie->pci->dev; 381 struct device *dev = imx6_pcie->pci->dev;
341 382
342 switch (imx6_pcie->variant) { 383 switch (imx6_pcie->drvdata->variant) {
343 case IMX7D: 384 case IMX7D:
385 case IMX8MQ:
344 reset_control_assert(imx6_pcie->pciephy_reset); 386 reset_control_assert(imx6_pcie->pciephy_reset);
345 reset_control_assert(imx6_pcie->apps_reset); 387 reset_control_assert(imx6_pcie->apps_reset);
346 break; 388 break;
@@ -375,13 +417,20 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
375 } 417 }
376} 418}
377 419
420static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
421{
422 WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ);
423 return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
424}
425
378static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) 426static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
379{ 427{
380 struct dw_pcie *pci = imx6_pcie->pci; 428 struct dw_pcie *pci = imx6_pcie->pci;
381 struct device *dev = pci->dev; 429 struct device *dev = pci->dev;
430 unsigned int offset;
382 int ret = 0; 431 int ret = 0;
383 432
384 switch (imx6_pcie->variant) { 433 switch (imx6_pcie->drvdata->variant) {
385 case IMX6SX: 434 case IMX6SX:
386 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi); 435 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
387 if (ret) { 436 if (ret) {
@@ -409,6 +458,25 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
409 break; 458 break;
410 case IMX7D: 459 case IMX7D:
411 break; 460 break;
461 case IMX8MQ:
462 ret = clk_prepare_enable(imx6_pcie->pcie_aux);
463 if (ret) {
464 dev_err(dev, "unable to enable pcie_aux clock\n");
465 break;
466 }
467
468 offset = imx6_pcie_grp_offset(imx6_pcie);
469 /*
470 * Set the over ride low and enabled
471 * make sure that REF_CLK is turned on.
472 */
473 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
474 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
475 0);
476 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
477 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
478 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
479 break;
412 } 480 }
413 481
414 return ret; 482 return ret;
@@ -484,9 +552,32 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
484 !imx6_pcie->gpio_active_high); 552 !imx6_pcie->gpio_active_high);
485 } 553 }
486 554
487 switch (imx6_pcie->variant) { 555 switch (imx6_pcie->drvdata->variant) {
556 case IMX8MQ:
557 reset_control_deassert(imx6_pcie->pciephy_reset);
558 break;
488 case IMX7D: 559 case IMX7D:
489 reset_control_deassert(imx6_pcie->pciephy_reset); 560 reset_control_deassert(imx6_pcie->pciephy_reset);
561
562 /* Workaround for ERR010728, failure of PCI-e PLL VCO to
563 * oscillate, especially when cold. This turns off "Duty-cycle
564 * Corrector" and other mysterious undocumented things.
565 */
566 if (likely(imx6_pcie->phy_base)) {
567 /* De-assert DCC_FB_EN */
568 writel(PCIE_PHY_CMN_REG4_DCC_FB_EN,
569 imx6_pcie->phy_base + PCIE_PHY_CMN_REG4);
570 /* Assert RX_EQS and RX_EQS_SEL */
571 writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL
572 | PCIE_PHY_CMN_REG24_RX_EQ,
573 imx6_pcie->phy_base + PCIE_PHY_CMN_REG24);
574 /* Assert ATT_MODE */
575 writel(PCIE_PHY_CMN_REG26_ATT_MODE,
576 imx6_pcie->phy_base + PCIE_PHY_CMN_REG26);
577 } else {
578 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
579 }
580
490 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie); 581 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
491 break; 582 break;
492 case IMX6SX: 583 case IMX6SX:
@@ -520,9 +611,37 @@ err_pcie_phy:
520 } 611 }
521} 612}
522 613
614static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
615{
616 unsigned int mask, val;
617
618 if (imx6_pcie->drvdata->variant == IMX8MQ &&
619 imx6_pcie->controller_id == 1) {
620 mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
621 val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
622 PCI_EXP_TYPE_ROOT_PORT);
623 } else {
624 mask = IMX6Q_GPR12_DEVICE_TYPE;
625 val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE,
626 PCI_EXP_TYPE_ROOT_PORT);
627 }
628
629 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
630}
631
523static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) 632static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
524{ 633{
525 switch (imx6_pcie->variant) { 634 switch (imx6_pcie->drvdata->variant) {
635 case IMX8MQ:
636 /*
637 * TODO: Currently this code assumes external
638 * oscillator is being used
639 */
640 regmap_update_bits(imx6_pcie->iomuxc_gpr,
641 imx6_pcie_grp_offset(imx6_pcie),
642 IMX8MQ_GPR_PCIE_REF_USE_PAD,
643 IMX8MQ_GPR_PCIE_REF_USE_PAD);
644 break;
526 case IMX7D: 645 case IMX7D:
527 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 646 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
528 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); 647 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
@@ -558,8 +677,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
558 break; 677 break;
559 } 678 }
560 679
561 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 680 imx6_pcie_configure_type(imx6_pcie);
562 IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
563} 681}
564 682
565static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) 683static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
@@ -568,6 +686,9 @@ static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
568 int mult, div; 686 int mult, div;
569 u32 val; 687 u32 val;
570 688
689 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
690 return 0;
691
571 switch (phy_rate) { 692 switch (phy_rate) {
572 case 125000000: 693 case 125000000:
573 /* 694 /*
@@ -644,7 +765,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
644{ 765{
645 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 766 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
646 767
647 switch (imx6_pcie->variant) { 768 switch (imx6_pcie->drvdata->variant) {
648 case IMX6Q: 769 case IMX6Q:
649 case IMX6SX: 770 case IMX6SX:
650 case IMX6QP: 771 case IMX6QP:
@@ -653,6 +774,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
653 IMX6Q_GPR12_PCIE_CTL_2); 774 IMX6Q_GPR12_PCIE_CTL_2);
654 break; 775 break;
655 case IMX7D: 776 case IMX7D:
777 case IMX8MQ:
656 reset_control_deassert(imx6_pcie->apps_reset); 778 reset_control_deassert(imx6_pcie->apps_reset);
657 break; 779 break;
658 } 780 }
@@ -697,7 +819,8 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
697 tmp |= PORT_LOGIC_SPEED_CHANGE; 819 tmp |= PORT_LOGIC_SPEED_CHANGE;
698 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); 820 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
699 821
700 if (imx6_pcie->variant != IMX7D) { 822 if (imx6_pcie->drvdata->flags &
823 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) {
701 /* 824 /*
702 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently 825 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently
703 * from i.MX6 family when no link speed transition 826 * from i.MX6 family when no link speed transition
@@ -794,7 +917,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
794{ 917{
795 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 918 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
796 919
797 switch (imx6_pcie->variant) { 920 switch (imx6_pcie->drvdata->variant) {
798 case IMX6SX: 921 case IMX6SX:
799 case IMX6QP: 922 case IMX6QP:
800 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 923 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
@@ -820,7 +943,7 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
820 } 943 }
821 944
822 /* Others poke directly at IOMUXC registers */ 945 /* Others poke directly at IOMUXC registers */
823 switch (imx6_pcie->variant) { 946 switch (imx6_pcie->drvdata->variant) {
824 case IMX6SX: 947 case IMX6SX:
825 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 948 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
826 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 949 IMX6SX_GPR12_PCIE_PM_TURN_OFF,
@@ -850,7 +973,7 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
850 clk_disable_unprepare(imx6_pcie->pcie_phy); 973 clk_disable_unprepare(imx6_pcie->pcie_phy);
851 clk_disable_unprepare(imx6_pcie->pcie_bus); 974 clk_disable_unprepare(imx6_pcie->pcie_bus);
852 975
853 switch (imx6_pcie->variant) { 976 switch (imx6_pcie->drvdata->variant) {
854 case IMX6SX: 977 case IMX6SX:
855 clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); 978 clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
856 break; 979 break;
@@ -859,6 +982,9 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
859 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 982 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
860 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); 983 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
861 break; 984 break;
985 case IMX8MQ:
986 clk_disable_unprepare(imx6_pcie->pcie_aux);
987 break;
862 default: 988 default:
863 break; 989 break;
864 } 990 }
@@ -866,8 +992,8 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
866 992
867static inline bool imx6_pcie_supports_suspend(struct imx6_pcie *imx6_pcie) 993static inline bool imx6_pcie_supports_suspend(struct imx6_pcie *imx6_pcie)
868{ 994{
869 return (imx6_pcie->variant == IMX7D || 995 return (imx6_pcie->drvdata->variant == IMX7D ||
870 imx6_pcie->variant == IMX6SX); 996 imx6_pcie->drvdata->variant == IMX6SX);
871} 997}
872 998
873static int imx6_pcie_suspend_noirq(struct device *dev) 999static int imx6_pcie_suspend_noirq(struct device *dev)
@@ -916,6 +1042,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
916 struct device *dev = &pdev->dev; 1042 struct device *dev = &pdev->dev;
917 struct dw_pcie *pci; 1043 struct dw_pcie *pci;
918 struct imx6_pcie *imx6_pcie; 1044 struct imx6_pcie *imx6_pcie;
1045 struct device_node *np;
919 struct resource *dbi_base; 1046 struct resource *dbi_base;
920 struct device_node *node = dev->of_node; 1047 struct device_node *node = dev->of_node;
921 int ret; 1048 int ret;
@@ -933,8 +1060,24 @@ static int imx6_pcie_probe(struct platform_device *pdev)
933 pci->ops = &dw_pcie_ops; 1060 pci->ops = &dw_pcie_ops;
934 1061
935 imx6_pcie->pci = pci; 1062 imx6_pcie->pci = pci;
936 imx6_pcie->variant = 1063 imx6_pcie->drvdata = of_device_get_match_data(dev);
937 (enum imx6_pcie_variants)of_device_get_match_data(dev); 1064
1065 /* Find the PHY if one is defined, only imx7d uses it */
1066 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0);
1067 if (np) {
1068 struct resource res;
1069
1070 ret = of_address_to_resource(np, 0, &res);
1071 if (ret) {
1072 dev_err(dev, "Unable to map PCIe PHY\n");
1073 return ret;
1074 }
1075 imx6_pcie->phy_base = devm_ioremap_resource(dev, &res);
1076 if (IS_ERR(imx6_pcie->phy_base)) {
1077 dev_err(dev, "Unable to map PCIe PHY\n");
1078 return PTR_ERR(imx6_pcie->phy_base);
1079 }
1080 }
938 1081
939 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1082 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
940 pci->dbi_base = devm_ioremap_resource(dev, dbi_base); 1083 pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
@@ -978,7 +1121,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
978 return PTR_ERR(imx6_pcie->pcie); 1121 return PTR_ERR(imx6_pcie->pcie);
979 } 1122 }
980 1123
981 switch (imx6_pcie->variant) { 1124 switch (imx6_pcie->drvdata->variant) {
982 case IMX6SX: 1125 case IMX6SX:
983 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev, 1126 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
984 "pcie_inbound_axi"); 1127 "pcie_inbound_axi");
@@ -987,7 +1130,17 @@ static int imx6_pcie_probe(struct platform_device *pdev)
987 return PTR_ERR(imx6_pcie->pcie_inbound_axi); 1130 return PTR_ERR(imx6_pcie->pcie_inbound_axi);
988 } 1131 }
989 break; 1132 break;
1133 case IMX8MQ:
1134 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
1135 if (IS_ERR(imx6_pcie->pcie_aux)) {
1136 dev_err(dev, "pcie_aux clock source missing or invalid\n");
1137 return PTR_ERR(imx6_pcie->pcie_aux);
1138 }
1139 /* fall through */
990 case IMX7D: 1140 case IMX7D:
1141 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
1142 imx6_pcie->controller_id = 1;
1143
991 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, 1144 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev,
992 "pciephy"); 1145 "pciephy");
993 if (IS_ERR(imx6_pcie->pciephy_reset)) { 1146 if (IS_ERR(imx6_pcie->pciephy_reset)) {
@@ -1084,11 +1237,36 @@ static void imx6_pcie_shutdown(struct platform_device *pdev)
1084 imx6_pcie_assert_core_reset(imx6_pcie); 1237 imx6_pcie_assert_core_reset(imx6_pcie);
1085} 1238}
1086 1239
1240static const struct imx6_pcie_drvdata drvdata[] = {
1241 [IMX6Q] = {
1242 .variant = IMX6Q,
1243 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1244 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
1245 },
1246 [IMX6SX] = {
1247 .variant = IMX6SX,
1248 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1249 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
1250 },
1251 [IMX6QP] = {
1252 .variant = IMX6QP,
1253 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1254 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
1255 },
1256 [IMX7D] = {
1257 .variant = IMX7D,
1258 },
1259 [IMX8MQ] = {
1260 .variant = IMX8MQ,
1261 },
1262};
1263
1087static const struct of_device_id imx6_pcie_of_match[] = { 1264static const struct of_device_id imx6_pcie_of_match[] = {
1088 { .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, }, 1265 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
1089 { .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, }, 1266 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
1090 { .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, }, 1267 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
1091 { .compatible = "fsl,imx7d-pcie", .data = (void *)IMX7D, }, 1268 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
1269 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } ,
1092 {}, 1270 {},
1093}; 1271};
1094 1272
@@ -1105,6 +1283,7 @@ static struct platform_driver imx6_pcie_driver = {
1105 1283
1106static int __init imx6_pcie_init(void) 1284static int __init imx6_pcie_init(void)
1107{ 1285{
1286#ifdef CONFIG_ARM
1108 /* 1287 /*
1109 * Since probe() can be deferred we need to make sure that 1288 * Since probe() can be deferred we need to make sure that
1110 * hook_fault_code is not called after __init memory is freed 1289 * hook_fault_code is not called after __init memory is freed
@@ -1114,6 +1293,7 @@ static int __init imx6_pcie_init(void)
1114 */ 1293 */
1115 hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0, 1294 hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0,
1116 "external abort on non-linefetch"); 1295 "external abort on non-linefetch");
1296#endif
1117 1297
1118 return platform_driver_register(&imx6_pcie_driver); 1298 return platform_driver_register(&imx6_pcie_driver);
1119} 1299}
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 7a2925a16ab8..24f5a775ad34 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -477,8 +477,10 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
477 477
478 iounmap(msix_tbl); 478 iounmap(msix_tbl);
479 479
480 if (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT) 480 if (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT) {
481 dev_dbg(pci->dev, "MSI-X entry ctrl set\n");
481 return -EPERM; 482 return -EPERM;
483 }
482 484
483 ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, 485 ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
484 epc->mem->page_size); 486 epc->mem->page_size);
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 721d60a5d9e4..25087d3c9a82 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -120,9 +120,9 @@ static void dw_chained_msi_isr(struct irq_desc *desc)
120 chained_irq_exit(chip, desc); 120 chained_irq_exit(chip, desc);
121} 121}
122 122
123static void dw_pci_setup_msi_msg(struct irq_data *data, struct msi_msg *msg) 123static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
124{ 124{
125 struct pcie_port *pp = irq_data_get_irq_chip_data(data); 125 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
126 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 126 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
127 u64 msi_target; 127 u64 msi_target;
128 128
@@ -135,61 +135,61 @@ static void dw_pci_setup_msi_msg(struct irq_data *data, struct msi_msg *msg)
135 msg->address_hi = upper_32_bits(msi_target); 135 msg->address_hi = upper_32_bits(msi_target);
136 136
137 if (pp->ops->get_msi_data) 137 if (pp->ops->get_msi_data)
138 msg->data = pp->ops->get_msi_data(pp, data->hwirq); 138 msg->data = pp->ops->get_msi_data(pp, d->hwirq);
139 else 139 else
140 msg->data = data->hwirq; 140 msg->data = d->hwirq;
141 141
142 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", 142 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
143 (int)data->hwirq, msg->address_hi, msg->address_lo); 143 (int)d->hwirq, msg->address_hi, msg->address_lo);
144} 144}
145 145
146static int dw_pci_msi_set_affinity(struct irq_data *irq_data, 146static int dw_pci_msi_set_affinity(struct irq_data *d,
147 const struct cpumask *mask, bool force) 147 const struct cpumask *mask, bool force)
148{ 148{
149 return -EINVAL; 149 return -EINVAL;
150} 150}
151 151
152static void dw_pci_bottom_mask(struct irq_data *data) 152static void dw_pci_bottom_mask(struct irq_data *d)
153{ 153{
154 struct pcie_port *pp = irq_data_get_irq_chip_data(data); 154 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
155 unsigned int res, bit, ctrl; 155 unsigned int res, bit, ctrl;
156 unsigned long flags; 156 unsigned long flags;
157 157
158 raw_spin_lock_irqsave(&pp->lock, flags); 158 raw_spin_lock_irqsave(&pp->lock, flags);
159 159
160 if (pp->ops->msi_clear_irq) { 160 if (pp->ops->msi_clear_irq) {
161 pp->ops->msi_clear_irq(pp, data->hwirq); 161 pp->ops->msi_clear_irq(pp, d->hwirq);
162 } else { 162 } else {
163 ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL; 163 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
164 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 164 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
165 bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL; 165 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
166 166
167 pp->irq_status[ctrl] &= ~(1 << bit); 167 pp->irq_mask[ctrl] |= BIT(bit);
168 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, 168 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
169 ~pp->irq_status[ctrl]); 169 pp->irq_mask[ctrl]);
170 } 170 }
171 171
172 raw_spin_unlock_irqrestore(&pp->lock, flags); 172 raw_spin_unlock_irqrestore(&pp->lock, flags);
173} 173}
174 174
175static void dw_pci_bottom_unmask(struct irq_data *data) 175static void dw_pci_bottom_unmask(struct irq_data *d)
176{ 176{
177 struct pcie_port *pp = irq_data_get_irq_chip_data(data); 177 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
178 unsigned int res, bit, ctrl; 178 unsigned int res, bit, ctrl;
179 unsigned long flags; 179 unsigned long flags;
180 180
181 raw_spin_lock_irqsave(&pp->lock, flags); 181 raw_spin_lock_irqsave(&pp->lock, flags);
182 182
183 if (pp->ops->msi_set_irq) { 183 if (pp->ops->msi_set_irq) {
184 pp->ops->msi_set_irq(pp, data->hwirq); 184 pp->ops->msi_set_irq(pp, d->hwirq);
185 } else { 185 } else {
186 ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL; 186 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
187 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 187 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
188 bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL; 188 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
189 189
190 pp->irq_status[ctrl] |= 1 << bit; 190 pp->irq_mask[ctrl] &= ~BIT(bit);
191 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, 191 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
192 ~pp->irq_status[ctrl]); 192 pp->irq_mask[ctrl]);
193 } 193 }
194 194
195 raw_spin_unlock_irqrestore(&pp->lock, flags); 195 raw_spin_unlock_irqrestore(&pp->lock, flags);
@@ -207,7 +207,7 @@ static void dw_pci_bottom_ack(struct irq_data *d)
207 207
208 raw_spin_lock_irqsave(&pp->lock, flags); 208 raw_spin_lock_irqsave(&pp->lock, flags);
209 209
210 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, 1 << bit); 210 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, BIT(bit));
211 211
212 if (pp->ops->msi_irq_ack) 212 if (pp->ops->msi_irq_ack)
213 pp->ops->msi_irq_ack(d->hwirq, pp); 213 pp->ops->msi_irq_ack(d->hwirq, pp);
@@ -255,13 +255,13 @@ static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
255static void dw_pcie_irq_domain_free(struct irq_domain *domain, 255static void dw_pcie_irq_domain_free(struct irq_domain *domain,
256 unsigned int virq, unsigned int nr_irqs) 256 unsigned int virq, unsigned int nr_irqs)
257{ 257{
258 struct irq_data *data = irq_domain_get_irq_data(domain, virq); 258 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
259 struct pcie_port *pp = irq_data_get_irq_chip_data(data); 259 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
260 unsigned long flags; 260 unsigned long flags;
261 261
262 raw_spin_lock_irqsave(&pp->lock, flags); 262 raw_spin_lock_irqsave(&pp->lock, flags);
263 263
264 bitmap_release_region(pp->msi_irq_in_use, data->hwirq, 264 bitmap_release_region(pp->msi_irq_in_use, d->hwirq,
265 order_base_2(nr_irqs)); 265 order_base_2(nr_irqs));
266 266
267 raw_spin_unlock_irqrestore(&pp->lock, flags); 267 raw_spin_unlock_irqrestore(&pp->lock, flags);
@@ -439,7 +439,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
439 if (ret) 439 if (ret)
440 pci->num_viewport = 2; 440 pci->num_viewport = 2;
441 441
442 if (IS_ENABLED(CONFIG_PCI_MSI)) { 442 if (IS_ENABLED(CONFIG_PCI_MSI) && pci_msi_enabled()) {
443 /* 443 /*
444 * If a specific SoC driver needs to change the 444 * If a specific SoC driver needs to change the
445 * default number of vectors, it needs to implement 445 * default number of vectors, it needs to implement
@@ -512,8 +512,9 @@ error:
512 return ret; 512 return ret;
513} 513}
514 514
515static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, 515static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus,
516 u32 devfn, int where, int size, u32 *val) 516 u32 devfn, int where, int size, u32 *val,
517 bool write)
517{ 518{
518 int ret, type; 519 int ret, type;
519 u32 busdev, cfg_size; 520 u32 busdev, cfg_size;
@@ -521,9 +522,6 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
521 void __iomem *va_cfg_base; 522 void __iomem *va_cfg_base;
522 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 523 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
523 524
524 if (pp->ops->rd_other_conf)
525 return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
526
527 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | 525 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
528 PCIE_ATU_FUNC(PCI_FUNC(devfn)); 526 PCIE_ATU_FUNC(PCI_FUNC(devfn));
529 527
@@ -542,7 +540,11 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
542 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, 540 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
543 type, cpu_addr, 541 type, cpu_addr,
544 busdev, cfg_size); 542 busdev, cfg_size);
545 ret = dw_pcie_read(va_cfg_base + where, size, val); 543 if (write)
544 ret = dw_pcie_write(va_cfg_base + where, size, *val);
545 else
546 ret = dw_pcie_read(va_cfg_base + where, size, val);
547
546 if (pci->num_viewport <= 2) 548 if (pci->num_viewport <= 2)
547 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, 549 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
548 PCIE_ATU_TYPE_IO, pp->io_base, 550 PCIE_ATU_TYPE_IO, pp->io_base,
@@ -551,43 +553,26 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
551 return ret; 553 return ret;
552} 554}
553 555
556static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
557 u32 devfn, int where, int size, u32 *val)
558{
559 if (pp->ops->rd_other_conf)
560 return pp->ops->rd_other_conf(pp, bus, devfn, where,
561 size, val);
562
563 return dw_pcie_access_other_conf(pp, bus, devfn, where, size, val,
564 false);
565}
566
554static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, 567static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
555 u32 devfn, int where, int size, u32 val) 568 u32 devfn, int where, int size, u32 val)
556{ 569{
557 int ret, type;
558 u32 busdev, cfg_size;
559 u64 cpu_addr;
560 void __iomem *va_cfg_base;
561 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
562
563 if (pp->ops->wr_other_conf) 570 if (pp->ops->wr_other_conf)
564 return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val); 571 return pp->ops->wr_other_conf(pp, bus, devfn, where,
565 572 size, val);
566 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
567 PCIE_ATU_FUNC(PCI_FUNC(devfn));
568 573
569 if (bus->parent->number == pp->root_bus_nr) { 574 return dw_pcie_access_other_conf(pp, bus, devfn, where, size, &val,
570 type = PCIE_ATU_TYPE_CFG0; 575 true);
571 cpu_addr = pp->cfg0_base;
572 cfg_size = pp->cfg0_size;
573 va_cfg_base = pp->va_cfg0_base;
574 } else {
575 type = PCIE_ATU_TYPE_CFG1;
576 cpu_addr = pp->cfg1_base;
577 cfg_size = pp->cfg1_size;
578 va_cfg_base = pp->va_cfg1_base;
579 }
580
581 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
582 type, cpu_addr,
583 busdev, cfg_size);
584 ret = dw_pcie_write(va_cfg_base + where, size, val);
585 if (pci->num_viewport <= 2)
586 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
587 PCIE_ATU_TYPE_IO, pp->io_base,
588 pp->io_bus_addr, pp->io_size);
589
590 return ret;
591} 576}
592 577
593static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus, 578static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus,
@@ -665,13 +650,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
665 650
666 /* Initialize IRQ Status array */ 651 /* Initialize IRQ Status array */
667 for (ctrl = 0; ctrl < num_ctrls; ctrl++) { 652 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
653 pp->irq_mask[ctrl] = ~0;
668 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + 654 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK +
669 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 655 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
670 4, ~0); 656 4, pp->irq_mask[ctrl]);
671 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + 657 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE +
672 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 658 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
673 4, ~0); 659 4, ~0);
674 pp->irq_status[ctrl] = 0;
675 } 660 }
676 661
677 /* Setup RC BARs */ 662 /* Setup RC BARs */
diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
index 3be87126aef3..932dbd0b34b6 100644
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -13,11 +13,9 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/of_device.h> 15#include <linux/of_device.h>
16#include <linux/of_gpio.h>
17#include <linux/pci.h> 16#include <linux/pci.h>
18#include <linux/platform_device.h> 17#include <linux/platform_device.h>
19#include <linux/resource.h> 18#include <linux/resource.h>
20#include <linux/signal.h>
21#include <linux/types.h> 19#include <linux/types.h>
22#include <linux/regmap.h> 20#include <linux/regmap.h>
23 21
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 93ef8c31fb39..31f6331ca46f 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -22,7 +22,7 @@
22 22
23int dw_pcie_read(void __iomem *addr, int size, u32 *val) 23int dw_pcie_read(void __iomem *addr, int size, u32 *val)
24{ 24{
25 if ((uintptr_t)addr & (size - 1)) { 25 if (!IS_ALIGNED((uintptr_t)addr, size)) {
26 *val = 0; 26 *val = 0;
27 return PCIBIOS_BAD_REGISTER_NUMBER; 27 return PCIBIOS_BAD_REGISTER_NUMBER;
28 } 28 }
@@ -43,7 +43,7 @@ int dw_pcie_read(void __iomem *addr, int size, u32 *val)
43 43
44int dw_pcie_write(void __iomem *addr, int size, u32 val) 44int dw_pcie_write(void __iomem *addr, int size, u32 val)
45{ 45{
46 if ((uintptr_t)addr & (size - 1)) 46 if (!IS_ALIGNED((uintptr_t)addr, size))
47 return PCIBIOS_BAD_REGISTER_NUMBER; 47 return PCIBIOS_BAD_REGISTER_NUMBER;
48 48
49 if (size == 4) 49 if (size == 4)
@@ -306,7 +306,7 @@ void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
306 } 306 }
307 307
308 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index); 308 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
309 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~PCIE_ATU_ENABLE); 309 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, (u32)~PCIE_ATU_ENABLE);
310} 310}
311 311
312int dw_pcie_wait_for_link(struct dw_pcie *pci) 312int dw_pcie_wait_for_link(struct dw_pcie *pci)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 1f56e6ae34ff..377f4c0b52da 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -11,6 +11,7 @@
11#ifndef _PCIE_DESIGNWARE_H 11#ifndef _PCIE_DESIGNWARE_H
12#define _PCIE_DESIGNWARE_H 12#define _PCIE_DESIGNWARE_H
13 13
14#include <linux/bitfield.h>
14#include <linux/dma-mapping.h> 15#include <linux/dma-mapping.h>
15#include <linux/irq.h> 16#include <linux/irq.h>
16#include <linux/msi.h> 17#include <linux/msi.h>
@@ -30,23 +31,25 @@
30 31
31/* Synopsys-specific PCIe configuration registers */ 32/* Synopsys-specific PCIe configuration registers */
32#define PCIE_PORT_LINK_CONTROL 0x710 33#define PCIE_PORT_LINK_CONTROL 0x710
33#define PORT_LINK_MODE_MASK (0x3f << 16) 34#define PORT_LINK_MODE_MASK GENMASK(21, 16)
34#define PORT_LINK_MODE_1_LANES (0x1 << 16) 35#define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n)
35#define PORT_LINK_MODE_2_LANES (0x3 << 16) 36#define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1)
36#define PORT_LINK_MODE_4_LANES (0x7 << 16) 37#define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3)
37#define PORT_LINK_MODE_8_LANES (0xf << 16) 38#define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7)
39#define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf)
38 40
39#define PCIE_PORT_DEBUG0 0x728 41#define PCIE_PORT_DEBUG0 0x728
40#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f 42#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
41#define PORT_LOGIC_LTSSM_STATE_L0 0x11 43#define PORT_LOGIC_LTSSM_STATE_L0 0x11
42 44
43#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C 45#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
44#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) 46#define PORT_LOGIC_SPEED_CHANGE BIT(17)
45#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) 47#define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8)
46#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) 48#define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n)
47#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) 49#define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1)
48#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) 50#define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2)
49#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8) 51#define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4)
52#define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8)
50 53
51#define PCIE_MSI_ADDR_LO 0x820 54#define PCIE_MSI_ADDR_LO 0x820
52#define PCIE_MSI_ADDR_HI 0x824 55#define PCIE_MSI_ADDR_HI 0x824
@@ -55,30 +58,30 @@
55#define PCIE_MSI_INTR0_STATUS 0x830 58#define PCIE_MSI_INTR0_STATUS 0x830
56 59
57#define PCIE_ATU_VIEWPORT 0x900 60#define PCIE_ATU_VIEWPORT 0x900
58#define PCIE_ATU_REGION_INBOUND (0x1 << 31) 61#define PCIE_ATU_REGION_INBOUND BIT(31)
59#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) 62#define PCIE_ATU_REGION_OUTBOUND 0
60#define PCIE_ATU_REGION_INDEX2 (0x2 << 0) 63#define PCIE_ATU_REGION_INDEX2 0x2
61#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) 64#define PCIE_ATU_REGION_INDEX1 0x1
62#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) 65#define PCIE_ATU_REGION_INDEX0 0x0
63#define PCIE_ATU_CR1 0x904 66#define PCIE_ATU_CR1 0x904
64#define PCIE_ATU_TYPE_MEM (0x0 << 0) 67#define PCIE_ATU_TYPE_MEM 0x0
65#define PCIE_ATU_TYPE_IO (0x2 << 0) 68#define PCIE_ATU_TYPE_IO 0x2
66#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) 69#define PCIE_ATU_TYPE_CFG0 0x4
67#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) 70#define PCIE_ATU_TYPE_CFG1 0x5
68#define PCIE_ATU_CR2 0x908 71#define PCIE_ATU_CR2 0x908
69#define PCIE_ATU_ENABLE (0x1 << 31) 72#define PCIE_ATU_ENABLE BIT(31)
70#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) 73#define PCIE_ATU_BAR_MODE_ENABLE BIT(30)
71#define PCIE_ATU_LOWER_BASE 0x90C 74#define PCIE_ATU_LOWER_BASE 0x90C
72#define PCIE_ATU_UPPER_BASE 0x910 75#define PCIE_ATU_UPPER_BASE 0x910
73#define PCIE_ATU_LIMIT 0x914 76#define PCIE_ATU_LIMIT 0x914
74#define PCIE_ATU_LOWER_TARGET 0x918 77#define PCIE_ATU_LOWER_TARGET 0x918
75#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) 78#define PCIE_ATU_BUS(x) FIELD_PREP(GENMASK(31, 24), x)
76#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) 79#define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x)
77#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 80#define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x)
78#define PCIE_ATU_UPPER_TARGET 0x91C 81#define PCIE_ATU_UPPER_TARGET 0x91C
79 82
80#define PCIE_MISC_CONTROL_1_OFF 0x8BC 83#define PCIE_MISC_CONTROL_1_OFF 0x8BC
81#define PCIE_DBI_RO_WR_EN (0x1 << 0) 84#define PCIE_DBI_RO_WR_EN BIT(0)
82 85
83/* 86/*
84 * iATU Unroll-specific register definitions 87 * iATU Unroll-specific register definitions
@@ -105,7 +108,7 @@
105 ((region) << 9) 108 ((region) << 9)
106 109
107#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \ 110#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
108 (((region) << 9) | (0x1 << 8)) 111 (((region) << 9) | BIT(8))
109 112
110#define MAX_MSI_IRQS 256 113#define MAX_MSI_IRQS 256
111#define MAX_MSI_IRQS_PER_CTRL 32 114#define MAX_MSI_IRQS_PER_CTRL 32
@@ -177,7 +180,7 @@ struct pcie_port {
177 struct irq_domain *msi_domain; 180 struct irq_domain *msi_domain;
178 dma_addr_t msi_data; 181 dma_addr_t msi_data;
179 u32 num_vectors; 182 u32 num_vectors;
180 u32 irq_status[MAX_MSI_CTRLS]; 183 u32 irq_mask[MAX_MSI_CTRLS];
181 raw_spinlock_t lock; 184 raw_spinlock_t lock;
182 DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); 185 DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
183}; 186};
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index d185ea5fe996..a7f703556790 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1228,7 +1228,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
1228 1228
1229 pcie->ops = of_device_get_match_data(dev); 1229 pcie->ops = of_device_get_match_data(dev);
1230 1230
1231 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_LOW); 1231 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
1232 if (IS_ERR(pcie->reset)) { 1232 if (IS_ERR(pcie->reset)) {
1233 ret = PTR_ERR(pcie->reset); 1233 ret = PTR_ERR(pcie->reset);
1234 goto err_pm_runtime_put; 1234 goto err_pm_runtime_put;
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-06 02:20:10 -0400