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-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x.h2
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c72
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c1
3 files changed, 30 insertions, 45 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
index 77bcd4cb4ffb..463b9ec57d80 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
@@ -1278,7 +1278,7 @@ struct bnx2x {
1278#define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1278#define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1279 1279
1280#define BNX2X_FW_RX_ALIGN_END \ 1280#define BNX2X_FW_RX_ALIGN_END \
1281 max(1UL << BNX2X_RX_ALIGN_SHIFT, \ 1281 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \
1282 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1282 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1283 1283
1284#define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1284#define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
index dd451c3dd83d..02b5a343b195 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
@@ -4041,20 +4041,6 @@ static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4041 return val != 0; 4041 return val != 0;
4042} 4042}
4043 4043
4044/*
4045 * Reset the load status for the current engine.
4046 */
4047static void bnx2x_clear_load_status(struct bnx2x *bp)
4048{
4049 u32 val;
4050 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4051 BNX2X_PATH0_LOAD_CNT_MASK);
4052 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4053 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4054 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
4055 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4056}
4057
4058static void _print_next_block(int idx, const char *blk) 4044static void _print_next_block(int idx, const char *blk)
4059{ 4045{
4060 pr_cont("%s%s", idx ? ", " : "", blk); 4046 pr_cont("%s%s", idx ? ", " : "", blk);
@@ -9384,32 +9370,24 @@ static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp)
9384 return rc; 9370 return rc;
9385} 9371}
9386 9372
9387static bool __devinit bnx2x_can_flr(struct bnx2x *bp)
9388{
9389 int pos;
9390 u32 cap;
9391 struct pci_dev *dev = bp->pdev;
9392
9393 pos = pci_pcie_cap(dev);
9394 if (!pos)
9395 return false;
9396
9397 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
9398 if (!(cap & PCI_EXP_DEVCAP_FLR))
9399 return false;
9400
9401 return true;
9402}
9403
9404static int __devinit bnx2x_do_flr(struct bnx2x *bp) 9373static int __devinit bnx2x_do_flr(struct bnx2x *bp)
9405{ 9374{
9406 int i, pos; 9375 int i, pos;
9407 u16 status; 9376 u16 status;
9408 struct pci_dev *dev = bp->pdev; 9377 struct pci_dev *dev = bp->pdev;
9409 9378
9410 /* probe the capability first */ 9379
9411 if (bnx2x_can_flr(bp)) 9380 if (CHIP_IS_E1x(bp)) {
9412 return -ENOTTY; 9381 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9382 return -EINVAL;
9383 }
9384
9385 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9386 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9387 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9388 bp->common.bc_ver);
9389 return -EINVAL;
9390 }
9413 9391
9414 pos = pci_pcie_cap(dev); 9392 pos = pci_pcie_cap(dev);
9415 if (!pos) 9393 if (!pos)
@@ -9429,12 +9407,8 @@ static int __devinit bnx2x_do_flr(struct bnx2x *bp)
9429 "transaction is not cleared; proceeding with reset anyway\n"); 9407 "transaction is not cleared; proceeding with reset anyway\n");
9430 9408
9431clear: 9409clear:
9432 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9433 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9434 bp->common.bc_ver);
9435 return -EINVAL;
9436 }
9437 9410
9411 BNX2X_DEV_INFO("Initiating FLR\n");
9438 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); 9412 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9439 9413
9440 return 0; 9414 return 0;
@@ -9454,8 +9428,21 @@ static int __devinit bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9454 * the one required, then FLR will be sufficient to clean any residue 9428 * the one required, then FLR will be sufficient to clean any residue
9455 * left by previous driver 9429 * left by previous driver
9456 */ 9430 */
9457 if (bnx2x_test_firmware_version(bp, false) && bnx2x_can_flr(bp)) 9431 rc = bnx2x_test_firmware_version(bp, false);
9458 return bnx2x_do_flr(bp); 9432
9433 if (!rc) {
9434 /* fw version is good */
9435 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9436 rc = bnx2x_do_flr(bp);
9437 }
9438
9439 if (!rc) {
9440 /* FLR was performed */
9441 BNX2X_DEV_INFO("FLR successful\n");
9442 return 0;
9443 }
9444
9445 BNX2X_DEV_INFO("Could not FLR\n");
9459 9446
9460 /* Close the MCP request, return failure*/ 9447 /* Close the MCP request, return failure*/
9461 rc = bnx2x_prev_mcp_done(bp); 9448 rc = bnx2x_prev_mcp_done(bp);
@@ -11427,9 +11414,6 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
11427 if (!chip_is_e1x) 11414 if (!chip_is_e1x)
11428 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 11415 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11429 11416
11430 /* Reset the load counter */
11431 bnx2x_clear_load_status(bp);
11432
11433 dev->watchdog_timeo = TX_TIMEOUT; 11417 dev->watchdog_timeo = TX_TIMEOUT;
11434 11418
11435 dev->netdev_ops = &bnx2x_netdev_ops; 11419 dev->netdev_ops = &bnx2x_netdev_ops;
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
index 734fd87cd990..62f754bd0dfe 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
@@ -2485,6 +2485,7 @@ static int bnx2x_mcast_enqueue_cmd(struct bnx2x *bp,
2485 break; 2485 break;
2486 2486
2487 default: 2487 default:
2488 kfree(new_cmd);
2488 BNX2X_ERR("Unknown command: %d\n", cmd); 2489 BNX2X_ERR("Unknown command: %d\n", cmd);
2489 return -EINVAL; 2490 return -EINVAL;
2490 } 2491 }