7 files changed, 276 insertions, 265 deletions

diff --git a/drivers/net/dsa/mv88e6xxx/Makefile b/drivers/net/dsa/mv88e6xxx/Makefile
index 50de304abe2f..e85755dde90b 100644
--- a/drivers/net/dsa/mv88e6xxx/Makefile
+++ b/drivers/net/dsa/mv88e6xxx/Makefile
@@ -12,3 +12,4 @@ mv88e6xxx-objs += phy.o
 mv88e6xxx-objs += port.o
 mv88e6xxx-$(CONFIG_NET_DSA_MV88E6XXX_PTP) += ptp.o
 mv88e6xxx-objs += serdes.o
+mv88e6xxx-objs += smi.o
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index f4e2db44ad91..28414db979b0 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -43,6 +43,7 @@
 #include "port.h"
 #include "ptp.h"
 #include "serdes.h"
+#include "smi.h"
 
 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
 {
@@ -52,149 +53,6 @@ static void assert_reg_lock(struct mv88e6xxx_chip *chip)
         }
 }
 
-/* The switch ADDR[4:1] configuration pins define the chip SMI device address
- * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
- *
- * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
- * is the only device connected to the SMI master. In this mode it responds to
- * all 32 possible SMI addresses, and thus maps directly the internal devices.
- *
- * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
- * multiple devices to share the SMI interface. In this mode it responds to only
- * 2 registers, used to indirectly access the internal SMI devices.
- */
-
-static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
-                              int addr, int reg, u16 *val)
-{
-        if (!chip->smi_ops)
-                return -EOPNOTSUPP;
-
-        return chip->smi_ops->read(chip, addr, reg, val);
-}
-
-static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
-                               int addr, int reg, u16 val)
-{
-        if (!chip->smi_ops)
-                return -EOPNOTSUPP;
-
-        return chip->smi_ops->write(chip, addr, reg, val);
-}
-
-static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
-                                          int addr, int reg, u16 *val)
-{
-        int ret;
-
-        ret = mdiobus_read_nested(chip->bus, addr, reg);
-        if (ret < 0)
-                return ret;
-
-        *val = ret & 0xffff;
-
-        return 0;
-}
-
-static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
-                                           int addr, int reg, u16 val)
-{
-        int ret;
-
-        ret = mdiobus_write_nested(chip->bus, addr, reg, val);
-        if (ret < 0)
-                return ret;
-
-        return 0;
-}
-
-static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
-        .read = mv88e6xxx_smi_single_chip_read,
-        .write = mv88e6xxx_smi_single_chip_write,
-};
-
-static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
-{
-        int ret;
-        int i;
-
-        for (i = 0; i < 16; i++) {
-                ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
-                if (ret < 0)
-                        return ret;
-
-                if ((ret & SMI_CMD_BUSY) == 0)
-                        return 0;
-        }
-
-        return -ETIMEDOUT;
-}
-
-static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
-                                         int addr, int reg, u16 *val)
-{
-        int ret;
-
-        /* Wait for the bus to become free. */
-        ret = mv88e6xxx_smi_multi_chip_wait(chip);
-        if (ret < 0)
-                return ret;
-
-        /* Transmit the read command. */
-        ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
-                                   SMI_CMD_OP_22_READ | (addr << 5) | reg);
-        if (ret < 0)
-                return ret;
-
-        /* Wait for the read command to complete. */
-        ret = mv88e6xxx_smi_multi_chip_wait(chip);
-        if (ret < 0)
-                return ret;
-
-        /* Read the data. */
-        ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
-        if (ret < 0)
-                return ret;
-
-        *val = ret & 0xffff;
-
-        return 0;
-}
-
-static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
-                                          int addr, int reg, u16 val)
-{
-        int ret;
-
-        /* Wait for the bus to become free. */
-        ret = mv88e6xxx_smi_multi_chip_wait(chip);
-        if (ret < 0)
-                return ret;
-
-        /* Transmit the data to write. */
-        ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
-        if (ret < 0)
-                return ret;
-
-        /* Transmit the write command. */
-        ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
-                                   SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
-        if (ret < 0)
-                return ret;
-
-        /* Wait for the write command to complete. */
-        ret = mv88e6xxx_smi_multi_chip_wait(chip);
-        if (ret < 0)
-                return ret;
-
-        return 0;
-}
-
-static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
-        .read = mv88e6xxx_smi_multi_chip_read,
-        .write = mv88e6xxx_smi_multi_chip_write,
-};
-
 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
 {
         int err;
@@ -553,11 +411,28 @@ int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link,
                              int speed, int duplex, int pause,
                              phy_interface_t mode)
 {
+        struct phylink_link_state state;
         int err;
 
         if (!chip->info->ops->port_set_link)
                 return 0;
 
+        if (!chip->info->ops->port_link_state)
+                return 0;
+
+        err = chip->info->ops->port_link_state(chip, port, &state);
+        if (err)
+                return err;
+
+        /* Has anything actually changed? We don't expect the
+         * interface mode to change without one of the other
+         * parameters also changing
+         */
+        if (state.link == link &&
+            state.speed == speed &&
+            state.duplex == duplex)
+                return 0;
+
         /* Port's MAC control must not be changed unless the link is down */
         err = chip->info->ops->port_set_link(chip, port, 0);
         if (err)
@@ -2411,6 +2286,9 @@ static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
 
         mutex_lock(&chip->reg_lock);
 
+        if (mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED))
+                dev_err(chip->dev, "failed to disable port\n");
+
         if (chip->info->ops->serdes_irq_free)
                 chip->info->ops->serdes_irq_free(chip, port);
 
@@ -2579,8 +2457,18 @@ static int mv88e6xxx_setup(struct dsa_switch *ds)
 
         /* Setup Switch Port Registers */
         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
-                if (dsa_is_unused_port(ds, i))
+                if (dsa_is_unused_port(ds, i)) {
+                        err = mv88e6xxx_port_set_state(chip, i,
+                                                       BR_STATE_DISABLED);
+                        if (err)
+                                goto unlock;
+
+                        err = mv88e6xxx_serdes_power(chip, i, false);
+                        if (err)
+                                goto unlock;
+
                         continue;
+                }
 
                 err = mv88e6xxx_setup_port(chip, i);
                 if (err)
@@ -4615,30 +4503,6 @@ static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
         return chip;
 }
 
-static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
-                              struct mii_bus *bus, int sw_addr)
-{
-        if (sw_addr == 0)
-                chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
-        else if (chip->info->multi_chip)
-                chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
-        else
-                return -EINVAL;
-
-        chip->bus = bus;
-        chip->sw_addr = sw_addr;
-
-        return 0;
-}
-
-static void mv88e6xxx_ports_cmode_init(struct mv88e6xxx_chip *chip)
-{
-        int i;
-
-        for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
-                chip->ports[i].cmode = MV88E6XXX_PORT_STS_CMODE_INVALID;
-}
-
 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
                                                         int port)
 {
@@ -4647,58 +4511,6 @@ static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
         return chip->info->tag_protocol;
 }
 
-#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
-static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
-                                       struct device *host_dev, int sw_addr,
-                                       void **priv)
-{
-        struct mv88e6xxx_chip *chip;
-        struct mii_bus *bus;
-        int err;
-
-        bus = dsa_host_dev_to_mii_bus(host_dev);
-        if (!bus)
-                return NULL;
-
-        chip = mv88e6xxx_alloc_chip(dsa_dev);
-        if (!chip)
-                return NULL;
-
-        /* Legacy SMI probing will only support chips similar to 88E6085 */
-        chip->info = &mv88e6xxx_table[MV88E6085];
-
-        err = mv88e6xxx_smi_init(chip, bus, sw_addr);
-        if (err)
-                goto free;
-
-        err = mv88e6xxx_detect(chip);
-        if (err)
-                goto free;
-
-        mv88e6xxx_ports_cmode_init(chip);
-
-        mutex_lock(&chip->reg_lock);
-        err = mv88e6xxx_switch_reset(chip);
-        mutex_unlock(&chip->reg_lock);
-        if (err)
-                goto free;
-
-        mv88e6xxx_phy_init(chip);
-
-        err = mv88e6xxx_mdios_register(chip, NULL);
-        if (err)
-                goto free;
-
-        *priv = chip;
-
-        return chip->info->name;
-free:
-        devm_kfree(dsa_dev, chip);
-
-        return NULL;
-}
-#endif
-
 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
                                       const struct switchdev_obj_port_mdb *mdb)
 {
@@ -4753,9 +4565,6 @@ static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port,
 }
 
 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
-#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
-        .probe                  = mv88e6xxx_drv_probe,
-#endif
         .get_tag_protocol       = mv88e6xxx_get_tag_protocol,
         .setup                  = mv88e6xxx_setup,
         .adjust_link            = mv88e6xxx_adjust_link,
@@ -4801,10 +4610,6 @@ static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
         .get_ts_info            = mv88e6xxx_get_ts_info,
 };
 
-static struct dsa_switch_driver mv88e6xxx_switch_drv = {
-        .ops                    = &mv88e6xxx_switch_ops,
-};
-
 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
 {
         struct device *dev = chip->dev;
@@ -4915,7 +4720,6 @@ static int mv88e6xxx_probe(struct mdio_device *mdiodev)
         if (err)
                 goto out;
 
-        mv88e6xxx_ports_cmode_init(chip);
         mv88e6xxx_phy_init(chip);
 
         if (chip->info->ops->get_eeprom) {
@@ -4932,12 +4736,17 @@ static int mv88e6xxx_probe(struct mdio_device *mdiodev)
         if (err)
                 goto out;
 
-        chip->irq = of_irq_get(np, 0);
-        if (chip->irq == -EPROBE_DEFER) {
-                err = chip->irq;
-                goto out;
+        if (np) {
+                chip->irq = of_irq_get(np, 0);
+                if (chip->irq == -EPROBE_DEFER) {
+                        err = chip->irq;
+                        goto out;
+                }
         }
 
+        if (pdata)
+                chip->irq = pdata->irq;
+
         /* Has to be performed before the MDIO bus is created, because
          * the PHYs will link their interrupts to these interrupt
          * controllers
@@ -5047,19 +4856,7 @@ static struct mdio_driver mv88e6xxx_driver = {
         },
 };
 
-static int __init mv88e6xxx_init(void)
-{
-        register_switch_driver(&mv88e6xxx_switch_drv);
-        return mdio_driver_register(&mv88e6xxx_driver);
-}
-module_init(mv88e6xxx_init);
-
-static void __exit mv88e6xxx_cleanup(void)
-{
-        mdio_driver_unregister(&mv88e6xxx_driver);
-        unregister_switch_driver(&mv88e6xxx_switch_drv);
-}
-module_exit(mv88e6xxx_cleanup);
+mdio_module_driver(mv88e6xxx_driver);
 
 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h
index 19c07dff0440..faa3fa889f19 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.h
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
@@ -21,17 +21,6 @@
 #include <linux/timecounter.h>
 #include <net/dsa.h>
 
-#define SMI_CMD                 0x00
-#define SMI_CMD_BUSY            BIT(15)
-#define SMI_CMD_CLAUSE_22       BIT(12)
-#define SMI_CMD_OP_22_WRITE     ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
-#define SMI_CMD_OP_22_READ      ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
-#define SMI_CMD_OP_45_WRITE_ADDR        ((0 << 10) | SMI_CMD_BUSY)
-#define SMI_CMD_OP_45_WRITE_DATA        ((1 << 10) | SMI_CMD_BUSY)
-#define SMI_CMD_OP_45_READ_DATA         ((2 << 10) | SMI_CMD_BUSY)
-#define SMI_CMD_OP_45_READ_DATA_INC     ((3 << 10) | SMI_CMD_BUSY)
-#define SMI_DATA                0x01
-
 #define MV88E6XXX_N_FID         4096
 
 /* PVT limits for 4-bit port and 5-bit switch */
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index dce84a2a65c7..c44b2822e4dd 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -427,18 +427,22 @@ int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
                 return 0;
 
         lane = mv88e6390x_serdes_get_lane(chip, port);
-        if (lane < 0)
+        if (lane < 0 && lane != -ENODEV)
                 return lane;
 
-        if (chip->ports[port].serdes_irq) {
-                err = mv88e6390_serdes_irq_disable(chip, port, lane);
+        if (lane >= 0) {
+                if (chip->ports[port].serdes_irq) {
+                        err = mv88e6390_serdes_irq_disable(chip, port, lane);
+                        if (err)
+                                return err;
+                }
+
+                err = mv88e6390x_serdes_power(chip, port, false);
                 if (err)
                         return err;
         }
 
-        err = mv88e6390x_serdes_power(chip, port, false);
-        if (err)
-                return err;
+        chip->ports[port].cmode = 0;
 
         if (cmode) {
                 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
@@ -452,6 +456,12 @@ int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
                 if (err)
                         return err;
 
+                chip->ports[port].cmode = cmode;
+
+                lane = mv88e6390x_serdes_get_lane(chip, port);
+                if (lane < 0)
+                        return lane;
+
                 err = mv88e6390x_serdes_power(chip, port, true);
                 if (err)
                         return err;
@@ -463,8 +473,6 @@ int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
                 }
         }
 
-        chip->ports[port].cmode = cmode;
-
         return 0;
 }
 
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index c7bed263a0f4..39c85e98fb92 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -52,7 +52,6 @@
 #define MV88E6185_PORT_STS_CMODE_1000BASE_X     0x0005
 #define MV88E6185_PORT_STS_CMODE_PHY            0x0006
 #define MV88E6185_PORT_STS_CMODE_DISABLED       0x0007
-#define MV88E6XXX_PORT_STS_CMODE_INVALID        0xff
 
 /* Offset 0x01: MAC (or PCS or Physical) Control Register */
 #define MV88E6XXX_PORT_MAC_CTL                          0x01
diff --git a/drivers/net/dsa/mv88e6xxx/smi.c b/drivers/net/dsa/mv88e6xxx/smi.c
new file mode 100644
index 000000000000..96f7d2685bdc
--- /dev/null
+++ b/drivers/net/dsa/mv88e6xxx/smi.c
@@ -0,0 +1,158 @@
+/*
+ * Marvell 88E6xxx System Management Interface (SMI) support
+ *
+ * Copyright (c) 2008 Marvell Semiconductor
+ *
+ * Copyright (c) 2019 Vivien Didelot <vivien.didelot@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "chip.h"
+#include "smi.h"
+
+/* The switch ADDR[4:1] configuration pins define the chip SMI device address
+ * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
+ *
+ * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
+ * is the only device connected to the SMI master. In this mode it responds to
+ * all 32 possible SMI addresses, and thus maps directly the internal devices.
+ *
+ * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
+ * multiple devices to share the SMI interface. In this mode it responds to only
+ * 2 registers, used to indirectly access the internal SMI devices.
+ */
+
+static int mv88e6xxx_smi_direct_read(struct mv88e6xxx_chip *chip,
+                                     int dev, int reg, u16 *data)
+{
+        int ret;
+
+        ret = mdiobus_read_nested(chip->bus, dev, reg);
+        if (ret < 0)
+                return ret;
+
+        *data = ret & 0xffff;
+
+        return 0;
+}
+
+static int mv88e6xxx_smi_direct_write(struct mv88e6xxx_chip *chip,
+                                      int dev, int reg, u16 data)
+{
+        int ret;
+
+        ret = mdiobus_write_nested(chip->bus, dev, reg, data);
+        if (ret < 0)
+                return ret;
+
+        return 0;
+}
+
+static int mv88e6xxx_smi_direct_wait(struct mv88e6xxx_chip *chip,
+                                     int dev, int reg, int bit, int val)
+{
+        u16 data;
+        int err;
+        int i;
+
+        for (i = 0; i < 16; i++) {
+                err = mv88e6xxx_smi_direct_read(chip, dev, reg, &data);
+                if (err)
+                        return err;
+
+                if (!!(data >> bit) == !!val)
+                        return 0;
+        }
+
+        return -ETIMEDOUT;
+}
+
+static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_direct_ops = {
+        .read = mv88e6xxx_smi_direct_read,
+        .write = mv88e6xxx_smi_direct_write,
+};
+
+/* Offset 0x00: SMI Command Register
+ * Offset 0x01: SMI Data Register
+ */
+
+static int mv88e6xxx_smi_indirect_read(struct mv88e6xxx_chip *chip,
+                                       int dev, int reg, u16 *data)
+{
+        int err;
+
+        err = mv88e6xxx_smi_direct_wait(chip, chip->sw_addr,
+                                        MV88E6XXX_SMI_CMD, 15, 0);
+        if (err)
+                return err;
+
+        err = mv88e6xxx_smi_direct_write(chip, chip->sw_addr,
+                                         MV88E6XXX_SMI_CMD,
+                                         MV88E6XXX_SMI_CMD_BUSY |
+                                         MV88E6XXX_SMI_CMD_MODE_22 |
+                                         MV88E6XXX_SMI_CMD_OP_22_READ |
+                                         (dev << 5) | reg);
+        if (err)
+                return err;
+
+        err = mv88e6xxx_smi_direct_wait(chip, chip->sw_addr,
+                                        MV88E6XXX_SMI_CMD, 15, 0);
+        if (err)
+                return err;
+
+        return mv88e6xxx_smi_direct_read(chip, chip->sw_addr,
+                                         MV88E6XXX_SMI_DATA, data);
+}
+
+static int mv88e6xxx_smi_indirect_write(struct mv88e6xxx_chip *chip,
+                                        int dev, int reg, u16 data)
+{
+        int err;
+
+        err = mv88e6xxx_smi_direct_wait(chip, chip->sw_addr,
+                                        MV88E6XXX_SMI_CMD, 15, 0);
+        if (err)
+                return err;
+
+        err = mv88e6xxx_smi_direct_write(chip, chip->sw_addr,
+                                         MV88E6XXX_SMI_DATA, data);
+        if (err)
+                return err;
+
+        err = mv88e6xxx_smi_direct_write(chip, chip->sw_addr,
+                                         MV88E6XXX_SMI_CMD,
+                                         MV88E6XXX_SMI_CMD_BUSY |
+                                         MV88E6XXX_SMI_CMD_MODE_22 |
+                                         MV88E6XXX_SMI_CMD_OP_22_WRITE |
+                                         (dev << 5) | reg);
+        if (err)
+                return err;
+
+        return mv88e6xxx_smi_direct_wait(chip, chip->sw_addr,
+                                         MV88E6XXX_SMI_CMD, 15, 0);
+}
+
+static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_indirect_ops = {
+        .read = mv88e6xxx_smi_indirect_read,
+        .write = mv88e6xxx_smi_indirect_write,
+};
+
+int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
+                       struct mii_bus *bus, int sw_addr)
+{
+        if (sw_addr == 0)
+                chip->smi_ops = &mv88e6xxx_smi_direct_ops;
+        else if (chip->info->multi_chip)
+                chip->smi_ops = &mv88e6xxx_smi_indirect_ops;
+        else
+                return -EINVAL;
+
+        chip->bus = bus;
+        chip->sw_addr = sw_addr;
+
+        return 0;
+}
diff --git a/drivers/net/dsa/mv88e6xxx/smi.h b/drivers/net/dsa/mv88e6xxx/smi.h
new file mode 100644
index 000000000000..35e6403b65dc
--- /dev/null
+++ b/drivers/net/dsa/mv88e6xxx/smi.h
@@ -0,0 +1,59 @@
+/*
+ * Marvell 88E6xxx System Management Interface (SMI) support
+ *
+ * Copyright (c) 2008 Marvell Semiconductor
+ *
+ * Copyright (c) 2019 Vivien Didelot <vivien.didelot@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _MV88E6XXX_SMI_H
+#define _MV88E6XXX_SMI_H
+
+#include "chip.h"
+
+/* Offset 0x00: SMI Command Register */
+#define MV88E6XXX_SMI_CMD                       0x00
+#define MV88E6XXX_SMI_CMD_BUSY                  0x8000
+#define MV88E6XXX_SMI_CMD_MODE_MASK             0x1000
+#define MV88E6XXX_SMI_CMD_MODE_45               0x0000
+#define MV88E6XXX_SMI_CMD_MODE_22               0x1000
+#define MV88E6XXX_SMI_CMD_OP_MASK               0x0c00
+#define MV88E6XXX_SMI_CMD_OP_22_WRITE           0x0400
+#define MV88E6XXX_SMI_CMD_OP_22_READ            0x0800
+#define MV88E6XXX_SMI_CMD_OP_45_WRITE_ADDR      0x0000
+#define MV88E6XXX_SMI_CMD_OP_45_WRITE_DATA      0x0400
+#define MV88E6XXX_SMI_CMD_OP_45_READ_DATA       0x0800
+#define MV88E6XXX_SMI_CMD_OP_45_READ_DATA_INC   0x0c00
+#define MV88E6XXX_SMI_CMD_DEV_ADDR_MASK         0x003e
+#define MV88E6XXX_SMI_CMD_REG_ADDR_MASK         0x001f
+
+/* Offset 0x01: SMI Data Register */
+#define MV88E6XXX_SMI_DATA                      0x01
+
+int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
+                       struct mii_bus *bus, int sw_addr);
+
+static inline int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
+                                     int dev, int reg, u16 *data)
+{
+        if (chip->smi_ops && chip->smi_ops->read)
+                return chip->smi_ops->read(chip, dev, reg, data);
+
+        return -EOPNOTSUPP;
+}
+
+static inline int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
+                                      int dev, int reg, u16 data)
+{
+        if (chip->smi_ops && chip->smi_ops->write)
+                return chip->smi_ops->write(chip, dev, reg, data);
+
+        return -EOPNOTSUPP;
+}
+
+#endif /* _MV88E6XXX_SMI_H */