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Diffstat (limited to 'drivers/net/dsa/mv88e6060.c')
-rw-r--r--drivers/net/dsa/mv88e6060.c217
1 files changed, 118 insertions, 99 deletions
diff --git a/drivers/net/dsa/mv88e6060.c b/drivers/net/dsa/mv88e6060.c
index 0b3e51f248c2..2a2489b5196d 100644
--- a/drivers/net/dsa/mv88e6060.c
+++ b/drivers/net/dsa/mv88e6060.c
@@ -1,11 +1,7 @@
1// SPDX-License-Identifier: GPL-2.0+
1/* 2/*
2 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips 3 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
3 * Copyright (c) 2008-2009 Marvell Semiconductor 4 * Copyright (c) 2008-2009 Marvell Semiconductor
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */ 5 */
10 6
11#include <linux/delay.h> 7#include <linux/delay.h>
@@ -18,40 +14,16 @@
18#include <net/dsa.h> 14#include <net/dsa.h>
19#include "mv88e6060.h" 15#include "mv88e6060.h"
20 16
21static int reg_read(struct dsa_switch *ds, int addr, int reg) 17static int reg_read(struct mv88e6060_priv *priv, int addr, int reg)
22{ 18{
23 struct mv88e6060_priv *priv = ds->priv;
24
25 return mdiobus_read_nested(priv->bus, priv->sw_addr + addr, reg); 19 return mdiobus_read_nested(priv->bus, priv->sw_addr + addr, reg);
26} 20}
27 21
28#define REG_READ(addr, reg) \ 22static int reg_write(struct mv88e6060_priv *priv, int addr, int reg, u16 val)
29 ({ \
30 int __ret; \
31 \
32 __ret = reg_read(ds, addr, reg); \
33 if (__ret < 0) \
34 return __ret; \
35 __ret; \
36 })
37
38
39static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
40{ 23{
41 struct mv88e6060_priv *priv = ds->priv;
42
43 return mdiobus_write_nested(priv->bus, priv->sw_addr + addr, reg, val); 24 return mdiobus_write_nested(priv->bus, priv->sw_addr + addr, reg, val);
44} 25}
45 26
46#define REG_WRITE(addr, reg, val) \
47 ({ \
48 int __ret; \
49 \
50 __ret = reg_write(ds, addr, reg, val); \
51 if (__ret < 0) \
52 return __ret; \
53 })
54
55static const char *mv88e6060_get_name(struct mii_bus *bus, int sw_addr) 27static const char *mv88e6060_get_name(struct mii_bus *bus, int sw_addr)
56{ 28{
57 int ret; 29 int ret;
@@ -76,28 +48,7 @@ static enum dsa_tag_protocol mv88e6060_get_tag_protocol(struct dsa_switch *ds,
76 return DSA_TAG_PROTO_TRAILER; 48 return DSA_TAG_PROTO_TRAILER;
77} 49}
78 50
79static const char *mv88e6060_drv_probe(struct device *dsa_dev, 51static int mv88e6060_switch_reset(struct mv88e6060_priv *priv)
80 struct device *host_dev, int sw_addr,
81 void **_priv)
82{
83 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
84 struct mv88e6060_priv *priv;
85 const char *name;
86
87 name = mv88e6060_get_name(bus, sw_addr);
88 if (name) {
89 priv = devm_kzalloc(dsa_dev, sizeof(*priv), GFP_KERNEL);
90 if (!priv)
91 return NULL;
92 *_priv = priv;
93 priv->bus = bus;
94 priv->sw_addr = sw_addr;
95 }
96
97 return name;
98}
99
100static int mv88e6060_switch_reset(struct dsa_switch *ds)
101{ 52{
102 int i; 53 int i;
103 int ret; 54 int ret;
@@ -105,23 +56,32 @@ static int mv88e6060_switch_reset(struct dsa_switch *ds)
105 56
106 /* Set all ports to the disabled state. */ 57 /* Set all ports to the disabled state. */
107 for (i = 0; i < MV88E6060_PORTS; i++) { 58 for (i = 0; i < MV88E6060_PORTS; i++) {
108 ret = REG_READ(REG_PORT(i), PORT_CONTROL); 59 ret = reg_read(priv, REG_PORT(i), PORT_CONTROL);
109 REG_WRITE(REG_PORT(i), PORT_CONTROL, 60 if (ret < 0)
110 ret & ~PORT_CONTROL_STATE_MASK); 61 return ret;
62 ret = reg_write(priv, REG_PORT(i), PORT_CONTROL,
63 ret & ~PORT_CONTROL_STATE_MASK);
64 if (ret)
65 return ret;
111 } 66 }
112 67
113 /* Wait for transmit queues to drain. */ 68 /* Wait for transmit queues to drain. */
114 usleep_range(2000, 4000); 69 usleep_range(2000, 4000);
115 70
116 /* Reset the switch. */ 71 /* Reset the switch. */
117 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL, 72 ret = reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL,
118 GLOBAL_ATU_CONTROL_SWRESET | 73 GLOBAL_ATU_CONTROL_SWRESET |
119 GLOBAL_ATU_CONTROL_LEARNDIS); 74 GLOBAL_ATU_CONTROL_LEARNDIS);
75 if (ret)
76 return ret;
120 77
121 /* Wait up to one second for reset to complete. */ 78 /* Wait up to one second for reset to complete. */
122 timeout = jiffies + 1 * HZ; 79 timeout = jiffies + 1 * HZ;
123 while (time_before(jiffies, timeout)) { 80 while (time_before(jiffies, timeout)) {
124 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); 81 ret = reg_read(priv, REG_GLOBAL, GLOBAL_STATUS);
82 if (ret < 0)
83 return ret;
84
125 if (ret & GLOBAL_STATUS_INIT_READY) 85 if (ret & GLOBAL_STATUS_INIT_READY)
126 break; 86 break;
127 87
@@ -133,61 +93,69 @@ static int mv88e6060_switch_reset(struct dsa_switch *ds)
133 return 0; 93 return 0;
134} 94}
135 95
136static int mv88e6060_setup_global(struct dsa_switch *ds) 96static int mv88e6060_setup_global(struct mv88e6060_priv *priv)
137{ 97{
98 int ret;
99
138 /* Disable discarding of frames with excessive collisions, 100 /* Disable discarding of frames with excessive collisions,
139 * set the maximum frame size to 1536 bytes, and mask all 101 * set the maximum frame size to 1536 bytes, and mask all
140 * interrupt sources. 102 * interrupt sources.
141 */ 103 */
142 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536); 104 ret = reg_write(priv, REG_GLOBAL, GLOBAL_CONTROL,
105 GLOBAL_CONTROL_MAX_FRAME_1536);
106 if (ret)
107 return ret;
143 108
144 /* Disable automatic address learning. 109 /* Disable automatic address learning.
145 */ 110 */
146 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL, 111 return reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL,
147 GLOBAL_ATU_CONTROL_LEARNDIS); 112 GLOBAL_ATU_CONTROL_LEARNDIS);
148
149 return 0;
150} 113}
151 114
152static int mv88e6060_setup_port(struct dsa_switch *ds, int p) 115static int mv88e6060_setup_port(struct mv88e6060_priv *priv, int p)
153{ 116{
154 int addr = REG_PORT(p); 117 int addr = REG_PORT(p);
118 int ret;
155 119
156 /* Do not force flow control, disable Ingress and Egress 120 /* Do not force flow control, disable Ingress and Egress
157 * Header tagging, disable VLAN tunneling, and set the port 121 * Header tagging, disable VLAN tunneling, and set the port
158 * state to Forwarding. Additionally, if this is the CPU 122 * state to Forwarding. Additionally, if this is the CPU
159 * port, enable Ingress and Egress Trailer tagging mode. 123 * port, enable Ingress and Egress Trailer tagging mode.
160 */ 124 */
161 REG_WRITE(addr, PORT_CONTROL, 125 ret = reg_write(priv, addr, PORT_CONTROL,
162 dsa_is_cpu_port(ds, p) ? 126 dsa_is_cpu_port(priv->ds, p) ?
163 PORT_CONTROL_TRAILER | 127 PORT_CONTROL_TRAILER |
164 PORT_CONTROL_INGRESS_MODE | 128 PORT_CONTROL_INGRESS_MODE |
165 PORT_CONTROL_STATE_FORWARDING : 129 PORT_CONTROL_STATE_FORWARDING :
166 PORT_CONTROL_STATE_FORWARDING); 130 PORT_CONTROL_STATE_FORWARDING);
131 if (ret)
132 return ret;
167 133
168 /* Port based VLAN map: give each port its own address 134 /* Port based VLAN map: give each port its own address
169 * database, allow the CPU port to talk to each of the 'real' 135 * database, allow the CPU port to talk to each of the 'real'
170 * ports, and allow each of the 'real' ports to only talk to 136 * ports, and allow each of the 'real' ports to only talk to
171 * the CPU port. 137 * the CPU port.
172 */ 138 */
173 REG_WRITE(addr, PORT_VLAN_MAP, 139 ret = reg_write(priv, addr, PORT_VLAN_MAP,
174 ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) | 140 ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
175 (dsa_is_cpu_port(ds, p) ? dsa_user_ports(ds) : 141 (dsa_is_cpu_port(priv->ds, p) ?
176 BIT(dsa_to_port(ds, p)->cpu_dp->index))); 142 dsa_user_ports(priv->ds) :
143 BIT(dsa_to_port(priv->ds, p)->cpu_dp->index)));
144 if (ret)
145 return ret;
177 146
178 /* Port Association Vector: when learning source addresses 147 /* Port Association Vector: when learning source addresses
179 * of packets, add the address to the address database using 148 * of packets, add the address to the address database using
180 * a port bitmap that has only the bit for this port set and 149 * a port bitmap that has only the bit for this port set and
181 * the other bits clear. 150 * the other bits clear.
182 */ 151 */
183 REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p)); 152 return reg_write(priv, addr, PORT_ASSOC_VECTOR, BIT(p));
184
185 return 0;
186} 153}
187 154
188static int mv88e6060_setup_addr(struct dsa_switch *ds) 155static int mv88e6060_setup_addr(struct mv88e6060_priv *priv)
189{ 156{
190 u8 addr[ETH_ALEN]; 157 u8 addr[ETH_ALEN];
158 int ret;
191 u16 val; 159 u16 val;
192 160
193 eth_random_addr(addr); 161 eth_random_addr(addr);
@@ -199,34 +167,43 @@ static int mv88e6060_setup_addr(struct dsa_switch *ds)
199 */ 167 */
200 val &= 0xfeff; 168 val &= 0xfeff;
201 169
202 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, val); 170 ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_01, val);
203 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); 171 if (ret)
204 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); 172 return ret;
173
174 ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_23,
175 (addr[2] << 8) | addr[3]);
176 if (ret)
177 return ret;
205 178
206 return 0; 179 return reg_write(priv, REG_GLOBAL, GLOBAL_MAC_45,
180 (addr[4] << 8) | addr[5]);
207} 181}
208 182
209static int mv88e6060_setup(struct dsa_switch *ds) 183static int mv88e6060_setup(struct dsa_switch *ds)
210{ 184{
185 struct mv88e6060_priv *priv = ds->priv;
211 int ret; 186 int ret;
212 int i; 187 int i;
213 188
214 ret = mv88e6060_switch_reset(ds); 189 priv->ds = ds;
190
191 ret = mv88e6060_switch_reset(priv);
215 if (ret < 0) 192 if (ret < 0)
216 return ret; 193 return ret;
217 194
218 /* @@@ initialise atu */ 195 /* @@@ initialise atu */
219 196
220 ret = mv88e6060_setup_global(ds); 197 ret = mv88e6060_setup_global(priv);
221 if (ret < 0) 198 if (ret < 0)
222 return ret; 199 return ret;
223 200
224 ret = mv88e6060_setup_addr(ds); 201 ret = mv88e6060_setup_addr(priv);
225 if (ret < 0) 202 if (ret < 0)
226 return ret; 203 return ret;
227 204
228 for (i = 0; i < MV88E6060_PORTS; i++) { 205 for (i = 0; i < MV88E6060_PORTS; i++) {
229 ret = mv88e6060_setup_port(ds, i); 206 ret = mv88e6060_setup_port(priv, i);
230 if (ret < 0) 207 if (ret < 0)
231 return ret; 208 return ret;
232 } 209 }
@@ -243,51 +220,93 @@ static int mv88e6060_port_to_phy_addr(int port)
243 220
244static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum) 221static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
245{ 222{
223 struct mv88e6060_priv *priv = ds->priv;
246 int addr; 224 int addr;
247 225
248 addr = mv88e6060_port_to_phy_addr(port); 226 addr = mv88e6060_port_to_phy_addr(port);
249 if (addr == -1) 227 if (addr == -1)
250 return 0xffff; 228 return 0xffff;
251 229
252 return reg_read(ds, addr, regnum); 230 return reg_read(priv, addr, regnum);
253} 231}
254 232
255static int 233static int
256mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) 234mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
257{ 235{
236 struct mv88e6060_priv *priv = ds->priv;
258 int addr; 237 int addr;
259 238
260 addr = mv88e6060_port_to_phy_addr(port); 239 addr = mv88e6060_port_to_phy_addr(port);
261 if (addr == -1) 240 if (addr == -1)
262 return 0xffff; 241 return 0xffff;
263 242
264 return reg_write(ds, addr, regnum, val); 243 return reg_write(priv, addr, regnum, val);
265} 244}
266 245
267static const struct dsa_switch_ops mv88e6060_switch_ops = { 246static const struct dsa_switch_ops mv88e6060_switch_ops = {
268 .get_tag_protocol = mv88e6060_get_tag_protocol, 247 .get_tag_protocol = mv88e6060_get_tag_protocol,
269 .probe = mv88e6060_drv_probe,
270 .setup = mv88e6060_setup, 248 .setup = mv88e6060_setup,
271 .phy_read = mv88e6060_phy_read, 249 .phy_read = mv88e6060_phy_read,
272 .phy_write = mv88e6060_phy_write, 250 .phy_write = mv88e6060_phy_write,
273}; 251};
274 252
275static struct dsa_switch_driver mv88e6060_switch_drv = { 253static int mv88e6060_probe(struct mdio_device *mdiodev)
276 .ops = &mv88e6060_switch_ops,
277};
278
279static int __init mv88e6060_init(void)
280{ 254{
281 register_switch_driver(&mv88e6060_switch_drv); 255 struct device *dev = &mdiodev->dev;
282 return 0; 256 struct mv88e6060_priv *priv;
257 struct dsa_switch *ds;
258 const char *name;
259
260 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
261 if (!priv)
262 return -ENOMEM;
263
264 priv->bus = mdiodev->bus;
265 priv->sw_addr = mdiodev->addr;
266
267 name = mv88e6060_get_name(priv->bus, priv->sw_addr);
268 if (!name)
269 return -ENODEV;
270
271 dev_info(dev, "switch %s detected\n", name);
272
273 ds = dsa_switch_alloc(dev, MV88E6060_PORTS);
274 if (!ds)
275 return -ENOMEM;
276
277 ds->priv = priv;
278 ds->dev = dev;
279 ds->ops = &mv88e6060_switch_ops;
280
281 dev_set_drvdata(dev, ds);
282
283 return dsa_register_switch(ds);
283} 284}
284module_init(mv88e6060_init);
285 285
286static void __exit mv88e6060_cleanup(void) 286static void mv88e6060_remove(struct mdio_device *mdiodev)
287{ 287{
288 unregister_switch_driver(&mv88e6060_switch_drv); 288 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
289
290 dsa_unregister_switch(ds);
289} 291}
290module_exit(mv88e6060_cleanup); 292
293static const struct of_device_id mv88e6060_of_match[] = {
294 {
295 .compatible = "marvell,mv88e6060",
296 },
297 { /* sentinel */ },
298};
299
300static struct mdio_driver mv88e6060_driver = {
301 .probe = mv88e6060_probe,
302 .remove = mv88e6060_remove,
303 .mdiodrv.driver = {
304 .name = "mv88e6060",
305 .of_match_table = mv88e6060_of_match,
306 },
307};
308
309mdio_module_driver(mv88e6060_driver);
291 310
292MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 311MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
293MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip"); 312MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");