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Diffstat (limited to 'drivers/mtd/nand/raw/qcom_nandc.c')
-rw-r--r--drivers/mtd/nand/raw/qcom_nandc.c32
1 files changed, 16 insertions, 16 deletions
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index ef75dfa62a4f..699d3cf49c6d 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -150,15 +150,15 @@
150#define NAND_VERSION_MINOR_SHIFT 16 150#define NAND_VERSION_MINOR_SHIFT 16
151 151
152/* NAND OP_CMDs */ 152/* NAND OP_CMDs */
153#define PAGE_READ 0x2 153#define OP_PAGE_READ 0x2
154#define PAGE_READ_WITH_ECC 0x3 154#define OP_PAGE_READ_WITH_ECC 0x3
155#define PAGE_READ_WITH_ECC_SPARE 0x4 155#define OP_PAGE_READ_WITH_ECC_SPARE 0x4
156#define PROGRAM_PAGE 0x6 156#define OP_PROGRAM_PAGE 0x6
157#define PAGE_PROGRAM_WITH_ECC 0x7 157#define OP_PAGE_PROGRAM_WITH_ECC 0x7
158#define PROGRAM_PAGE_SPARE 0x9 158#define OP_PROGRAM_PAGE_SPARE 0x9
159#define BLOCK_ERASE 0xa 159#define OP_BLOCK_ERASE 0xa
160#define FETCH_ID 0xb 160#define OP_FETCH_ID 0xb
161#define RESET_DEVICE 0xd 161#define OP_RESET_DEVICE 0xd
162 162
163/* Default Value for NAND_DEV_CMD_VLD */ 163/* Default Value for NAND_DEV_CMD_VLD */
164#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \ 164#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \
@@ -692,11 +692,11 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
692 692
693 if (read) { 693 if (read) {
694 if (host->use_ecc) 694 if (host->use_ecc)
695 cmd = PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE; 695 cmd = OP_PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
696 else 696 else
697 cmd = PAGE_READ | PAGE_ACC | LAST_PAGE; 697 cmd = OP_PAGE_READ | PAGE_ACC | LAST_PAGE;
698 } else { 698 } else {
699 cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE; 699 cmd = OP_PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
700 } 700 }
701 701
702 if (host->use_ecc) { 702 if (host->use_ecc) {
@@ -1170,7 +1170,7 @@ static int nandc_param(struct qcom_nand_host *host)
1170 * in use. we configure the controller to perform a raw read of 512 1170 * in use. we configure the controller to perform a raw read of 512
1171 * bytes to read onfi params 1171 * bytes to read onfi params
1172 */ 1172 */
1173 nandc_set_reg(nandc, NAND_FLASH_CMD, PAGE_READ | PAGE_ACC | LAST_PAGE); 1173 nandc_set_reg(nandc, NAND_FLASH_CMD, OP_PAGE_READ | PAGE_ACC | LAST_PAGE);
1174 nandc_set_reg(nandc, NAND_ADDR0, 0); 1174 nandc_set_reg(nandc, NAND_ADDR0, 0);
1175 nandc_set_reg(nandc, NAND_ADDR1, 0); 1175 nandc_set_reg(nandc, NAND_ADDR1, 0);
1176 nandc_set_reg(nandc, NAND_DEV0_CFG0, 0 << CW_PER_PAGE 1176 nandc_set_reg(nandc, NAND_DEV0_CFG0, 0 << CW_PER_PAGE
@@ -1224,7 +1224,7 @@ static int erase_block(struct qcom_nand_host *host, int page_addr)
1224 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); 1224 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1225 1225
1226 nandc_set_reg(nandc, NAND_FLASH_CMD, 1226 nandc_set_reg(nandc, NAND_FLASH_CMD,
1227 BLOCK_ERASE | PAGE_ACC | LAST_PAGE); 1227 OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
1228 nandc_set_reg(nandc, NAND_ADDR0, page_addr); 1228 nandc_set_reg(nandc, NAND_ADDR0, page_addr);
1229 nandc_set_reg(nandc, NAND_ADDR1, 0); 1229 nandc_set_reg(nandc, NAND_ADDR1, 0);
1230 nandc_set_reg(nandc, NAND_DEV0_CFG0, 1230 nandc_set_reg(nandc, NAND_DEV0_CFG0,
@@ -1255,7 +1255,7 @@ static int read_id(struct qcom_nand_host *host, int column)
1255 if (column == -1) 1255 if (column == -1)
1256 return 0; 1256 return 0;
1257 1257
1258 nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID); 1258 nandc_set_reg(nandc, NAND_FLASH_CMD, OP_FETCH_ID);
1259 nandc_set_reg(nandc, NAND_ADDR0, column); 1259 nandc_set_reg(nandc, NAND_ADDR0, column);
1260 nandc_set_reg(nandc, NAND_ADDR1, 0); 1260 nandc_set_reg(nandc, NAND_ADDR1, 0);
1261 nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, 1261 nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
@@ -1276,7 +1276,7 @@ static int reset(struct qcom_nand_host *host)
1276 struct nand_chip *chip = &host->chip; 1276 struct nand_chip *chip = &host->chip;
1277 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); 1277 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1278 1278
1279 nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE); 1279 nandc_set_reg(nandc, NAND_FLASH_CMD, OP_RESET_DEVICE);
1280 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); 1280 nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
1281 1281
1282 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); 1282 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);