1 files changed, 25 insertions, 1 deletions

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 279e326e397e..70fadc976795 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -1399,13 +1399,37 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
         mmc->caps              |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
                                   MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
 
-        if (host->cfg->clk_delays || host->use_new_timings)
+        /*
+         * Some H5 devices do not have signal traces precise enough to
+         * use HS DDR mode for their eMMC chips.
+         *
+         * We still enable HS DDR modes for all the other controller
+         * variants that support them.
+         */
+        if ((host->cfg->clk_delays || host->use_new_timings) &&
+            !of_device_is_compatible(pdev->dev.of_node,
+                                     "allwinner,sun50i-h5-emmc"))
                 mmc->caps      |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
 
         ret = mmc_of_parse(mmc);
         if (ret)
                 goto error_free_dma;
 
+        /*
+         * If we don't support delay chains in the SoC, we can't use any
+         * of the higher speed modes. Mask them out in case the device
+         * tree specifies the properties for them, which gets added to
+         * the caps by mmc_of_parse() above.
+         */
+        if (!(host->cfg->clk_delays || host->use_new_timings)) {
+                mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR |
+                               MMC_CAP_1_2V_DDR | MMC_CAP_UHS);
+                mmc->caps2 &= ~MMC_CAP2_HS200;
+        }
+
+        /* TODO: This driver doesn't support HS400 mode yet */
+        mmc->caps2 &= ~MMC_CAP2_HS400;
+
         ret = sunxi_mmc_init_host(host);
         if (ret)
                 goto error_free_dma;