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Diffstat (limited to 'drivers/misc/cxl/api.c')
-rw-r--r--drivers/misc/cxl/api.c71
1 files changed, 0 insertions, 71 deletions
diff --git a/drivers/misc/cxl/api.c b/drivers/misc/cxl/api.c
index 21d620e29fea..2e5862b7a074 100644
--- a/drivers/misc/cxl/api.c
+++ b/drivers/misc/cxl/api.c
@@ -11,7 +11,6 @@
11#include <linux/slab.h> 11#include <linux/slab.h>
12#include <linux/file.h> 12#include <linux/file.h>
13#include <misc/cxl.h> 13#include <misc/cxl.h>
14#include <linux/msi.h>
15#include <linux/module.h> 14#include <linux/module.h>
16#include <linux/mount.h> 15#include <linux/mount.h>
17#include <linux/sched/mm.h> 16#include <linux/sched/mm.h>
@@ -595,73 +594,3 @@ int cxl_get_max_irqs_per_process(struct pci_dev *dev)
595 return afu->irqs_max; 594 return afu->irqs_max;
596} 595}
597EXPORT_SYMBOL_GPL(cxl_get_max_irqs_per_process); 596EXPORT_SYMBOL_GPL(cxl_get_max_irqs_per_process);
598
599/*
600 * This is a special interrupt allocation routine called from the PHB's MSI
601 * setup function. When capi interrupts are allocated in this manner they must
602 * still be associated with a running context, but since the MSI APIs have no
603 * way to specify this we use the default context associated with the device.
604 *
605 * The Mellanox CX4 has a hardware limitation that restricts the maximum AFU
606 * interrupt number, so in order to overcome this their driver informs us of
607 * the restriction by setting the maximum interrupts per context, and we
608 * allocate additional contexts as necessary so that we can keep the AFU
609 * interrupt number within the supported range.
610 */
611int _cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
612{
613 struct cxl_context *ctx, *new_ctx, *default_ctx;
614 int remaining;
615 int rc;
616
617 ctx = default_ctx = cxl_get_context(pdev);
618 if (WARN_ON(!default_ctx))
619 return -ENODEV;
620
621 remaining = nvec;
622 while (remaining > 0) {
623 rc = cxl_allocate_afu_irqs(ctx, min(remaining, ctx->afu->irqs_max));
624 if (rc) {
625 pr_warn("%s: Failed to find enough free MSIs\n", pci_name(pdev));
626 return rc;
627 }
628 remaining -= ctx->afu->irqs_max;
629
630 if (ctx != default_ctx && default_ctx->status == STARTED) {
631 WARN_ON(cxl_start_context(ctx,
632 be64_to_cpu(default_ctx->elem->common.wed),
633 NULL));
634 }
635
636 if (remaining > 0) {
637 new_ctx = cxl_dev_context_init(pdev);
638 if (IS_ERR(new_ctx)) {
639 pr_warn("%s: Failed to allocate enough contexts for MSIs\n", pci_name(pdev));
640 return -ENOSPC;
641 }
642 list_add(&new_ctx->extra_irq_contexts, &ctx->extra_irq_contexts);
643 ctx = new_ctx;
644 }
645 }
646
647 return 0;
648}
649/* Exported via cxl_base */
650
651void _cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev)
652{
653 struct cxl_context *ctx, *pos, *tmp;
654
655 ctx = cxl_get_context(pdev);
656 if (WARN_ON(!ctx))
657 return;
658
659 cxl_free_afu_irqs(ctx);
660 list_for_each_entry_safe(pos, tmp, &ctx->extra_irq_contexts, extra_irq_contexts) {
661 cxl_stop_context(pos);
662 cxl_free_afu_irqs(pos);
663 list_del(&pos->extra_irq_contexts);
664 cxl_release_context(pos);
665 }
666}
667/* Exported via cxl_base */