1 files changed, 51 insertions, 12 deletions

diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
index 013bdfff2d4d..bf4959f4225b 100644
--- a/drivers/iommu/amd_iommu_init.c
+++ b/drivers/iommu/amd_iommu_init.c
@@ -228,6 +228,10 @@ static int amd_iommu_enable_interrupts(void);
 static int __init iommu_go_to_state(enum iommu_init_state state);
 static void init_device_table_dma(void);
 
+static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
+                                    u8 bank, u8 cntr, u8 fxn,
+                                    u64 *value, bool is_write);
+
 static inline void update_last_devid(u16 devid)
 {
         if (devid > amd_iommu_last_bdf)
@@ -1016,6 +1020,34 @@ static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
 }
 
 /*
+ * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
+ * Workaround:
+ *     BIOS should enable ATS write permission check by setting
+ *     L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
+ */
+static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
+{
+        u32 value;
+
+        if ((boot_cpu_data.x86 != 0x15) ||
+            (boot_cpu_data.x86_model < 0x30) ||
+            (boot_cpu_data.x86_model > 0x3f))
+                return;
+
+        /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
+        value = iommu_read_l2(iommu, 0x47);
+
+        if (value & BIT(0))
+                return;
+
+        /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
+        iommu_write_l2(iommu, 0x47, value | BIT(0));
+
+        pr_info("AMD-Vi: Applying ATS write check workaround for IOMMU at %s\n",
+                dev_name(&iommu->dev->dev));
+}
+
+/*
  * This function clues the initialization function for one IOMMU
  * together and also allocates the command buffer and programs the
  * hardware. It does NOT enable the IOMMU. This is done afterwards.
@@ -1142,8 +1174,8 @@ static void init_iommu_perf_ctr(struct amd_iommu *iommu)
         amd_iommu_pc_present = true;
 
         /* Check if the performance counters can be written to */
-        if ((0 != amd_iommu_pc_get_set_reg_val(0, 0, 0, 0, &val, true)) ||
-            (0 != amd_iommu_pc_get_set_reg_val(0, 0, 0, 0, &val2, false)) ||
+        if ((0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val, true)) ||
+            (0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val2, false)) ||
             (val != val2)) {
                 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
                 amd_iommu_pc_present = false;
@@ -1284,6 +1316,7 @@ static int iommu_init_pci(struct amd_iommu *iommu)
         }
 
         amd_iommu_erratum_746_workaround(iommu);
+        amd_iommu_ats_write_check_workaround(iommu);
 
         iommu->iommu_dev = iommu_device_create(&iommu->dev->dev, iommu,
                                                amd_iommu_groups, "ivhd%d",
@@ -2283,22 +2316,15 @@ u8 amd_iommu_pc_get_max_counters(u16 devid)
 }
 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
 
-int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
+static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
+                                    u8 bank, u8 cntr, u8 fxn,
                                     u64 *value, bool is_write)
 {
-        struct amd_iommu *iommu;
         u32 offset;
         u32 max_offset_lim;
 
-        /* Make sure the IOMMU PC resource is available */
-        if (!amd_iommu_pc_present)
-                return -ENODEV;
-
-        /* Locate the iommu associated with the device ID */
-        iommu = amd_iommu_rlookup_table[devid];
-
         /* Check for valid iommu and pc register indexing */
-        if (WARN_ON((iommu == NULL) || (fxn > 0x28) || (fxn & 7)))
+        if (WARN_ON((fxn > 0x28) || (fxn & 7)))
                 return -ENODEV;
 
         offset = (u32)(((0x40|bank) << 12) | (cntr << 8) | fxn);
@@ -2322,3 +2348,16 @@ int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
         return 0;
 }
 EXPORT_SYMBOL(amd_iommu_pc_get_set_reg_val);
+
+int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
+                                    u64 *value, bool is_write)
+{
+        struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
+
+        /* Make sure the IOMMU PC resource is available */
+        if (!amd_iommu_pc_present || iommu == NULL)
+                return -ENODEV;
+
+        return iommu_pc_get_set_reg_val(iommu, bank, cntr, fxn,
+                                        value, is_write);
+}