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path: root/drivers/infiniband/hw/cxgb4/t4.h
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Diffstat (limited to 'drivers/infiniband/hw/cxgb4/t4.h')
-rw-r--r--drivers/infiniband/hw/cxgb4/t4.h44
1 files changed, 37 insertions, 7 deletions
diff --git a/drivers/infiniband/hw/cxgb4/t4.h b/drivers/infiniband/hw/cxgb4/t4.h
index 24f369046ef3..70004425d695 100644
--- a/drivers/infiniband/hw/cxgb4/t4.h
+++ b/drivers/infiniband/hw/cxgb4/t4.h
@@ -52,6 +52,7 @@
52#define T4_STAG_UNSET 0xffffffff 52#define T4_STAG_UNSET 0xffffffff
53#define T4_FW_MAJ 0 53#define T4_FW_MAJ 0
54#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1) 54#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
55#define A_PCIE_MA_SYNC 0x30b4
55 56
56struct t4_status_page { 57struct t4_status_page {
57 __be32 rsvd1; /* flit 0 - hw owns */ 58 __be32 rsvd1; /* flit 0 - hw owns */
@@ -65,7 +66,7 @@ struct t4_status_page {
65 66
66#define T4_EQ_ENTRY_SIZE 64 67#define T4_EQ_ENTRY_SIZE 64
67 68
68#define T4_SQ_NUM_SLOTS 4 69#define T4_SQ_NUM_SLOTS 5
69#define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS) 70#define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
70#define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ 71#define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
71 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 72 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
@@ -78,7 +79,7 @@ struct t4_status_page {
78 sizeof(struct fw_ri_rdma_write_wr) - \ 79 sizeof(struct fw_ri_rdma_write_wr) - \
79 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 80 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
80#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \ 81#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
81 sizeof(struct fw_ri_immd))) 82 sizeof(struct fw_ri_immd)) & ~31UL)
82#define T4_MAX_FR_DEPTH (T4_MAX_FR_IMMD / sizeof(u64)) 83#define T4_MAX_FR_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
83 84
84#define T4_RQ_NUM_SLOTS 2 85#define T4_RQ_NUM_SLOTS 2
@@ -266,10 +267,36 @@ struct t4_swsqe {
266 u16 idx; 267 u16 idx;
267}; 268};
268 269
270static inline pgprot_t t4_pgprot_wc(pgprot_t prot)
271{
272#if defined(__i386__) || defined(__x86_64__)
273 return pgprot_writecombine(prot);
274#elif defined(CONFIG_PPC64)
275 return __pgprot((pgprot_val(prot) | _PAGE_NO_CACHE) &
276 ~(pgprot_t)_PAGE_GUARDED);
277#else
278 return pgprot_noncached(prot);
279#endif
280}
281
282static inline int t4_ocqp_supported(void)
283{
284#if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
285 return 1;
286#else
287 return 0;
288#endif
289}
290
291enum {
292 T4_SQ_ONCHIP = (1<<0),
293};
294
269struct t4_sq { 295struct t4_sq {
270 union t4_wr *queue; 296 union t4_wr *queue;
271 dma_addr_t dma_addr; 297 dma_addr_t dma_addr;
272 DEFINE_DMA_UNMAP_ADDR(mapping); 298 DEFINE_DMA_UNMAP_ADDR(mapping);
299 unsigned long phys_addr;
273 struct t4_swsqe *sw_sq; 300 struct t4_swsqe *sw_sq;
274 struct t4_swsqe *oldest_read; 301 struct t4_swsqe *oldest_read;
275 u64 udb; 302 u64 udb;
@@ -280,6 +307,7 @@ struct t4_sq {
280 u16 cidx; 307 u16 cidx;
281 u16 pidx; 308 u16 pidx;
282 u16 wq_pidx; 309 u16 wq_pidx;
310 u16 flags;
283}; 311};
284 312
285struct t4_swrqe { 313struct t4_swrqe {
@@ -350,6 +378,11 @@ static inline void t4_rq_consume(struct t4_wq *wq)
350 wq->rq.cidx = 0; 378 wq->rq.cidx = 0;
351} 379}
352 380
381static inline int t4_sq_onchip(struct t4_sq *sq)
382{
383 return sq->flags & T4_SQ_ONCHIP;
384}
385
353static inline int t4_sq_empty(struct t4_wq *wq) 386static inline int t4_sq_empty(struct t4_wq *wq)
354{ 387{
355 return wq->sq.in_use == 0; 388 return wq->sq.in_use == 0;
@@ -396,30 +429,27 @@ static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc)
396 429
397static inline int t4_wq_in_error(struct t4_wq *wq) 430static inline int t4_wq_in_error(struct t4_wq *wq)
398{ 431{
399 return wq->sq.queue[wq->sq.size].status.qp_err; 432 return wq->rq.queue[wq->rq.size].status.qp_err;
400} 433}
401 434
402static inline void t4_set_wq_in_error(struct t4_wq *wq) 435static inline void t4_set_wq_in_error(struct t4_wq *wq)
403{ 436{
404 wq->sq.queue[wq->sq.size].status.qp_err = 1;
405 wq->rq.queue[wq->rq.size].status.qp_err = 1; 437 wq->rq.queue[wq->rq.size].status.qp_err = 1;
406} 438}
407 439
408static inline void t4_disable_wq_db(struct t4_wq *wq) 440static inline void t4_disable_wq_db(struct t4_wq *wq)
409{ 441{
410 wq->sq.queue[wq->sq.size].status.db_off = 1;
411 wq->rq.queue[wq->rq.size].status.db_off = 1; 442 wq->rq.queue[wq->rq.size].status.db_off = 1;
412} 443}
413 444
414static inline void t4_enable_wq_db(struct t4_wq *wq) 445static inline void t4_enable_wq_db(struct t4_wq *wq)
415{ 446{
416 wq->sq.queue[wq->sq.size].status.db_off = 0;
417 wq->rq.queue[wq->rq.size].status.db_off = 0; 447 wq->rq.queue[wq->rq.size].status.db_off = 0;
418} 448}
419 449
420static inline int t4_wq_db_enabled(struct t4_wq *wq) 450static inline int t4_wq_db_enabled(struct t4_wq *wq)
421{ 451{
422 return !wq->sq.queue[wq->sq.size].status.db_off; 452 return !wq->rq.queue[wq->rq.size].status.db_off;
423} 453}
424 454
425struct t4_cq { 455struct t4_cq {