156 files changed, 1633 insertions, 808 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 992f00b65be4..e055d5be1c3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1820,6 +1820,8 @@ struct amdgpu_asic_funcs {
         /* MM block clocks */
         int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
         int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
+        /* query virtual capabilities */
+        u32 (*get_virtual_caps)(struct amdgpu_device *adev);
 };
 
 /*
@@ -1914,8 +1916,12 @@ void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
 
 
 /* GPU virtualization */
+#define AMDGPU_VIRT_CAPS_SRIOV_EN       (1 << 0)
+#define AMDGPU_VIRT_CAPS_IS_VF          (1 << 1)
 struct amdgpu_virtualization {
         bool supports_sr_iov;
+        bool is_virtual;
+        u32 caps;
 };
 
 /*
@@ -2204,6 +2210,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
+#define amdgpu_asic_get_virtual_caps(adev) ((adev)->asic_funcs->get_virtual_caps((adev)))
 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 199f76baf22c..cf6f49fc1c75 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -696,6 +696,17 @@ static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
         return result;
 }
 
+static int amdgpu_cgs_rel_firmware(struct cgs_device *cgs_device, enum cgs_ucode_id type)
+{
+        CGS_FUNC_ADEV;
+        if ((CGS_UCODE_ID_SMU == type) || (CGS_UCODE_ID_SMU_SK == type)) {
+                release_firmware(adev->pm.fw);
+                return 0;
+        }
+        /* cannot release other firmware because they are not created by cgs */
+        return -EINVAL;
+}
+
 static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
                                         enum cgs_ucode_id type,
                                         struct cgs_firmware_info *info)
@@ -898,7 +909,7 @@ static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device,
         struct cgs_acpi_method_argument *argument = NULL;
         uint32_t i, count;
         acpi_status status;
-        int result;
+        int result = 0;
         uint32_t func_no = 0xFFFFFFFF;
 
         handle = ACPI_HANDLE(&adev->pdev->dev);
@@ -1125,6 +1136,7 @@ static const struct cgs_ops amdgpu_cgs_ops = {
         amdgpu_cgs_pm_query_clock_limits,
         amdgpu_cgs_set_camera_voltages,
         amdgpu_cgs_get_firmware_info,
+        amdgpu_cgs_rel_firmware,
         amdgpu_cgs_set_powergating_state,
         amdgpu_cgs_set_clockgating_state,
         amdgpu_cgs_get_active_displays_info,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index bb8b149786d7..6e920086af46 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -827,8 +827,10 @@ static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
  */
 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
 {
-        if (adev->mode_info.atom_context)
+        if (adev->mode_info.atom_context) {
                 kfree(adev->mode_info.atom_context->scratch);
+                kfree(adev->mode_info.atom_context->iio);
+        }
         kfree(adev->mode_info.atom_context);
         adev->mode_info.atom_context = NULL;
         kfree(adev->mode_info.atom_card_info);
@@ -1325,6 +1327,11 @@ static int amdgpu_fini(struct amdgpu_device *adev)
                 adev->ip_block_status[i].valid = false;
         }
 
+        for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
+                if (adev->ip_blocks[i].funcs->late_fini)
+                        adev->ip_blocks[i].funcs->late_fini((void *)adev);
+        }
+
         return 0;
 }
 
@@ -1378,6 +1385,15 @@ static int amdgpu_resume(struct amdgpu_device *adev)
         return 0;
 }
 
+static bool amdgpu_device_is_virtual(void)
+{
+#ifdef CONFIG_X86
+        return boot_cpu_has(X86_FEATURE_HYPERVISOR);
+#else
+        return false;
+#endif
+}
+
 /**
  * amdgpu_device_init - initialize the driver
  *
@@ -1512,9 +1528,14 @@ int amdgpu_device_init(struct amdgpu_device *adev,
         adev->virtualization.supports_sr_iov =
                 amdgpu_atombios_has_gpu_virtualization_table(adev);
 
+        /* Check if we are executing in a virtualized environment */
+        adev->virtualization.is_virtual = amdgpu_device_is_virtual();
+        adev->virtualization.caps = amdgpu_asic_get_virtual_caps(adev);
+
         /* Post card if necessary */
         if (!amdgpu_card_posted(adev) ||
-            adev->virtualization.supports_sr_iov) {
+            (adev->virtualization.is_virtual &&
+             !(adev->virtualization.caps & AMDGPU_VIRT_CAPS_SRIOV_EN))) {
                 if (!adev->bios) {
                         dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
                         return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 40a23704a981..d851ea15059f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -447,7 +447,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                         dev_info.max_memory_clock = adev->pm.default_mclk * 10;
                 }
                 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
-                dev_info.num_rb_pipes = adev->gfx.config.num_rbs;
+                dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
+                        adev->gfx.config.max_shader_engines;
                 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
                 dev_info._pad = 0;
                 dev_info.ids_flags = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 589b36e8c5cf..0e13d80d2a95 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -270,30 +270,28 @@ static ssize_t amdgpu_set_pp_force_state(struct device *dev,
         struct drm_device *ddev = dev_get_drvdata(dev);
         struct amdgpu_device *adev = ddev->dev_private;
         enum amd_pm_state_type state = 0;
-        long idx;
+        unsigned long idx;
         int ret;
 
         if (strlen(buf) == 1)
                 adev->pp_force_state_enabled = false;
-        else {
-                ret = kstrtol(buf, 0, &idx);
+        else if (adev->pp_enabled) {
+                struct pp_states_info data;
 
-                if (ret) {
+                ret = kstrtoul(buf, 0, &idx);
+                if (ret || idx >= ARRAY_SIZE(data.states)) {
                         count = -EINVAL;
                         goto fail;
                 }
 
-                if (adev->pp_enabled) {
-                        struct pp_states_info data;
-                        amdgpu_dpm_get_pp_num_states(adev, &data);
-                        state = data.states[idx];
-                        /* only set user selected power states */
-                        if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
-                                state != POWER_STATE_TYPE_DEFAULT) {
-                                amdgpu_dpm_dispatch_task(adev,
-                                                AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
-                                adev->pp_force_state_enabled = true;
-                        }
+                amdgpu_dpm_get_pp_num_states(adev, &data);
+                state = data.states[idx];
+                /* only set user selected power states */
+                if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
+                    state != POWER_STATE_TYPE_DEFAULT) {
+                        amdgpu_dpm_dispatch_task(adev,
+                                        AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
+                        adev->pp_force_state_enabled = true;
                 }
         }
 fail:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index 6bd961fb43dc..82256558e0f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -183,13 +183,6 @@ static int amdgpu_pp_sw_fini(void *handle)
         if (ret)
                 return ret;
 
-#ifdef CONFIG_DRM_AMD_POWERPLAY
-        if (adev->pp_enabled) {
-                amdgpu_pm_sysfs_fini(adev);
-                amd_powerplay_fini(adev->powerplay.pp_handle);
-        }
-#endif
-
         return ret;
 }
 
@@ -223,6 +216,22 @@ static int amdgpu_pp_hw_fini(void *handle)
         return ret;
 }
 
+static void amdgpu_pp_late_fini(void *handle)
+{
+#ifdef CONFIG_DRM_AMD_POWERPLAY
+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+        if (adev->pp_enabled) {
+                amdgpu_pm_sysfs_fini(adev);
+                amd_powerplay_fini(adev->powerplay.pp_handle);
+        }
+
+        if (adev->powerplay.ip_funcs->late_fini)
+                adev->powerplay.ip_funcs->late_fini(
+                          adev->powerplay.pp_handle);
+#endif
+}
+
 static int amdgpu_pp_suspend(void *handle)
 {
         int ret = 0;
@@ -311,6 +320,7 @@ const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
         .sw_fini = amdgpu_pp_sw_fini,
         .hw_init = amdgpu_pp_hw_init,
         .hw_fini = amdgpu_pp_hw_fini,
+        .late_fini = amdgpu_pp_late_fini,
         .suspend = amdgpu_pp_suspend,
         .resume = amdgpu_pp_resume,
         .is_idle = amdgpu_pp_is_idle,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 3b02272db678..870f9494252c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -343,6 +343,7 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring)
         ring->ring = NULL;
         ring->ring_obj = NULL;
 
+        amdgpu_wb_free(ring->adev, ring->cond_exe_offs);
         amdgpu_wb_free(ring->adev, ring->fence_offs);
         amdgpu_wb_free(ring->adev, ring->rptr_offs);
         amdgpu_wb_free(ring->adev, ring->wptr_offs);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
index 8bf84efafb04..48618ee324eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
@@ -115,6 +115,7 @@ int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
                 return r;
         }
         r = amdgpu_bo_kmap(sa_manager->bo, &sa_manager->cpu_ptr);
+        memset(sa_manager->cpu_ptr, 0, sa_manager->size);
         amdgpu_bo_unreserve(sa_manager->bo);
         return r;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 01abfc21b4a2..e19520c4b4b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -253,19 +253,20 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 {
         int r;
 
-        if (adev->uvd.vcpu_bo == NULL)
-                return 0;
+        kfree(adev->uvd.saved_bo);
 
         amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
 
-        r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
-        if (!r) {
-                amdgpu_bo_kunmap(adev->uvd.vcpu_bo);
-                amdgpu_bo_unpin(adev->uvd.vcpu_bo);
-                amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
-        }
+        if (adev->uvd.vcpu_bo) {
+                r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
+                if (!r) {
+                        amdgpu_bo_kunmap(adev->uvd.vcpu_bo);
+                        amdgpu_bo_unpin(adev->uvd.vcpu_bo);
+                        amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
+                }
 
-        amdgpu_bo_unref(&adev->uvd.vcpu_bo);
+                amdgpu_bo_unref(&adev->uvd.vcpu_bo);
+        }
 
         amdgpu_ring_fini(&adev->uvd.ring);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index ea407db1fbcf..5ec1f1e9c983 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -6221,6 +6221,9 @@ static int ci_dpm_sw_fini(void *handle)
         ci_dpm_fini(adev);
         mutex_unlock(&adev->pm.mutex);
 
+        release_firmware(adev->pm.fw);
+        adev->pm.fw = NULL;
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 07bc795a4ca9..910431808542 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -962,6 +962,12 @@ static bool cik_read_bios_from_rom(struct amdgpu_device *adev,
         return true;
 }
 
+static u32 cik_get_virtual_caps(struct amdgpu_device *adev)
+{
+        /* CIK does not support SR-IOV */
+        return 0;
+}
+
 static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = {
         {mmGRBM_STATUS, false},
         {mmGB_ADDR_CONFIG, false},
@@ -2007,6 +2013,7 @@ static const struct amdgpu_asic_funcs cik_asic_funcs =
         .get_xclk = &cik_get_xclk,
         .set_uvd_clocks = &cik_set_uvd_clocks,
         .set_vce_clocks = &cik_set_vce_clocks,
+        .get_virtual_caps = &cik_get_virtual_caps,
         /* these should be moved to their own ip modules */
         .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
         .wait_for_mc_idle = &gmc_v7_0_mc_wait_for_idle,
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 518dca43b133..9dc4e24e31e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -66,6 +66,16 @@ MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
 
 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
 
+
+static void cik_sdma_free_microcode(struct amdgpu_device *adev)
+{
+        int i;
+        for (i = 0; i < adev->sdma.num_instances; i++) {
+                        release_firmware(adev->sdma.instance[i].fw);
+                        adev->sdma.instance[i].fw = NULL;
+        }
+}
+
 /*
  * sDMA - System DMA
  * Starting with CIK, the GPU has new asynchronous
@@ -419,6 +429,8 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
                 /* Initialize the ring buffer's read and write pointers */
                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
+                WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
+                WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 
                 /* set the wb address whether it's enabled or not */
                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
@@ -446,7 +458,12 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 
                 ring->ready = true;
+        }
+
+        cik_sdma_enable(adev, true);
 
+        for (i = 0; i < adev->sdma.num_instances; i++) {
+                ring = &adev->sdma.instance[i].ring;
                 r = amdgpu_ring_test_ring(ring);
                 if (r) {
                         ring->ready = false;
@@ -529,8 +546,8 @@ static int cik_sdma_start(struct amdgpu_device *adev)
         if (r)
                 return r;
 
-        /* unhalt the MEs */
-        cik_sdma_enable(adev, true);
+        /* halt the engine before programing */
+        cik_sdma_enable(adev, false);
 
         /* start the gfx rings and rlc compute queues */
         r = cik_sdma_gfx_resume(adev);
@@ -998,6 +1015,7 @@ static int cik_sdma_sw_fini(void *handle)
         for (i = 0; i < adev->sdma.num_instances; i++)
                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 
+        cik_sdma_free_microcode(adev);
         return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c b/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
index 245cabf06575..ed03b75175d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
@@ -72,6 +72,11 @@ static int fiji_dpm_sw_init(void *handle)
 
 static int fiji_dpm_sw_fini(void *handle)
 {
+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+        release_firmware(adev->pm.fw);
+        adev->pm.fw = NULL;
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 7f18a53ab53a..fc8ff4d3ccf8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -991,6 +991,22 @@ out:
         return err;
 }
 
+static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)
+{
+        release_firmware(adev->gfx.pfp_fw);
+        adev->gfx.pfp_fw = NULL;
+        release_firmware(adev->gfx.me_fw);
+        adev->gfx.me_fw = NULL;
+        release_firmware(adev->gfx.ce_fw);
+        adev->gfx.ce_fw = NULL;
+        release_firmware(adev->gfx.mec_fw);
+        adev->gfx.mec_fw = NULL;
+        release_firmware(adev->gfx.mec2_fw);
+        adev->gfx.mec2_fw = NULL;
+        release_firmware(adev->gfx.rlc_fw);
+        adev->gfx.rlc_fw = NULL;
+}
+
 /**
  * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
  *
@@ -4489,6 +4505,7 @@ static int gfx_v7_0_sw_fini(void *handle)
         gfx_v7_0_cp_compute_fini(adev);
         gfx_v7_0_rlc_fini(adev);
         gfx_v7_0_mec_fini(adev);
+        gfx_v7_0_free_microcode(adev);
 
         return 0;
 }
@@ -4816,7 +4833,7 @@ static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
         case 2:
                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
                         ring = &adev->gfx.compute_ring[i];
-                        if ((ring->me == me_id) & (ring->pipe == pipe_id))
+                        if ((ring->me == me_id) && (ring->pipe == pipe_id))
                                 amdgpu_fence_process(ring);
                 }
                 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index f19bab68fd83..1a5cbaff1e34 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -297,7 +297,8 @@ static const u32 polaris11_golden_common_all[] =
 static const u32 golden_settings_polaris10_a11[] =
 {
         mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
-        mmCB_HW_CONTROL, 0xfffdf3cf, 0x00006208,
+        mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
+        mmCB_HW_CONTROL_2, 0, 0x0f000000,
         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
@@ -836,6 +837,26 @@ err1:
         return r;
 }
 
+
+static void gfx_v8_0_free_microcode(struct amdgpu_device *adev) {
+        release_firmware(adev->gfx.pfp_fw);
+        adev->gfx.pfp_fw = NULL;
+        release_firmware(adev->gfx.me_fw);
+        adev->gfx.me_fw = NULL;
+        release_firmware(adev->gfx.ce_fw);
+        adev->gfx.ce_fw = NULL;
+        release_firmware(adev->gfx.rlc_fw);
+        adev->gfx.rlc_fw = NULL;
+        release_firmware(adev->gfx.mec_fw);
+        adev->gfx.mec_fw = NULL;
+        if ((adev->asic_type != CHIP_STONEY) &&
+            (adev->asic_type != CHIP_TOPAZ))
+                release_firmware(adev->gfx.mec2_fw);
+        adev->gfx.mec2_fw = NULL;
+
+        kfree(adev->gfx.rlc.register_list_format);
+}
+
 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
 {
         const char *chip_name;
@@ -1983,7 +2004,7 @@ static int gfx_v8_0_sw_fini(void *handle)
 
         gfx_v8_0_rlc_fini(adev);
 
-        kfree(adev->gfx.rlc.register_list_format);
+        gfx_v8_0_free_microcode(adev);
 
         return 0;
 }
@@ -3974,11 +3995,15 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
                 amdgpu_ring_write(ring, 0x3a00161a);
                 amdgpu_ring_write(ring, 0x0000002e);
                 break;
-        case CHIP_TOPAZ:
         case CHIP_CARRIZO:
                 amdgpu_ring_write(ring, 0x00000002);
                 amdgpu_ring_write(ring, 0x00000000);
                 break;
+        case CHIP_TOPAZ:
+                amdgpu_ring_write(ring, adev->gfx.config.num_rbs == 1 ?
+                                0x00000000 : 0x00000002);
+                amdgpu_ring_write(ring, 0x00000000);
+                break;
         case CHIP_STONEY:
                 amdgpu_ring_write(ring, 0x00000000);
                 amdgpu_ring_write(ring, 0x00000000);
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
index 460bc8ad37e6..825ccd63f2dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
@@ -72,6 +72,11 @@ static int iceland_dpm_sw_init(void *handle)
 
 static int iceland_dpm_sw_fini(void *handle)
 {
+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+        release_firmware(adev->pm.fw);
+        adev->pm.fw = NULL;
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index f4c3130d3fdb..b556bd0a8797 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -105,6 +105,15 @@ static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
         }
 }
 
+static void sdma_v2_4_free_microcode(struct amdgpu_device *adev)
+{
+        int i;
+        for (i = 0; i < adev->sdma.num_instances; i++) {
+                release_firmware(adev->sdma.instance[i].fw);
+                adev->sdma.instance[i].fw = NULL;
+        }
+}
+
 /**
  * sdma_v2_4_init_microcode - load ucode images from disk
  *
@@ -461,6 +470,8 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
                 /* Initialize the ring buffer's read and write pointers */
                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
+                WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
+                WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 
                 /* set the wb address whether it's enabled or not */
                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
@@ -489,7 +500,11 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 
                 ring->ready = true;
+        }
 
+        sdma_v2_4_enable(adev, true);
+        for (i = 0; i < adev->sdma.num_instances; i++) {
+                ring = &adev->sdma.instance[i].ring;
                 r = amdgpu_ring_test_ring(ring);
                 if (r) {
                         ring->ready = false;
@@ -580,8 +595,8 @@ static int sdma_v2_4_start(struct amdgpu_device *adev)
                         return -EINVAL;
         }
 
-        /* unhalt the MEs */
-        sdma_v2_4_enable(adev, true);
+        /* halt the engine before programing */
+        sdma_v2_4_enable(adev, false);
 
         /* start the gfx rings and rlc compute queues */
         r = sdma_v2_4_gfx_resume(adev);
@@ -1012,6 +1027,7 @@ static int sdma_v2_4_sw_fini(void *handle)
         for (i = 0; i < adev->sdma.num_instances; i++)
                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 
+        sdma_v2_4_free_microcode(adev);
         return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 31d99b0010f7..532ea88da66a 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -236,6 +236,15 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
         }
 }
 
+static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
+{
+        int i;
+        for (i = 0; i < adev->sdma.num_instances; i++) {
+                release_firmware(adev->sdma.instance[i].fw);
+                adev->sdma.instance[i].fw = NULL;
+        }
+}
+
 /**
  * sdma_v3_0_init_microcode - load ucode images from disk
  *
@@ -672,6 +681,8 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
                 /* Initialize the ring buffer's read and write pointers */
                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
+                WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
+                WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 
                 /* set the wb address whether it's enabled or not */
                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
@@ -711,7 +722,15 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 
                 ring->ready = true;
+        }
+
+        /* unhalt the MEs */
+        sdma_v3_0_enable(adev, true);
+        /* enable sdma ring preemption */
+        sdma_v3_0_ctx_switch_enable(adev, true);
 
+        for (i = 0; i < adev->sdma.num_instances; i++) {
+                ring = &adev->sdma.instance[i].ring;
                 r = amdgpu_ring_test_ring(ring);
                 if (r) {
                         ring->ready = false;
@@ -804,10 +823,9 @@ static int sdma_v3_0_start(struct amdgpu_device *adev)
                 }
         }
 
-        /* unhalt the MEs */
-        sdma_v3_0_enable(adev, true);
-        /* enable sdma ring preemption */
-        sdma_v3_0_ctx_switch_enable(adev, true);
+        /* disble sdma engine before programing it */
+        sdma_v3_0_ctx_switch_enable(adev, false);
+        sdma_v3_0_enable(adev, false);
 
         /* start the gfx rings and rlc compute queues */
         r = sdma_v3_0_gfx_resume(adev);
@@ -1247,6 +1265,7 @@ static int sdma_v3_0_sw_fini(void *handle)
         for (i = 0; i < adev->sdma.num_instances; i++)
                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 
+        sdma_v3_0_free_microcode(adev);
         return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
index b7615cefcac4..f06f6f4dc3a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
@@ -71,6 +71,11 @@ static int tonga_dpm_sw_init(void *handle)
 
 static int tonga_dpm_sw_fini(void *handle)
 {
+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+        release_firmware(adev->pm.fw);
+        adev->pm.fw = NULL;
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 2c88d0b66cf3..a65c96029476 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -421,6 +421,20 @@ static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
         return true;
 }
 
+static u32 vi_get_virtual_caps(struct amdgpu_device *adev)
+{
+        u32 caps = 0;
+        u32 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
+
+        if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE))
+                caps |= AMDGPU_VIRT_CAPS_SRIOV_EN;
+
+        if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER))
+                caps |= AMDGPU_VIRT_CAPS_IS_VF;
+
+        return caps;
+}
+
 static const struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
         {mmGB_MACROTILE_MODE7, true},
 };
@@ -1118,6 +1132,7 @@ static const struct amdgpu_asic_funcs vi_asic_funcs =
         .get_xclk = &vi_get_xclk,
         .set_uvd_clocks = &vi_set_uvd_clocks,
         .set_vce_clocks = &vi_set_vce_clocks,
+        .get_virtual_caps = &vi_get_virtual_caps,
         /* these should be moved to their own ip modules */
         .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
         .wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index ac005796b71c..7708d90b9da9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -242,13 +242,19 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn,
         pqm_uninit(&p->pqm);
 
         /* Iterate over all process device data structure and check
-         * if we should reset all wavefronts */
-        list_for_each_entry(pdd, &p->per_device_data, per_device_list)
+         * if we should delete debug managers and reset all wavefronts
+         */
+        list_for_each_entry(pdd, &p->per_device_data, per_device_list) {
+                if ((pdd->dev->dbgmgr) &&
+                                (pdd->dev->dbgmgr->pasid == p->pasid))
+                        kfd_dbgmgr_destroy(pdd->dev->dbgmgr);
+
                 if (pdd->reset_wavefronts) {
                         pr_warn("amdkfd: Resetting all wave fronts\n");
                         dbgdev_wave_reset_wavefronts(pdd->dev, p);
                         pdd->reset_wavefronts = false;
                 }
+        }
 
         mutex_unlock(&p->mutex);
 
@@ -404,42 +410,52 @@ void kfd_unbind_process_from_device(struct kfd_dev *dev, unsigned int pasid)
 
         idx = srcu_read_lock(&kfd_processes_srcu);
 
+        /*
+         * Look for the process that matches the pasid. If there is no such
+         * process, we either released it in amdkfd's own notifier, or there
+         * is a bug. Unfortunately, there is no way to tell...
+         */
         hash_for_each_rcu(kfd_processes_table, i, p, kfd_processes)
-                if (p->pasid == pasid)
-                        break;
+                if (p->pasid == pasid) {
 
-        srcu_read_unlock(&kfd_processes_srcu, idx);
+                        srcu_read_unlock(&kfd_processes_srcu, idx);
 
-        BUG_ON(p->pasid != pasid);
+                        pr_debug("Unbinding process %d from IOMMU\n", pasid);
 
-        mutex_lock(&p->mutex);
+                        mutex_lock(&p->mutex);
 
-        if ((dev->dbgmgr) && (dev->dbgmgr->pasid == p->pasid))
-                kfd_dbgmgr_destroy(dev->dbgmgr);
+                        if ((dev->dbgmgr) && (dev->dbgmgr->pasid == p->pasid))
+                                kfd_dbgmgr_destroy(dev->dbgmgr);
 
-        pqm_uninit(&p->pqm);
+                        pqm_uninit(&p->pqm);
 
-        pdd = kfd_get_process_device_data(dev, p);
+                        pdd = kfd_get_process_device_data(dev, p);
 
-        if (!pdd) {
-                mutex_unlock(&p->mutex);
-                return;
-        }
+                        if (!pdd) {
+                                mutex_unlock(&p->mutex);
+                                return;
+                        }
 
-        if (pdd->reset_wavefronts) {
-                dbgdev_wave_reset_wavefronts(pdd->dev, p);
-                pdd->reset_wavefronts = false;
-        }
+                        if (pdd->reset_wavefronts) {
+                                dbgdev_wave_reset_wavefronts(pdd->dev, p);
+                                pdd->reset_wavefronts = false;
+                        }
 
-        /*
-         * Just mark pdd as unbound, because we still need it to call
-         * amd_iommu_unbind_pasid() in when the process exits.
-         * We don't call amd_iommu_unbind_pasid() here
-         * because the IOMMU called us.
-         */
-        pdd->bound = false;
+                        /*
+                         * Just mark pdd as unbound, because we still need it
+                         * to call amd_iommu_unbind_pasid() in when the
+                         * process exits.
+                         * We don't call amd_iommu_unbind_pasid() here
+                         * because the IOMMU called us.
+                         */
+                        pdd->bound = false;
 
-        mutex_unlock(&p->mutex);
+                        mutex_unlock(&p->mutex);
+
+                        return;
+                }
+
+        srcu_read_unlock(&kfd_processes_srcu, idx);
 }
 
 struct kfd_process_device *kfd_get_first_process_device_data(struct kfd_process *p)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 74909e72a009..884c96f50c3d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -666,7 +666,7 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr,
                         dev->node_props.simd_count);
 
         if (dev->mem_bank_count < dev->node_props.mem_banks_count) {
-                pr_warn("kfd: mem_banks_count truncated from %d to %d\n",
+                pr_info_once("kfd: mem_banks_count truncated from %d to %d\n",
                                 dev->node_props.mem_banks_count,
                                 dev->mem_bank_count);
                 sysfs_show_32bit_prop(buffer, "mem_banks_count",
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 6080951d539d..afce1edbe250 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -157,6 +157,7 @@ struct amd_ip_funcs {
         int (*hw_init)(void *handle);
         /* tears down the hw state */
         int (*hw_fini)(void *handle);
+        void (*late_fini)(void *handle);
         /* handles IP specific hw/sw changes for suspend */
         int (*suspend)(void *handle);
         /* handles IP specific hw/sw changes for resume */
diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h
index 32f3e345de08..3493da5c8f0e 100644
--- a/drivers/gpu/drm/amd/include/atombios.h
+++ b/drivers/gpu/drm/amd/include/atombios.h
@@ -5538,6 +5538,78 @@ typedef struct  _ATOM_ASIC_PROFILING_INFO_V3_5
   ULONG  ulReserved[12];
 }ATOM_ASIC_PROFILING_INFO_V3_5;
 
+/* for Polars10/11 AVFS parameters */
+typedef struct  _ATOM_ASIC_PROFILING_INFO_V3_6
+{
+  ATOM_COMMON_TABLE_HEADER         asHeader;
+  ULONG  ulMaxVddc;
+  ULONG  ulMinVddc;
+  USHORT usLkgEuseIndex;
+  UCHAR  ucLkgEfuseBitLSB;
+  UCHAR  ucLkgEfuseLength;
+  ULONG  ulLkgEncodeLn_MaxDivMin;
+  ULONG  ulLkgEncodeMax;
+  ULONG  ulLkgEncodeMin;
+  EFUSE_LINEAR_FUNC_PARAM sRoFuse;
+  ULONG  ulEvvDefaultVddc;
+  ULONG  ulEvvNoCalcVddc;
+  ULONG  ulSpeed_Model;
+  ULONG  ulSM_A0;
+  ULONG  ulSM_A1;
+  ULONG  ulSM_A2;
+  ULONG  ulSM_A3;
+  ULONG  ulSM_A4;
+  ULONG  ulSM_A5;
+  ULONG  ulSM_A6;
+  ULONG  ulSM_A7;
+  UCHAR  ucSM_A0_sign;
+  UCHAR  ucSM_A1_sign;
+  UCHAR  ucSM_A2_sign;
+  UCHAR  ucSM_A3_sign;
+  UCHAR  ucSM_A4_sign;
+  UCHAR  ucSM_A5_sign;
+  UCHAR  ucSM_A6_sign;
+  UCHAR  ucSM_A7_sign;
+  ULONG  ulMargin_RO_a;
+  ULONG  ulMargin_RO_b;
+  ULONG  ulMargin_RO_c;
+  ULONG  ulMargin_fixed;
+  ULONG  ulMargin_Fmax_mean;
+  ULONG  ulMargin_plat_mean;
+  ULONG  ulMargin_Fmax_sigma;
+  ULONG  ulMargin_plat_sigma;
+  ULONG  ulMargin_DC_sigma;
+  ULONG  ulLoadLineSlop;
+  ULONG  ulaTDClimitPerDPM[8];
+  ULONG  ulaNoCalcVddcPerDPM[8];
+  ULONG  ulAVFS_meanNsigma_Acontant0;
+  ULONG  ulAVFS_meanNsigma_Acontant1;
+  ULONG  ulAVFS_meanNsigma_Acontant2;
+  USHORT usAVFS_meanNsigma_DC_tol_sigma;
+  USHORT usAVFS_meanNsigma_Platform_mean;
+  USHORT usAVFS_meanNsigma_Platform_sigma;
+  ULONG  ulGB_VDROOP_TABLE_CKSOFF_a0;
+  ULONG  ulGB_VDROOP_TABLE_CKSOFF_a1;
+  ULONG  ulGB_VDROOP_TABLE_CKSOFF_a2;
+  ULONG  ulGB_VDROOP_TABLE_CKSON_a0;
+  ULONG  ulGB_VDROOP_TABLE_CKSON_a1;
+  ULONG  ulGB_VDROOP_TABLE_CKSON_a2;
+  ULONG  ulAVFSGB_FUSE_TABLE_CKSOFF_m1;
+  USHORT usAVFSGB_FUSE_TABLE_CKSOFF_m2;
+  ULONG  ulAVFSGB_FUSE_TABLE_CKSOFF_b;
+  ULONG  ulAVFSGB_FUSE_TABLE_CKSON_m1;
+  USHORT usAVFSGB_FUSE_TABLE_CKSON_m2;
+  ULONG  ulAVFSGB_FUSE_TABLE_CKSON_b;
+  USHORT usMaxVoltage_0_25mv;
+  UCHAR  ucEnableGB_VDROOP_TABLE_CKSOFF;
+  UCHAR  ucEnableGB_VDROOP_TABLE_CKSON;
+  UCHAR  ucEnableGB_FUSE_TABLE_CKSOFF;
+  UCHAR  ucEnableGB_FUSE_TABLE_CKSON;
+  USHORT usPSM_Age_ComFactor;
+  UCHAR  ucEnableApplyAVFS_CKS_OFF_Voltage;
+  UCHAR  ucReserved;
+}ATOM_ASIC_PROFILING_INFO_V3_6;
+
 
 typedef struct _ATOM_SCLK_FCW_RANGE_ENTRY_V1{
   ULONG  ulMaxSclkFreq;
diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
index a461e155a160..7464daf89ca1 100644
--- a/drivers/gpu/drm/amd/include/cgs_common.h
+++ b/drivers/gpu/drm/amd/include/cgs_common.h
@@ -581,6 +581,9 @@ typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
                                      enum cgs_ucode_id type,
                                      struct cgs_firmware_info *info);
 
+typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device,
+                                         enum cgs_ucode_id type);
+
 typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device,
                                   enum amd_ip_block_type block_type,
                                   enum amd_powergating_state state);
@@ -645,6 +648,7 @@ struct cgs_ops {
         cgs_set_camera_voltages_t set_camera_voltages;
         /* Firmware Info */
         cgs_get_firmware_info get_firmware_info;
+        cgs_rel_firmware rel_firmware;
         /* cg pg interface*/
         cgs_set_powergating_state set_powergating_state;
         cgs_set_clockgating_state set_clockgating_state;
@@ -738,6 +742,8 @@ struct cgs_device
         CGS_CALL(set_camera_voltages,dev,mask,voltages)
 #define cgs_get_firmware_info(dev, type, info)  \
         CGS_CALL(get_firmware_info, dev, type, info)
+#define cgs_rel_firmware(dev, type)     \
+        CGS_CALL(rel_firmware, dev, type)
 #define cgs_set_powergating_state(dev, block_type, state)       \
         CGS_CALL(set_powergating_state, dev, block_type, state)
 #define cgs_set_clockgating_state(dev, block_type, state)       \
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 8e345bfddb69..e629f8a9fe93 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -73,11 +73,14 @@ static int pp_sw_init(void *handle)
 
         ret = hwmgr->hwmgr_func->backend_init(hwmgr);
         if (ret)
-                goto err;
+                goto err1;
 
         pr_info("amdgpu: powerplay initialized\n");
 
         return 0;
+err1:
+        if (hwmgr->pptable_func->pptable_fini)
+                hwmgr->pptable_func->pptable_fini(hwmgr);
 err:
         pr_err("amdgpu: powerplay initialization failed\n");
         return ret;
@@ -100,6 +103,9 @@ static int pp_sw_fini(void *handle)
         if (hwmgr->hwmgr_func->backend_fini != NULL)
                 ret = hwmgr->hwmgr_func->backend_fini(hwmgr);
 
+        if (hwmgr->pptable_func->pptable_fini)
+                hwmgr->pptable_func->pptable_fini(hwmgr);
+
         return ret;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c
index 46410e3c7349..fb88e4e5d625 100644
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c
@@ -58,9 +58,6 @@ static void pem_fini(struct pp_eventmgr *eventmgr)
         pem_unregister_interrupts(eventmgr);
 
         pem_handle_event(eventmgr, AMD_PP_EVENT_UNINITIALIZE, &event_data);
-
-        if (eventmgr != NULL)
-                kfree(eventmgr);
 }
 
 int eventmgr_init(struct pp_instance *handle)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
index 24a16e49b571..92912ab20944 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
@@ -633,6 +633,8 @@ static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
         data->vddci_control = FIJI_VOLTAGE_CONTROL_NONE;
         data->mvdd_control = FIJI_VOLTAGE_CONTROL_NONE;
 
+        data->force_pcie_gen = PP_PCIEGenInvalid;
+
         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
                 data->voltage_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
@@ -1830,7 +1832,7 @@ static uint16_t fiji_find_closest_vddci(struct pp_hwmgr *hwmgr, uint16_t vddci)
 
         PP_ASSERT_WITH_CODE(false,
                         "VDDCI is larger than max VDDCI in VDDCI Voltage Table!",
-                        return vddci_table->entries[i].value);
+                        return vddci_table->entries[i-1].value);
 }
 
 static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index fa208ada6892..efb77eda7508 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -306,10 +306,14 @@ int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
 {
         PHM_FUNC_CHECK(hwmgr);
 
-        if (hwmgr->hwmgr_func->store_cc6_data == NULL)
+        if (display_config == NULL)
                 return -EINVAL;
 
         hwmgr->display_config = *display_config;
+
+        if (hwmgr->hwmgr_func->store_cc6_data == NULL)
+                return -EINVAL;
+
         /* to do pass other display configuration in furture */
 
         if (hwmgr->hwmgr_func->store_cc6_data)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 1c48917da3cf..20f20e075588 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -93,6 +93,13 @@ int hwmgr_fini(struct pp_hwmgr *hwmgr)
         if (hwmgr == NULL || hwmgr->ps == NULL)
                 return -EINVAL;
 
+        /* do hwmgr finish*/
+        kfree(hwmgr->backend);
+
+        kfree(hwmgr->start_thermal_controller.function_list);
+
+        kfree(hwmgr->set_temperature_range.function_list);
+
         kfree(hwmgr->ps);
         kfree(hwmgr);
         return 0;
@@ -462,7 +469,7 @@ uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, u
 
         PP_ASSERT_WITH_CODE(false,
                         "VDDCI is larger than max VDDCI in VDDCI Voltage Table!",
-                        return vddci_table->entries[i].value);
+                        return vddci_table->entries[i-1].value);
 }
 
 int phm_find_boot_level(void *table,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h
index 347fef127ce9..2930a3355948 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h
@@ -39,6 +39,7 @@ struct phm_ppt_v1_clock_voltage_dependency_record {
         uint8_t phases;
         uint8_t cks_enable;
         uint8_t cks_voffset;
+        uint32_t sclk_offset;
 };
 
 typedef struct phm_ppt_v1_clock_voltage_dependency_record phm_ppt_v1_clock_voltage_dependency_record;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index aa6be033f21b..64ee78f7d41e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -999,7 +999,7 @@ static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
                                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
                                                 (dep_table->entries[i].vddc -
                                                                 (uint16_t)data->vddc_vddci_delta));
-                                *voltage |= (vddci * VOLTAGE_SCALE) <<  VDDCI_SHIFT;
+                                *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
                         }
 
                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
@@ -1296,7 +1296,6 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
         }
 
         mem_level->MclkFrequency = clock;
-        mem_level->StutterEnable = 0;
         mem_level->EnabledForThrottle = 1;
         mem_level->EnabledForActivity = 0;
         mem_level->UpHyst = 0;
@@ -1304,7 +1303,6 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
         mem_level->VoltageDownHyst = 0;
         mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
         mem_level->StutterEnable = false;
-
         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
 
         data->display_timing.num_existing_displays = info.display_count;
@@ -1363,7 +1361,7 @@ static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
          * a higher state by default such that we are not effected by
          * up threshold or and MCLK DPM latency.
          */
-        levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
+        levels[0].ActivityLevel = 0x1f;
         CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
 
         data->smc_state_table.MemoryDpmLevelCount =
@@ -1761,12 +1759,9 @@ static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
 
 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
 {
-        uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
-                        volt_with_cks, value;
-        uint16_t clock_freq_u16;
+        uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-        uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
-                        volt_offset = 0;
+        uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
         struct phm_ppt_v1_information *table_info =
                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
@@ -1778,50 +1773,38 @@ static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
          * if the part is SS or FF. if RO >= 1660MHz, part is FF.
          */
         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-                        ixSMU_EFUSE_0 + (146 * 4));
-        efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-                        ixSMU_EFUSE_0 + (148 * 4));
+                        ixSMU_EFUSE_0 + (67 * 4));
         efuse &= 0xFF000000;
         efuse = efuse >> 24;
-        efuse2 &= 0xF;
-
-        if (efuse2 == 1)
-                ro = (2300 - 1350) * efuse / 255 + 1350;
-        else
-                ro = (2500 - 1000) * efuse / 255 + 1000;
 
-        if (ro >= 1660)
-                type = 0;
-        else
-                type = 1;
+        if (hwmgr->chip_id == CHIP_POLARIS10) {
+                min = 1000;
+                max = 2300;
+        } else {
+                min = 1100;
+                max = 2100;
+        }
 
-        /* Populate Stretch amount */
-        data->smc_state_table.ClockStretcherAmount = stretch_amount;
+        ro = efuse * (max -min)/255 + min;
 
         /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
         for (i = 0; i < sclk_table->count; i++) {
                 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
                                 sclk_table->entries[i].cks_enable << i;
-                volt_without_cks = (uint32_t)((14041 *
-                        (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
-                        (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
-                volt_with_cks = (uint32_t)((13946 *
-                        (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
-                        (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
+
+                volt_without_cks =  (uint32_t)(((ro - 40) * 1000 - 2753594 - sclk_table->entries[i].clk/100 * 136418 /1000) / \
+                                        (sclk_table->entries[i].clk/100 * 1132925 /10000 - 242418)/100);
+
+                volt_with_cks = (uint32_t)((ro * 1000 -2396351 - sclk_table->entries[i].clk/100 * 329021/1000) / \
+                                (sclk_table->entries[i].clk/10000 * 649434 /1000  - 18005)/10);
+
                 if (volt_without_cks >= volt_with_cks)
                         volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
                                         sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
+
                 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
         }
 
-        PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-                        STRETCH_ENABLE, 0x0);
-        PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-                        masterReset, 0x1);
-        /* PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, staticEnable, 0x1); */
-        PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-                        masterReset, 0x0);
-
         /* Populate CKS Lookup Table */
         if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
                 stretch_amount2 = 0;
@@ -1835,69 +1818,6 @@ static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
                                 return -EINVAL);
         }
 
-        value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-                        ixPWR_CKS_CNTL);
-        value &= 0xFFC2FF87;
-        data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
-                        polaris10_clock_stretcher_lookup_table[stretch_amount2][0];
-        data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
-                        polaris10_clock_stretcher_lookup_table[stretch_amount2][1];
-        clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
-                        GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].SclkSetting.SclkFrequency) / 100);
-        if (polaris10_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16
-        && polaris10_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) {
-                /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
-                value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
-                /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
-                value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
-                /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
-                value |= (polaris10_clock_stretch_amount_conversion
-                                [polaris10_clock_stretcher_lookup_table[stretch_amount2][3]]
-                                 [stretch_amount]) << 3;
-        }
-        CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq);
-        CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq);
-        data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
-                        polaris10_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
-        data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
-                        (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
-
-        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-                        ixPWR_CKS_CNTL, value);
-
-        /* Populate DDT Lookup Table */
-        for (i = 0; i < 4; i++) {
-                /* Assign the minimum and maximum VID stored
-                 * in the last row of Clock Stretcher Voltage Table.
-                 */
-                data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].minVID =
-                                (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][2];
-                data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].maxVID =
-                                (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][3];
-                /* Loop through each SCLK and check the frequency
-                 * to see if it lies within the frequency for clock stretcher.
-                 */
-                for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
-                        cks_setting = 0;
-                        clock_freq = PP_SMC_TO_HOST_UL(
-                                        data->smc_state_table.GraphicsLevel[j].SclkSetting.SclkFrequency);
-                        /* Check the allowed frequency against the sclk level[j].
-                         *  Sclk's endianness has already been converted,
-                         *  and it's in 10Khz unit,
-                         *  as opposed to Data table, which is in Mhz unit.
-                         */
-                        if (clock_freq >= (polaris10_clock_stretcher_ddt_table[type][i][0]) * 100) {
-                                cks_setting |= 0x2;
-                                if (clock_freq < (polaris10_clock_stretcher_ddt_table[type][i][1]) * 100)
-                                        cks_setting |= 0x1;
-                        }
-                        data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting
-                                                        |= cks_setting << (j * 2);
-                }
-                CONVERT_FROM_HOST_TO_SMC_US(
-                        data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting);
-        }
-
         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
         value &= 0xFFFFFFFE;
         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
@@ -1956,6 +1876,90 @@ static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
         return 0;
 }
 
+
+int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
+{
+        struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+        SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
+        int result = 0;
+        struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
+        AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
+        AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
+        uint32_t tmp, i;
+        struct pp_smumgr *smumgr = hwmgr->smumgr;
+        struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
+
+        struct phm_ppt_v1_information *table_info =
+                        (struct phm_ppt_v1_information *)hwmgr->pptable;
+        struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
+                        table_info->vdd_dep_on_sclk;
+
+
+        if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
+                return result;
+
+        result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
+
+        if (0 == result) {
+                table->BTCGB_VDROOP_TABLE[0].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
+                table->BTCGB_VDROOP_TABLE[0].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
+                table->BTCGB_VDROOP_TABLE[0].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
+                table->BTCGB_VDROOP_TABLE[1].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
+                table->BTCGB_VDROOP_TABLE[1].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
+                table->BTCGB_VDROOP_TABLE[1].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
+                table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
+                table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
+                table->AVFSGB_VDROOP_TABLE[0].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
+                table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
+                table->AVFSGB_VDROOP_TABLE[0].m2_shift  = 12;
+                table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
+                table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
+                table->AVFSGB_VDROOP_TABLE[1].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
+                table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
+                table->AVFSGB_VDROOP_TABLE[1].m2_shift  = 12;
+                table->MaxVoltage                = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
+                AVFS_meanNsigma.Aconstant[0]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
+                AVFS_meanNsigma.Aconstant[1]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
+                AVFS_meanNsigma.Aconstant[2]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
+                AVFS_meanNsigma.DC_tol_sigma      = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
+                AVFS_meanNsigma.Platform_mean     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
+                AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
+                AVFS_meanNsigma.Platform_sigma     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
+
+                for (i = 0; i < NUM_VFT_COLUMNS; i++) {
+                        AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
+                        AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
+                }
+
+                result = polaris10_read_smc_sram_dword(smumgr,
+                                SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
+                                &tmp, data->sram_end);
+
+                polaris10_copy_bytes_to_smc(smumgr,
+                                        tmp,
+                                        (uint8_t *)&AVFS_meanNsigma,
+                                        sizeof(AVFS_meanNsigma_t),
+                                        data->sram_end);
+
+                result = polaris10_read_smc_sram_dword(smumgr,
+                                SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
+                                &tmp, data->sram_end);
+                polaris10_copy_bytes_to_smc(smumgr,
+                                        tmp,
+                                        (uint8_t *)&AVFS_SclkOffset,
+                                        sizeof(AVFS_Sclk_Offset_t),
+                                        data->sram_end);
+
+                data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
+                                                (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
+                                                (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
+                                                (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
+                data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
+        }
+        return result;
+}
+
+
 /**
 * Initializes the SMC table and uploads it
 *
@@ -2056,6 +2060,10 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
                                 "Failed to populate Clock Stretcher Data Table!",
                                 return result);
         }
+
+        result = polaris10_populate_avfs_parameters(hwmgr);
+        PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
+
         table->CurrSclkPllRange = 0xff;
         table->GraphicsVoltageChangeEnable  = 1;
         table->GraphicsThermThrottleEnable  = 1;
@@ -2252,6 +2260,9 @@ static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
 static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
 {
         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+        uint32_t soft_register_value = 0;
+        uint32_t handshake_disables_offset = data->soft_regs_start
+                                + offsetof(SMU74_SoftRegisters, HandshakeDisables);
 
         /* enable SCLK dpm */
         if (!data->sclk_dpm_key_disabled)
@@ -2262,6 +2273,12 @@ static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
 
         /* enable MCLK dpm */
         if (0 == data->mclk_dpm_key_disabled) {
+/* Disable UVD - SMU handshake for MCLK. */
+                soft_register_value = cgs_read_ind_register(hwmgr->device,
+                                        CGS_IND_REG__SMC, handshake_disables_offset);
+                soft_register_value |= SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
+                cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+                                handshake_disables_offset, soft_register_value);
 
                 PP_ASSERT_WITH_CODE(
                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
@@ -2269,7 +2286,6 @@ static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
                                 "Failed to enable MCLK DPM during DPM Start Function!",
                                 return -1);
 
-
                 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
 
                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
@@ -2606,6 +2622,7 @@ int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
 
         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                                                 PHM_PlatformCaps_FanSpeedInTableIsRPM);
+
         if (hwmgr->chip_id == CHIP_POLARIS11)
                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                                         PHM_PlatformCaps_SPLLShutdownSupport);
@@ -2938,6 +2955,11 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
 
+        data->enable_tdc_limit_feature = true;
+        data->enable_pkg_pwr_tracking_feature = true;
+        data->force_pcie_gen = PP_PCIEGenInvalid;
+        data->mclk_stutter_mode_threshold = 40000;
+
         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
                 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
@@ -2962,6 +2984,10 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
         }
 
+        if (table_info->cac_dtp_table->usClockStretchAmount != 0)
+                phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                                        PHM_PlatformCaps_ClockStretcher);
+
         polaris10_set_features_platform_caps(hwmgr);
 
         polaris10_init_dpm_defaults(hwmgr);
@@ -3520,10 +3546,11 @@ static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
-        ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
-                        (ATOM_Tonga_SCLK_Dependency_Table *)
+        PPTable_Generic_SubTable_Header *sclk_dep_table =
+                        (PPTable_Generic_SubTable_Header *)
                         (((unsigned long)powerplay_table) +
                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
+
         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
                         (ATOM_Tonga_MCLK_Dependency_Table *)
                         (((unsigned long)powerplay_table) +
@@ -3575,7 +3602,11 @@ static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
         /* Performance levels are arranged from low to high. */
         performance_level->memory_clock = mclk_dep_table->entries
                         [state_entry->ucMemoryClockIndexLow].ulMclk;
-        performance_level->engine_clock = sclk_dep_table->entries
+        if (sclk_dep_table->ucRevId == 0)
+                performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
+                        [state_entry->ucEngineClockIndexLow].ulSclk;
+        else if (sclk_dep_table->ucRevId == 1)
+                performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
                         [state_entry->ucEngineClockIndexLow].ulSclk;
         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
                         state_entry->ucPCIEGenLow);
@@ -3586,8 +3617,14 @@ static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
                         [polaris10_power_state->performance_level_count++]);
         performance_level->memory_clock = mclk_dep_table->entries
                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
-        performance_level->engine_clock = sclk_dep_table->entries
+
+        if (sclk_dep_table->ucRevId == 0)
+                performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
                         [state_entry->ucEngineClockIndexHigh].ulSclk;
+        else if (sclk_dep_table->ucRevId == 1)
+                performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
+                        [state_entry->ucEngineClockIndexHigh].ulSclk;
+
         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
                         state_entry->ucPCIEGenHigh);
         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
@@ -3645,7 +3682,6 @@ static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
                 switch (state->classification.ui_label) {
                 case PP_StateUILabel_Performance:
                         data->use_pcie_performance_levels = true;
-
                         for (i = 0; i < ps->performance_level_count; i++) {
                                 if (data->pcie_gen_performance.max <
                                                 ps->performance_levels[i].pcie_gen)
@@ -3661,7 +3697,6 @@ static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
                                                 ps->performance_levels[i].pcie_lane)
                                         data->pcie_lane_performance.max =
                                                         ps->performance_levels[i].pcie_lane;
-
                                 if (data->pcie_lane_performance.min >
                                                 ps->performance_levels[i].pcie_lane)
                                         data->pcie_lane_performance.min =
@@ -4187,12 +4222,9 @@ int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
 {
         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
         uint32_t mm_boot_level_offset, mm_boot_level_value;
-        struct phm_ppt_v1_information *table_info =
-                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
 
         if (!bgate) {
-                data->smc_state_table.SamuBootLevel =
-                                (uint8_t) (table_info->mm_dep_table->count - 1);
+                data->smc_state_table.SamuBootLevel = 0;
                 mm_boot_level_offset = data->dpm_table_start +
                                 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
                 mm_boot_level_offset /= 4;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
index beedf35cbfa6..d717789441f5 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
@@ -312,6 +312,9 @@ struct polaris10_hwmgr {
 
         /* soft pptable for re-uploading into smu */
         void *soft_pp_table;
+
+        uint32_t                              avfs_vdroop_override_setting;
+        bool                                  apply_avfs_cks_off_voltage;
 };
 
 /* To convert to Q8.8 format for firmware */
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
index 0b99ab3ba0c5..ae96f14b827c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
@@ -286,7 +286,7 @@ int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
 
                 if (polaris10_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
                                 (uint8_t *)&data->power_tune_table,
-                                sizeof(struct SMU74_Discrete_PmFuses), data->sram_end))
+                                (sizeof(struct SMU74_Discrete_PmFuses) - 92), data->sram_end))
                         PP_ASSERT_WITH_CODE(false,
                                         "Attempt to download PmFuseTable Failed!",
                                         return -EINVAL);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
index aba167f7d167..b206632d4650 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
@@ -625,10 +625,14 @@ static int tf_polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
         int ret;
         struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr);
         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
+        struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 
-        if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS)
+        if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
                 return 0;
 
+        ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+                        PPSMC_MSG_SetGBDroopSettings, data->avfs_vdroop_override_setting);
+
         ret = (smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs) == 0) ?
                         0 : -1;
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c
index 58742e0d1492..a3c38bbd1e94 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c
@@ -44,6 +44,20 @@ bool acpi_atcs_functions_supported(void *device, uint32_t index)
         return result == 0 ? (output_buf.function_bits & (1 << (index - 1))) != 0 : false;
 }
 
+bool acpi_atcs_notify_pcie_device_ready(void *device)
+{
+        int32_t temp_buffer = 1;
+
+        return cgs_call_acpi_method(device, CGS_ACPI_METHOD_ATCS,
+                                ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION,
+                                                &temp_buffer,
+                                                NULL,
+                                                0,
+                                                sizeof(temp_buffer),
+                                                0);
+}
+
+
 int acpi_pcie_perf_request(void *device, uint8_t perf_req, bool advertise)
 {
         struct atcs_pref_req_input atcs_input;
@@ -52,7 +66,7 @@ int acpi_pcie_perf_request(void *device, uint8_t perf_req, bool advertise)
         int result;
         struct cgs_system_info info = {0};
 
-        if (!acpi_atcs_functions_supported(device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST))
+        if( 0 != acpi_atcs_notify_pcie_device_ready(device))
                 return -EINVAL;
 
         info.size = sizeof(struct cgs_system_info);
@@ -77,7 +91,7 @@ int acpi_pcie_perf_request(void *device, uint8_t perf_req, bool advertise)
                                                 ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST,
                                                 &atcs_input,
                                                 &atcs_output,
-                                                0,
+                                                1,
                                                 sizeof(atcs_input),
                                                 sizeof(atcs_output));
                 if (result != 0)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
index da9f5f1b6dc2..bf4e18fd3872 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
@@ -1302,3 +1302,46 @@ int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctr
 
         return 0;
 }
+
+int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param)
+{
+        ATOM_ASIC_PROFILING_INFO_V3_6 *profile = NULL;
+
+        if (param == NULL)
+                return -EINVAL;
+
+        profile = (ATOM_ASIC_PROFILING_INFO_V3_6 *)
+                        cgs_atom_get_data_table(hwmgr->device,
+                                        GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo),
+                                        NULL, NULL, NULL);
+        if (!profile)
+                return -1;
+
+        param->ulAVFS_meanNsigma_Acontant0 = profile->ulAVFS_meanNsigma_Acontant0;
+        param->ulAVFS_meanNsigma_Acontant1 = profile->ulAVFS_meanNsigma_Acontant1;
+        param->ulAVFS_meanNsigma_Acontant2 = profile->ulAVFS_meanNsigma_Acontant2;
+        param->usAVFS_meanNsigma_DC_tol_sigma = profile->usAVFS_meanNsigma_DC_tol_sigma;
+        param->usAVFS_meanNsigma_Platform_mean = profile->usAVFS_meanNsigma_Platform_mean;
+        param->usAVFS_meanNsigma_Platform_sigma = profile->usAVFS_meanNsigma_Platform_sigma;
+        param->ulGB_VDROOP_TABLE_CKSOFF_a0 = profile->ulGB_VDROOP_TABLE_CKSOFF_a0;
+        param->ulGB_VDROOP_TABLE_CKSOFF_a1 = profile->ulGB_VDROOP_TABLE_CKSOFF_a1;
+        param->ulGB_VDROOP_TABLE_CKSOFF_a2 = profile->ulGB_VDROOP_TABLE_CKSOFF_a2;
+        param->ulGB_VDROOP_TABLE_CKSON_a0 = profile->ulGB_VDROOP_TABLE_CKSON_a0;
+        param->ulGB_VDROOP_TABLE_CKSON_a1 = profile->ulGB_VDROOP_TABLE_CKSON_a1;
+        param->ulGB_VDROOP_TABLE_CKSON_a2 = profile->ulGB_VDROOP_TABLE_CKSON_a2;
+        param->ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = profile->ulAVFSGB_FUSE_TABLE_CKSOFF_m1;
+        param->usAVFSGB_FUSE_TABLE_CKSOFF_m2 = profile->usAVFSGB_FUSE_TABLE_CKSOFF_m2;
+        param->ulAVFSGB_FUSE_TABLE_CKSOFF_b = profile->ulAVFSGB_FUSE_TABLE_CKSOFF_b;
+        param->ulAVFSGB_FUSE_TABLE_CKSON_m1 = profile->ulAVFSGB_FUSE_TABLE_CKSON_m1;
+        param->usAVFSGB_FUSE_TABLE_CKSON_m2 = profile->usAVFSGB_FUSE_TABLE_CKSON_m2;
+        param->ulAVFSGB_FUSE_TABLE_CKSON_b = profile->ulAVFSGB_FUSE_TABLE_CKSON_b;
+        param->usMaxVoltage_0_25mv = profile->usMaxVoltage_0_25mv;
+        param->ucEnableGB_VDROOP_TABLE_CKSOFF = profile->ucEnableGB_VDROOP_TABLE_CKSOFF;
+        param->ucEnableGB_VDROOP_TABLE_CKSON = profile->ucEnableGB_VDROOP_TABLE_CKSON;
+        param->ucEnableGB_FUSE_TABLE_CKSOFF = profile->ucEnableGB_FUSE_TABLE_CKSOFF;
+        param->ucEnableGB_FUSE_TABLE_CKSON = profile->ucEnableGB_FUSE_TABLE_CKSON;
+        param->usPSM_Age_ComFactor = profile->usPSM_Age_ComFactor;
+        param->ucEnableApplyAVFS_CKS_OFF_Voltage = profile->ucEnableApplyAVFS_CKS_OFF_Voltage;
+
+        return 0;
+}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
index d24ebb566905..248c5db5f380 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
@@ -250,6 +250,35 @@ struct pp_atomctrl_gpio_pin_assignment {
 };
 typedef struct pp_atomctrl_gpio_pin_assignment pp_atomctrl_gpio_pin_assignment;
 
+struct pp_atom_ctrl__avfs_parameters {
+        uint32_t  ulAVFS_meanNsigma_Acontant0;
+        uint32_t  ulAVFS_meanNsigma_Acontant1;
+        uint32_t  ulAVFS_meanNsigma_Acontant2;
+        uint16_t usAVFS_meanNsigma_DC_tol_sigma;
+        uint16_t usAVFS_meanNsigma_Platform_mean;
+        uint16_t usAVFS_meanNsigma_Platform_sigma;
+        uint32_t  ulGB_VDROOP_TABLE_CKSOFF_a0;
+        uint32_t  ulGB_VDROOP_TABLE_CKSOFF_a1;
+        uint32_t  ulGB_VDROOP_TABLE_CKSOFF_a2;
+        uint32_t  ulGB_VDROOP_TABLE_CKSON_a0;
+        uint32_t  ulGB_VDROOP_TABLE_CKSON_a1;
+        uint32_t  ulGB_VDROOP_TABLE_CKSON_a2;
+        uint32_t  ulAVFSGB_FUSE_TABLE_CKSOFF_m1;
+        uint16_t  usAVFSGB_FUSE_TABLE_CKSOFF_m2;
+        uint32_t  ulAVFSGB_FUSE_TABLE_CKSOFF_b;
+        uint32_t  ulAVFSGB_FUSE_TABLE_CKSON_m1;
+        uint16_t  usAVFSGB_FUSE_TABLE_CKSON_m2;
+        uint32_t  ulAVFSGB_FUSE_TABLE_CKSON_b;
+        uint16_t  usMaxVoltage_0_25mv;
+        uint8_t  ucEnableGB_VDROOP_TABLE_CKSOFF;
+        uint8_t  ucEnableGB_VDROOP_TABLE_CKSON;
+        uint8_t  ucEnableGB_FUSE_TABLE_CKSOFF;
+        uint8_t  ucEnableGB_FUSE_TABLE_CKSON;
+        uint16_t usPSM_Age_ComFactor;
+        uint8_t  ucEnableApplyAVFS_CKS_OFF_Voltage;
+        uint8_t  ucReserved;
+};
+
 extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment);
 extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
 extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr);
@@ -278,5 +307,8 @@ extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clo
 extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
                                 uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
 extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table);
+
+extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param);
+
 #endif
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
index 16fed487973b..233eb7f36c1d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
@@ -2847,27 +2847,6 @@ static int tonga_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
                 }
         }
 
-        /* Initialize Vddc DPM table based on allow Vddc values.  And populate corresponding std values. */
-        for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
-                data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].vddc;
-                /* tonga_hwmgr->dpm_table.VddcTable.dpm_levels[i].param1 = stdVoltageTable->entries[i].Leakage; */
-                /* param1 is for corresponding std voltage */
-                data->dpm_table.vddc_table.dpm_levels[i].enabled = 1;
-        }
-        data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
-
-        if (NULL != allowed_vdd_mclk_table) {
-                /* Initialize Vddci DPM table based on allow Mclk values */
-                for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
-                        data->dpm_table.vdd_ci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].vddci;
-                        data->dpm_table.vdd_ci_table.dpm_levels[i].enabled = 1;
-                        data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].mvdd;
-                        data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1;
-                }
-                data->dpm_table.vdd_ci_table.count = allowed_vdd_mclk_table->count;
-                data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
-        }
-
         /* setup PCIE gen speed levels*/
         tonga_setup_default_pcie_tables(hwmgr);
 
@@ -4510,6 +4489,7 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
         data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_NONE;
         data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_NONE;
         data->mvdd_control = TONGA_VOLTAGE_CONTROL_NONE;
+        data->force_pcie_gen = PP_PCIEGenInvalid;
 
         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
                                 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h
index 1b44f4e9b8f5..f127198aafc4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h
@@ -197,6 +197,22 @@ typedef struct _ATOM_Tonga_SCLK_Dependency_Table {
         ATOM_Tonga_SCLK_Dependency_Record entries[1];                            /* Dynamically allocate entries. */
 } ATOM_Tonga_SCLK_Dependency_Table;
 
+typedef struct _ATOM_Polaris_SCLK_Dependency_Record {
+        UCHAR  ucVddInd;                                                                                        /* Base voltage */
+        USHORT usVddcOffset;                                                                            /* Offset relative to base voltage */
+        ULONG ulSclk;
+        USHORT usEdcCurrent;
+        UCHAR  ucReliabilityTemperature;
+        UCHAR  ucCKSVOffsetandDisable;                  /* Bits 0~6: Voltage offset for CKS, Bit 7: Disable/enable for the SCLK level. */
+        ULONG  ulSclkOffset;
+} ATOM_Polaris_SCLK_Dependency_Record;
+
+typedef struct _ATOM_Polaris_SCLK_Dependency_Table {
+        UCHAR ucRevId;
+        UCHAR ucNumEntries;                                                     /* Number of entries. */
+        ATOM_Polaris_SCLK_Dependency_Record entries[1];                          /* Dynamically allocate entries. */
+} ATOM_Polaris_SCLK_Dependency_Table;
+
 typedef struct _ATOM_Tonga_PCIE_Record {
         UCHAR ucPCIEGenSpeed;
         UCHAR usPCIELaneWidth;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
index 10e3630ee39d..671fdb4d615a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
@@ -408,41 +408,78 @@ static int get_mclk_voltage_dependency_table(
 static int get_sclk_voltage_dependency_table(
                 struct pp_hwmgr *hwmgr,
                 phm_ppt_v1_clock_voltage_dependency_table **pp_tonga_sclk_dep_table,
-                const ATOM_Tonga_SCLK_Dependency_Table * sclk_dep_table
+                const PPTable_Generic_SubTable_Header *sclk_dep_table
                 )
 {
         uint32_t table_size, i;
         phm_ppt_v1_clock_voltage_dependency_table *sclk_table;
 
-        PP_ASSERT_WITH_CODE((0 != sclk_dep_table->ucNumEntries),
-                "Invalid PowerPlay Table!", return -1);
+        if (sclk_dep_table->ucRevId < 1) {
+                const ATOM_Tonga_SCLK_Dependency_Table *tonga_table =
+                            (ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table;
 
-        table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record)
-                * sclk_dep_table->ucNumEntries;
+                PP_ASSERT_WITH_CODE((0 != tonga_table->ucNumEntries),
+                        "Invalid PowerPlay Table!", return -1);
 
-        sclk_table = (phm_ppt_v1_clock_voltage_dependency_table *)
-                kzalloc(table_size, GFP_KERNEL);
+                table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record)
+                        * tonga_table->ucNumEntries;
 
-        if (NULL == sclk_table)
-                return -ENOMEM;
+                sclk_table = (phm_ppt_v1_clock_voltage_dependency_table *)
+                        kzalloc(table_size, GFP_KERNEL);
 
-        memset(sclk_table, 0x00, table_size);
-
-        sclk_table->count = (uint32_t)sclk_dep_table->ucNumEntries;
-
-        for (i = 0; i < sclk_dep_table->ucNumEntries; i++) {
-                sclk_table->entries[i].vddInd =
-                        sclk_dep_table->entries[i].ucVddInd;
-                sclk_table->entries[i].vdd_offset =
-                        sclk_dep_table->entries[i].usVddcOffset;
-                sclk_table->entries[i].clk =
-                        sclk_dep_table->entries[i].ulSclk;
-                sclk_table->entries[i].cks_enable =
-                        (((sclk_dep_table->entries[i].ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0;
-                sclk_table->entries[i].cks_voffset =
-                        (sclk_dep_table->entries[i].ucCKSVOffsetandDisable & 0x7F);
-        }
+                if (NULL == sclk_table)
+                        return -ENOMEM;
+
+                memset(sclk_table, 0x00, table_size);
+
+                sclk_table->count = (uint32_t)tonga_table->ucNumEntries;
+
+                for (i = 0; i < tonga_table->ucNumEntries; i++) {
+                        sclk_table->entries[i].vddInd =
+                                tonga_table->entries[i].ucVddInd;
+                        sclk_table->entries[i].vdd_offset =
+                                tonga_table->entries[i].usVddcOffset;
+                        sclk_table->entries[i].clk =
+                                tonga_table->entries[i].ulSclk;
+                        sclk_table->entries[i].cks_enable =
+                                (((tonga_table->entries[i].ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0;
+                        sclk_table->entries[i].cks_voffset =
+                                (tonga_table->entries[i].ucCKSVOffsetandDisable & 0x7F);
+                }
+        } else {
+                const ATOM_Polaris_SCLK_Dependency_Table *polaris_table =
+                            (ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table;
+
+                PP_ASSERT_WITH_CODE((0 != polaris_table->ucNumEntries),
+                        "Invalid PowerPlay Table!", return -1);
+
+                table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record)
+                        * polaris_table->ucNumEntries;
+
+                sclk_table = (phm_ppt_v1_clock_voltage_dependency_table *)
+                        kzalloc(table_size, GFP_KERNEL);
 
+                if (NULL == sclk_table)
+                        return -ENOMEM;
+
+                memset(sclk_table, 0x00, table_size);
+
+                sclk_table->count = (uint32_t)polaris_table->ucNumEntries;
+
+                for (i = 0; i < polaris_table->ucNumEntries; i++) {
+                        sclk_table->entries[i].vddInd =
+                                polaris_table->entries[i].ucVddInd;
+                        sclk_table->entries[i].vdd_offset =
+                                polaris_table->entries[i].usVddcOffset;
+                        sclk_table->entries[i].clk =
+                                polaris_table->entries[i].ulSclk;
+                        sclk_table->entries[i].cks_enable =
+                                (((polaris_table->entries[i].ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0;
+                        sclk_table->entries[i].cks_voffset =
+                                (polaris_table->entries[i].ucCKSVOffsetandDisable & 0x7F);
+                        sclk_table->entries[i].sclk_offset = polaris_table->entries[i].ulSclkOffset;
+                }
+        }
         *pp_tonga_sclk_dep_table = sclk_table;
 
         return 0;
@@ -708,8 +745,8 @@ static int init_clock_voltage_dependency(
         const ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
                 (const ATOM_Tonga_MCLK_Dependency_Table *)(((unsigned long) powerplay_table) +
                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
-        const ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
-                (const ATOM_Tonga_SCLK_Dependency_Table *)(((unsigned long) powerplay_table) +
+        const PPTable_Generic_SubTable_Header *sclk_dep_table =
+                (const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) +
                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
         const ATOM_Tonga_Hard_Limit_Table *pHardLimits =
                 (const ATOM_Tonga_Hard_Limit_Table *)(((unsigned long) powerplay_table) +
@@ -1040,48 +1077,44 @@ int tonga_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
         struct phm_ppt_v1_information *pp_table_information =
                 (struct phm_ppt_v1_information *)(hwmgr->pptable);
 
-        if (NULL != hwmgr->soft_pp_table) {
-                kfree(hwmgr->soft_pp_table);
+        if (NULL != hwmgr->soft_pp_table)
                 hwmgr->soft_pp_table = NULL;
-        }
 
-        if (NULL != pp_table_information->vdd_dep_on_sclk)
-                pp_table_information->vdd_dep_on_sclk = NULL;
+        kfree(pp_table_information->vdd_dep_on_sclk);
+        pp_table_information->vdd_dep_on_sclk = NULL;
 
-        if (NULL != pp_table_information->vdd_dep_on_mclk)
-                pp_table_information->vdd_dep_on_mclk = NULL;
+        kfree(pp_table_information->vdd_dep_on_mclk);
+        pp_table_information->vdd_dep_on_mclk = NULL;
 
-        if (NULL != pp_table_information->valid_mclk_values)
-                pp_table_information->valid_mclk_values = NULL;
+        kfree(pp_table_information->valid_mclk_values);
+        pp_table_information->valid_mclk_values = NULL;
 
-        if (NULL != pp_table_information->valid_sclk_values)
-                pp_table_information->valid_sclk_values = NULL;
+        kfree(pp_table_information->valid_sclk_values);
+        pp_table_information->valid_sclk_values = NULL;
 
-        if (NULL != pp_table_information->vddc_lookup_table)
-                pp_table_information->vddc_lookup_table = NULL;
+        kfree(pp_table_information->vddc_lookup_table);
+        pp_table_information->vddc_lookup_table = NULL;
 
-        if (NULL != pp_table_information->vddgfx_lookup_table)
-                pp_table_information->vddgfx_lookup_table = NULL;
+        kfree(pp_table_information->vddgfx_lookup_table);
+        pp_table_information->vddgfx_lookup_table = NULL;
 
-        if (NULL != pp_table_information->mm_dep_table)
-                pp_table_information->mm_dep_table = NULL;
+        kfree(pp_table_information->mm_dep_table);
+        pp_table_information->mm_dep_table = NULL;
 
-        if (NULL != pp_table_information->cac_dtp_table)
-                pp_table_information->cac_dtp_table = NULL;
+        kfree(pp_table_information->cac_dtp_table);
+        pp_table_information->cac_dtp_table = NULL;
 
-        if (NULL != hwmgr->dyn_state.cac_dtp_table)
-                hwmgr->dyn_state.cac_dtp_table = NULL;
+        kfree(hwmgr->dyn_state.cac_dtp_table);
+        hwmgr->dyn_state.cac_dtp_table = NULL;
 
-        if (NULL != pp_table_information->ppm_parameter_table)
-                pp_table_information->ppm_parameter_table = NULL;
+        kfree(pp_table_information->ppm_parameter_table);
+        pp_table_information->ppm_parameter_table = NULL;
 
-        if (NULL != pp_table_information->pcie_table)
-                pp_table_information->pcie_table = NULL;
+        kfree(pp_table_information->pcie_table);
+        pp_table_information->pcie_table = NULL;
 
-        if (NULL != hwmgr->pptable) {
-                kfree(hwmgr->pptable);
-                hwmgr->pptable = NULL;
-        }
+        kfree(hwmgr->pptable);
+        hwmgr->pptable = NULL;
 
         return result;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h
index 0c6a413eaa5b..d41d37ab5b7c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h
@@ -27,6 +27,7 @@
 
 #pragma pack(push, 1)
 
+#define PPSMC_MSG_SetGBDroopSettings          ((uint16_t) 0x305)
 
 #define PPSMC_SWSTATE_FLAG_DC                           0x01
 #define PPSMC_SWSTATE_FLAG_UVD                          0x02
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h b/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h
index 3bd5e69b9045..3df5de2cdab0 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h
@@ -26,3 +26,4 @@ extern bool acpi_atcs_functions_supported(void *device,
 extern int acpi_pcie_perf_request(void *device,
                                                 uint8_t perf_req,
                                                 bool advertise);
+extern bool acpi_atcs_notify_pcie_device_ready(void *device);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu74.h b/drivers/gpu/drm/amd/powerplay/inc/smu74.h
index 1a12d85b8e97..fd10a9fa843d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu74.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu74.h
@@ -34,6 +34,30 @@
 #define SMU__NUM_LCLK_DPM_LEVELS 8
 #define SMU__NUM_PCIE_DPM_LEVELS 8
 
+#define EXP_M1  35
+#define EXP_M2  92821
+#define EXP_B   66629747
+
+#define EXP_M1_1  365
+#define EXP_M2_1  658700
+#define EXP_B_1   305506134
+
+#define EXP_M1_2  189
+#define EXP_M2_2  379692
+#define EXP_B_2   194609469
+
+#define EXP_M1_3  99
+#define EXP_M2_3  217915
+#define EXP_B_3   122255994
+
+#define EXP_M1_4  51
+#define EXP_M2_4  122643
+#define EXP_B_4   74893384
+
+#define EXP_M1_5  423
+#define EXP_M2_5  1103326
+#define EXP_B_5   728122621
+
 enum SID_OPTION {
         SID_OPTION_HI,
         SID_OPTION_LO,
@@ -548,20 +572,20 @@ struct SMU74_Firmware_Header {
         uint32_t CacConfigTable;
         uint32_t CacStatusTable;
 
-
         uint32_t mcRegisterTable;
 
-
         uint32_t mcArbDramTimingTable;
 
-
-
-
         uint32_t PmFuseTable;
         uint32_t Globals;
         uint32_t ClockStretcherTable;
         uint32_t VftTable;
-        uint32_t Reserved[21];
+        uint32_t Reserved1;
+        uint32_t AvfsTable;
+        uint32_t AvfsCksOffGbvTable;
+        uint32_t AvfsMeanNSigma;
+        uint32_t AvfsSclkOffsetTable;
+        uint32_t Reserved[16];
         uint32_t Signature;
 };
 
@@ -701,8 +725,6 @@ VR Config info is contained in dpmTable.VRConfig */
 struct SMU_ClockStretcherDataTableEntry {
         uint8_t minVID;
         uint8_t maxVID;
-
-
         uint16_t setting;
 };
 typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
@@ -769,6 +791,43 @@ struct VFT_TABLE_t {
 typedef struct VFT_TABLE_t VFT_TABLE_t;
 
 
+/* Total margin, root mean square of Fmax + DC + Platform */
+struct AVFS_Margin_t {
+        VFT_CELL_t Cell[NUM_VFT_COLUMNS];
+};
+typedef struct AVFS_Margin_t AVFS_Margin_t;
+
+#define BTCGB_VDROOP_TABLE_MAX_ENTRIES 2
+#define AVFSGB_VDROOP_TABLE_MAX_ENTRIES 2
+
+struct GB_VDROOP_TABLE_t {
+        int32_t a0;
+        int32_t a1;
+        int32_t a2;
+        uint32_t spare;
+};
+typedef struct GB_VDROOP_TABLE_t GB_VDROOP_TABLE_t;
+
+struct AVFS_CksOff_Gbv_t {
+        VFT_CELL_t Cell[NUM_VFT_COLUMNS];
+};
+typedef struct AVFS_CksOff_Gbv_t AVFS_CksOff_Gbv_t;
+
+struct AVFS_meanNsigma_t {
+        uint32_t Aconstant[3];
+        uint16_t DC_tol_sigma;
+        uint16_t Platform_mean;
+        uint16_t Platform_sigma;
+        uint16_t PSM_Age_CompFactor;
+        uint8_t  Static_Voltage_Offset[NUM_VFT_COLUMNS];
+};
+typedef struct AVFS_meanNsigma_t AVFS_meanNsigma_t;
+
+struct AVFS_Sclk_Offset_t {
+        uint16_t Sclk_Offset[8];
+};
+typedef struct AVFS_Sclk_Offset_t AVFS_Sclk_Offset_t;
+
 #endif
 
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
index 0dfe82336dc7..b85ff5400e57 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
@@ -223,6 +223,16 @@ struct SMU74_Discrete_StateInfo {
 
 typedef struct SMU74_Discrete_StateInfo SMU74_Discrete_StateInfo;
 
+struct SMU_QuadraticCoeffs {
+        int32_t m1;
+        uint32_t b;
+
+        int16_t m2;
+        uint8_t m1_shift;
+        uint8_t m2_shift;
+};
+typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
+
 struct SMU74_Discrete_DpmTable {
 
         SMU74_PIDController                  GraphicsPIDController;
@@ -258,7 +268,14 @@ struct SMU74_Discrete_DpmTable {
         uint8_t                             ThermOutPolarity;
         uint8_t                             ThermOutMode;
         uint8_t                             BootPhases;
-        uint32_t                            Reserved[4];
+
+        uint8_t                             VRHotLevel;
+        uint8_t                             Reserved1[3];
+        uint16_t                            FanStartTemperature;
+        uint16_t                            FanStopTemperature;
+        uint16_t                            MaxVoltage;
+        uint16_t                            Reserved2;
+        uint32_t                            Reserved[1];
 
         SMU74_Discrete_GraphicsLevel        GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS];
         SMU74_Discrete_MemoryLevel          MemoryACPILevel;
@@ -347,6 +364,8 @@ struct SMU74_Discrete_DpmTable {
 
         uint32_t                            CurrSclkPllRange;
         sclkFcwRange_t                      SclkFcwRangeTable[NUM_SCLK_RANGE];
+        GB_VDROOP_TABLE_t                   BTCGB_VDROOP_TABLE[BTCGB_VDROOP_TABLE_MAX_ENTRIES];
+        SMU_QuadraticCoeffs                 AVFSGB_VDROOP_TABLE[AVFSGB_VDROOP_TABLE_MAX_ENTRIES];
 };
 
 typedef struct SMU74_Discrete_DpmTable SMU74_Discrete_DpmTable;
@@ -550,16 +569,6 @@ struct SMU7_AcpiScoreboard {
 
 typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
 
-struct SMU_QuadraticCoeffs {
-        int32_t m1;
-        uint32_t b;
-
-        int16_t m2;
-        uint8_t m1_shift;
-        uint8_t m2_shift;
-};
-typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
-
 struct SMU74_Discrete_PmFuses {
         uint8_t BapmVddCVidHiSidd[8];
         uint8_t BapmVddCVidLoSidd[8];
@@ -821,6 +830,17 @@ typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
 #define DB_PCC_SHIFT 26 
 #define DB_EDC_SHIFT 27
 
+#define BTCGB0_Vdroop_Enable_MASK  0x1
+#define BTCGB1_Vdroop_Enable_MASK  0x2
+#define AVFSGB0_Vdroop_Enable_MASK 0x4
+#define AVFSGB1_Vdroop_Enable_MASK 0x8
+
+#define BTCGB0_Vdroop_Enable_SHIFT  0
+#define BTCGB1_Vdroop_Enable_SHIFT  1
+#define AVFSGB0_Vdroop_Enable_SHIFT 2
+#define AVFSGB1_Vdroop_Enable_SHIFT 3
+
+
 #pragma pack(pop)
 
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 673a75c74e18..8e52a2e82db5 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -1006,10 +1006,16 @@ static int fiji_smu_init(struct pp_smumgr *smumgr)
 
 static int fiji_smu_fini(struct pp_smumgr *smumgr)
 {
+        struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
+
+        smu_free_memory(smumgr->device, (void *)priv->header_buffer.handle);
+
         if (smumgr->backend) {
                 kfree(smumgr->backend);
                 smumgr->backend = NULL;
         }
+
+        cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU);
         return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index de618ead9db8..5dba7c509710 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -52,19 +52,18 @@
 static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
         /*  Min      pcie   DeepSleep Activity  CgSpll      CgSpll    CcPwr  CcPwr  Sclk         Enabled      Enabled                       Voltage    Power */
         /* Voltage, DpmLevel, DivId,  Level,  FuncCntl3,  FuncCntl4,  DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
-        { 0x3c0fd047, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x30750000, 0, 0, 0, 0, 0, 0, 0 } },
-        { 0xa00fd047, 0x01, 0x04, 0x1e00, 0x00800510, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x409c0000, 0, 0, 0, 0, 0, 0, 0 } },
-        { 0x0410d047, 0x01, 0x00, 0x1e00, 0x00600410, 0x87020000, 0, 0, 0x0e, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x50c30000, 0, 0, 0, 0, 0, 0, 0 } },
-        { 0x6810d047, 0x01, 0x00, 0x1e00, 0x00800410, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x60ea0000, 0, 0, 0, 0, 0, 0, 0 } },
-        { 0xcc10d047, 0x01, 0x00, 0x1e00, 0x00e00410, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0xe8fd0000, 0, 0, 0, 0, 0, 0, 0 } },
-        { 0x3011d047, 0x01, 0x00, 0x1e00, 0x00400510, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x70110100, 0, 0, 0, 0, 0, 0, 0 } },
-        { 0x9411d047, 0x01, 0x00, 0x1e00, 0x00a00510, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0xf8240100, 0, 0, 0, 0, 0, 0, 0 } },
-        { 0xf811d047, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x80380100, 0, 0, 0, 0, 0, 0, 0 } }
+        { 0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000, 0x3000, 0, 0x2600, 0, 0, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
+        { 0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000, 0x2000, 0, 0x1e00, 1, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
+        { 0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000, 0x2800, 0, 0x2000, 1, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } },
+        { 0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000, 0x3000, 0, 0x2600, 1, 1, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
+        { 0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100, 0x3800, 0, 0x2c00, 1, 1, 0x0004, 0x1203, 0xffff, 0x3600, 0xc9e2, 0x2e00 } },
+        { 0x3c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x80380100, 0x2000, 0, 0x1e00, 2, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
+        { 0x6c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x905f0100, 0x2400, 0, 0x1e00, 2, 1, 0x0004, 0x8901, 0xffff, 0x2300, 0x314c, 0x1d00 } },
+        { 0xa00fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0xa0860100, 0x2800, 0, 0x2000, 2, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } }
 };
 
 static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 =
-        {0x50140000, 0x50140000, 0x00320000, 0x00, 0x00,
-         0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0000, 0x00, 0x00};
+        {0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
 
 /**
 * Set the address for reading/writing the SMC SRAM space.
@@ -219,6 +218,18 @@ bool polaris10_is_smc_ram_running(struct pp_smumgr *smumgr)
         && (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
 }
 
+static bool polaris10_is_hw_avfs_present(struct pp_smumgr *smumgr)
+{
+        uint32_t efuse;
+
+        efuse = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
+        efuse &= 0x00000001;
+        if (efuse)
+                return true;
+
+        return false;
+}
+
 /**
 * Send a message to the SMC, and wait for its response.
 *
@@ -228,21 +239,27 @@ bool polaris10_is_smc_ram_running(struct pp_smumgr *smumgr)
 */
 int polaris10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
 {
+        int ret;
+
         if (!polaris10_is_smc_ram_running(smumgr))
                 return -1;
 
+
         SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
 
-        if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
-                printk("Failed to send Previous Message.\n");
+        ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
 
+        if (ret != 1)
+                printk("\n failed to send pre message %x ret is %d \n",  msg, ret);
 
         cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
 
         SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
 
-        if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
-                printk("Failed to send Message.\n");
+        ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
+
+        if (ret != 1)
+                printk("\n failed to send message %x ret is %d \n",  msg, ret);
 
         return 0;
 }
@@ -469,6 +486,7 @@ int polaris10_smu_fini(struct pp_smumgr *smumgr)
                 kfree(smumgr->backend);
                 smumgr->backend = NULL;
         }
+        cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU);
         return 0;
 }
 
@@ -952,6 +970,11 @@ static int polaris10_smu_init(struct pp_smumgr *smumgr)
                 (cgs_handle_t)smu_data->smu_buffer.handle);
                 return -1;);
 
+        if (polaris10_is_hw_avfs_present(smumgr))
+                smu_data->avfs.avfs_btc_status = AVFS_BTC_BOOT;
+        else
+                smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED;
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
index c483baf6b4fb..0728c1e3d97a 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
@@ -81,6 +81,7 @@ int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
 
 int smum_fini(struct pp_smumgr *smumgr)
 {
+        kfree(smumgr->device);
         kfree(smumgr);
         return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index 32820b680d88..b22722eabafc 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -328,10 +328,17 @@ int tonga_write_smc_sram_dword(struct pp_smumgr *smumgr,
 
 static int tonga_smu_fini(struct pp_smumgr *smumgr)
 {
+        struct tonga_smumgr *priv = (struct tonga_smumgr *)(smumgr->backend);
+
+        smu_free_memory(smumgr->device, (void *)priv->smu_buffer.handle);
+        smu_free_memory(smumgr->device, (void *)priv->header_buffer.handle);
+
         if (smumgr->backend != NULL) {
                 kfree(smumgr->backend);
                 smumgr->backend = NULL;
         }
+
+        cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU);
         return 0;
 }
 
diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c
index fef1b04c2aab..0813c2f06931 100644
--- a/drivers/gpu/drm/arm/hdlcd_crtc.c
+++ b/drivers/gpu/drm/arm/hdlcd_crtc.c
@@ -33,8 +33,17 @@
  *
  */
 
+static void hdlcd_crtc_cleanup(struct drm_crtc *crtc)
+{
+        struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
+
+        /* stop the controller on cleanup */
+        hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
+        drm_crtc_cleanup(crtc);
+}
+
 static const struct drm_crtc_funcs hdlcd_crtc_funcs = {
-        .destroy = drm_crtc_cleanup,
+        .destroy = hdlcd_crtc_cleanup,
         .set_config = drm_atomic_helper_set_config,
         .page_flip = drm_atomic_helper_page_flip,
         .reset = drm_atomic_helper_crtc_reset,
@@ -97,7 +106,7 @@ static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc)
         struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
         struct drm_display_mode *m = &crtc->state->adjusted_mode;
         struct videomode vm;
-        unsigned int polarities, line_length, err;
+        unsigned int polarities, err;
 
         vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
         vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
@@ -113,23 +122,18 @@ static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc)
         if (m->flags & DRM_MODE_FLAG_PVSYNC)
                 polarities |= HDLCD_POLARITY_VSYNC;
 
-        line_length = crtc->primary->state->fb->pitches[0];
-
         /* Allow max number of outstanding requests and largest burst size */
         hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS,
                     HDLCD_BUS_MAX_OUTSTAND | HDLCD_BUS_BURST_16);
 
-        hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, line_length);
-        hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, line_length);
-        hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, m->crtc_vdisplay - 1);
         hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1);
         hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1);
         hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1);
         hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1);
+        hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1);
         hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1);
         hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1);
         hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1);
-        hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1);
         hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities);
 
         err = hdlcd_set_pxl_fmt(crtc);
@@ -144,20 +148,19 @@ static void hdlcd_crtc_enable(struct drm_crtc *crtc)
         struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
 
         clk_prepare_enable(hdlcd->clk);
+        hdlcd_crtc_mode_set_nofb(crtc);
         hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);
-        drm_crtc_vblank_on(crtc);
 }
 
 static void hdlcd_crtc_disable(struct drm_crtc *crtc)
 {
         struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
 
-        if (!crtc->primary->fb)
+        if (!crtc->state->active)
                 return;
 
-        clk_disable_unprepare(hdlcd->clk);
         hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
-        drm_crtc_vblank_off(crtc);
+        clk_disable_unprepare(hdlcd->clk);
 }
 
 static int hdlcd_crtc_atomic_check(struct drm_crtc *crtc,
@@ -179,20 +182,17 @@ static int hdlcd_crtc_atomic_check(struct drm_crtc *crtc,
 static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc,
                                     struct drm_crtc_state *state)
 {
-        struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
-        unsigned long flags;
-
-        if (crtc->state->event) {
-                struct drm_pending_vblank_event *event = crtc->state->event;
+        struct drm_pending_vblank_event *event = crtc->state->event;
 
+        if (event) {
                 crtc->state->event = NULL;
-                event->pipe = drm_crtc_index(crtc);
-
-                WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 
-                spin_lock_irqsave(&crtc->dev->event_lock, flags);
-                list_add_tail(&event->base.link, &hdlcd->event_list);
-                spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
+                spin_lock_irq(&crtc->dev->event_lock);
+                if (drm_crtc_vblank_get(crtc) == 0)
+                        drm_crtc_arm_vblank_event(crtc, event);
+                else
+                        drm_crtc_send_vblank_event(crtc, event);
+                spin_unlock_irq(&crtc->dev->event_lock);
         }
 }
 
@@ -225,6 +225,15 @@ static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = {
 static int hdlcd_plane_atomic_check(struct drm_plane *plane,
                                     struct drm_plane_state *state)
 {
+        u32 src_w, src_h;
+
+        src_w = state->src_w >> 16;
+        src_h = state->src_h >> 16;
+
+        /* we can't do any scaling of the plane source */
+        if ((src_w != state->crtc_w) || (src_h != state->crtc_h))
+                return -EINVAL;
+
         return 0;
 }
 
@@ -233,20 +242,31 @@ static void hdlcd_plane_atomic_update(struct drm_plane *plane,
 {
         struct hdlcd_drm_private *hdlcd;
         struct drm_gem_cma_object *gem;
+        unsigned int depth, bpp;
+        u32 src_w, src_h, dest_w, dest_h;
         dma_addr_t scanout_start;
 
-        if (!plane->state->crtc || !plane->state->fb)
+        if (!plane->state->fb)
                 return;
 
-        hdlcd = crtc_to_hdlcd_priv(plane->state->crtc);
+        drm_fb_get_bpp_depth(plane->state->fb->pixel_format, &depth, &bpp);
+        src_w = plane->state->src_w >> 16;
+        src_h = plane->state->src_h >> 16;
+        dest_w = plane->state->crtc_w;
+        dest_h = plane->state->crtc_h;
         gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0);
-        scanout_start = gem->paddr;
+        scanout_start = gem->paddr + plane->state->fb->offsets[0] +
+                plane->state->crtc_y * plane->state->fb->pitches[0] +
+                plane->state->crtc_x * bpp / 8;
+
+        hdlcd = plane->dev->dev_private;
+        hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, plane->state->fb->pitches[0]);
+        hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, plane->state->fb->pitches[0]);
+        hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1);
         hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start);
 }
 
 static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = {
-        .prepare_fb = NULL,
-        .cleanup_fb = NULL,
         .atomic_check = hdlcd_plane_atomic_check,
         .atomic_update = hdlcd_plane_atomic_update,
 };
@@ -294,16 +314,6 @@ static struct drm_plane *hdlcd_plane_init(struct drm_device *drm)
         return plane;
 }
 
-void hdlcd_crtc_suspend(struct drm_crtc *crtc)
-{
-        hdlcd_crtc_disable(crtc);
-}
-
-void hdlcd_crtc_resume(struct drm_crtc *crtc)
-{
-        hdlcd_crtc_enable(crtc);
-}
-
 int hdlcd_setup_crtc(struct drm_device *drm)
 {
         struct hdlcd_drm_private *hdlcd = drm->dev_private;
diff --git a/drivers/gpu/drm/arm/hdlcd_drv.c b/drivers/gpu/drm/arm/hdlcd_drv.c
index b987c63ba8d6..a6ca36f0096f 100644
--- a/drivers/gpu/drm/arm/hdlcd_drv.c
+++ b/drivers/gpu/drm/arm/hdlcd_drv.c
@@ -49,8 +49,6 @@ static int hdlcd_load(struct drm_device *drm, unsigned long flags)
         atomic_set(&hdlcd->dma_end_count, 0);
 #endif
 
-        INIT_LIST_HEAD(&hdlcd->event_list);
-
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
         if (IS_ERR(hdlcd->mmio)) {
@@ -84,11 +82,7 @@ static int hdlcd_load(struct drm_device *drm, unsigned long flags)
                 goto setup_fail;
         }
 
-        pm_runtime_enable(drm->dev);
-
-        pm_runtime_get_sync(drm->dev);
         ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
-        pm_runtime_put_sync(drm->dev);
         if (ret < 0) {
                 DRM_ERROR("failed to install IRQ handler\n");
                 goto irq_fail;
@@ -164,24 +158,9 @@ static irqreturn_t hdlcd_irq(int irq, void *arg)
                 atomic_inc(&hdlcd->vsync_count);
 
 #endif
-        if (irq_status & HDLCD_INTERRUPT_VSYNC) {
-                bool events_sent = false;
-                unsigned long flags;
-                struct drm_pending_vblank_event *e, *t;
-
+        if (irq_status & HDLCD_INTERRUPT_VSYNC)
                 drm_crtc_handle_vblank(&hdlcd->crtc);
 
-                spin_lock_irqsave(&drm->event_lock, flags);
-                list_for_each_entry_safe(e, t, &hdlcd->event_list, base.link) {
-                        list_del(&e->base.link);
-                        drm_crtc_send_vblank_event(&hdlcd->crtc, e);
-                        events_sent = true;
-                }
-                if (events_sent)
-                        drm_crtc_vblank_put(&hdlcd->crtc);
-                spin_unlock_irqrestore(&drm->event_lock, flags);
-        }
-
         /* acknowledge interrupt(s) */
         hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
 
@@ -275,6 +254,7 @@ static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
 static struct drm_info_list hdlcd_debugfs_list[] = {
         { "interrupt_count", hdlcd_show_underrun_count, 0 },
         { "clocks", hdlcd_show_pxlclock, 0 },
+        { "fb", drm_fb_cma_debugfs_show, 0 },
 };
 
 static int hdlcd_debugfs_init(struct drm_minor *minor)
@@ -357,6 +337,8 @@ static int hdlcd_drm_bind(struct device *dev)
                 return -ENOMEM;
 
         drm->dev_private = hdlcd;
+        dev_set_drvdata(dev, drm);
+
         hdlcd_setup_mode_config(drm);
         ret = hdlcd_load(drm, 0);
         if (ret)
@@ -366,14 +348,18 @@ static int hdlcd_drm_bind(struct device *dev)
         if (ret)
                 goto err_unload;
 
-        dev_set_drvdata(dev, drm);
-
         ret = component_bind_all(dev, drm);
         if (ret) {
                 DRM_ERROR("Failed to bind all components\n");
                 goto err_unregister;
         }
 
+        ret = pm_runtime_set_active(dev);
+        if (ret)
+                goto err_pm_active;
+
+        pm_runtime_enable(dev);
+
         ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
         if (ret < 0) {
                 DRM_ERROR("failed to initialise vblank\n");
@@ -399,16 +385,16 @@ err_fbdev:
         drm_mode_config_cleanup(drm);
         drm_vblank_cleanup(drm);
 err_vblank:
+        pm_runtime_disable(drm->dev);
+err_pm_active:
         component_unbind_all(dev, drm);
 err_unregister:
         drm_dev_unregister(drm);
 err_unload:
-        pm_runtime_get_sync(drm->dev);
         drm_irq_uninstall(drm);
-        pm_runtime_put_sync(drm->dev);
-        pm_runtime_disable(drm->dev);
         of_reserved_mem_device_release(drm->dev);
 err_free:
+        dev_set_drvdata(dev, NULL);
         drm_dev_unref(drm);
 
         return ret;
@@ -495,30 +481,34 @@ MODULE_DEVICE_TABLE(of, hdlcd_of_match);
 static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
 {
         struct drm_device *drm = dev_get_drvdata(dev);
-        struct drm_crtc *crtc;
+        struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
 
-        if (pm_runtime_suspended(dev))
+        if (!hdlcd)
                 return 0;
 
-        drm_modeset_lock_all(drm);
-        list_for_each_entry(crtc, &drm->mode_config.crtc_list, head)
-                hdlcd_crtc_suspend(crtc);
-        drm_modeset_unlock_all(drm);
+        drm_kms_helper_poll_disable(drm);
+
+        hdlcd->state = drm_atomic_helper_suspend(drm);
+        if (IS_ERR(hdlcd->state)) {
+                drm_kms_helper_poll_enable(drm);
+                return PTR_ERR(hdlcd->state);
+        }
+
         return 0;
 }
 
 static int __maybe_unused hdlcd_pm_resume(struct device *dev)
 {
         struct drm_device *drm = dev_get_drvdata(dev);
-        struct drm_crtc *crtc;
+        struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
 
-        if (!pm_runtime_suspended(dev))
+        if (!hdlcd)
                 return 0;
 
-        drm_modeset_lock_all(drm);
-        list_for_each_entry(crtc, &drm->mode_config.crtc_list, head)
-                hdlcd_crtc_resume(crtc);
-        drm_modeset_unlock_all(drm);
+        drm_atomic_helper_resume(drm, hdlcd->state);
+        drm_kms_helper_poll_enable(drm);
+        pm_runtime_set_active(dev);
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/arm/hdlcd_drv.h b/drivers/gpu/drm/arm/hdlcd_drv.h
index aa234784f053..e3950a071152 100644
--- a/drivers/gpu/drm/arm/hdlcd_drv.h
+++ b/drivers/gpu/drm/arm/hdlcd_drv.h
@@ -9,10 +9,9 @@ struct hdlcd_drm_private {
         void __iomem                    *mmio;
         struct clk                      *clk;
         struct drm_fbdev_cma            *fbdev;
-        struct drm_framebuffer          *fb;
-        struct list_head                event_list;
         struct drm_crtc                 crtc;
         struct drm_plane                *plane;
+        struct drm_atomic_state         *state;
 #ifdef CONFIG_DEBUG_FS
         atomic_t buffer_underrun_count;
         atomic_t bus_error_count;
@@ -36,7 +35,5 @@ static inline u32 hdlcd_read(struct hdlcd_drm_private *hdlcd, unsigned int reg)
 
 int hdlcd_setup_crtc(struct drm_device *dev);
 void hdlcd_set_scanout(struct hdlcd_drm_private *hdlcd);
-void hdlcd_crtc_suspend(struct drm_crtc *crtc);
-void hdlcd_crtc_resume(struct drm_crtc *crtc);
 
 #endif /* __HDLCD_DRV_H__ */
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
index cf23a755f777..bd12231ab0cd 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
@@ -391,12 +391,11 @@ void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc)
 {
         struct atmel_hlcdc_crtc_state *state;
 
-        if (crtc->state && crtc->state->mode_blob)
-                drm_property_unreference_blob(crtc->state->mode_blob);
-
         if (crtc->state) {
+                __drm_atomic_helper_crtc_destroy_state(crtc->state);
                 state = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state);
                 kfree(state);
+                crtc->state = NULL;
         }
 
         state = kzalloc(sizeof(*state), GFP_KERNEL);
@@ -415,8 +414,9 @@ atmel_hlcdc_crtc_duplicate_state(struct drm_crtc *crtc)
                 return NULL;
 
         state = kmalloc(sizeof(*state), GFP_KERNEL);
-        if (state)
-                __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
+        if (!state)
+                return NULL;
+        __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 
         cur = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state);
         state->output_mode = cur->output_mode;
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c
index 39802c0539b6..3d34fc4ca826 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c
@@ -266,9 +266,10 @@ int atmel_hlcdc_create_outputs(struct drm_device *dev)
                 if (!ret)
                         ret = atmel_hlcdc_check_endpoint(dev, &ep);
 
-                of_node_put(ep_np);
-                if (ret)
+                if (ret) {
+                        of_node_put(ep_np);
                         return ret;
+                }
         }
 
         for_each_endpoint_of_node(dev->dev->of_node, ep_np) {
@@ -276,9 +277,10 @@ int atmel_hlcdc_create_outputs(struct drm_device *dev)
                 if (!ret)
                         ret = atmel_hlcdc_attach_endpoint(dev, &ep);
 
-                of_node_put(ep_np);
-                if (ret)
+                if (ret) {
+                        of_node_put(ep_np);
                         return ret;
+                }
         }
 
         return 0;
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
index aef3ca8a81fa..016c191221f3 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
@@ -339,6 +339,8 @@ atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane,
 
                 atmel_hlcdc_layer_update_cfg(&plane->layer, 13, 0xffffffff,
                                              factor_reg);
+        } else {
+                atmel_hlcdc_layer_update_cfg(&plane->layer, 13, 0xffffffff, 0);
         }
 }
 
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 3ff1ed7b33db..9bb99e274d23 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -351,6 +351,8 @@ int drm_atomic_set_mode_prop_for_crtc(struct drm_crtc_state *state,
         drm_property_unreference_blob(state->mode_blob);
         state->mode_blob = NULL;
 
+        memset(&state->mode, 0, sizeof(state->mode));
+
         if (blob) {
                 if (blob->length != sizeof(struct drm_mode_modeinfo) ||
                     drm_mode_convert_umode(&state->mode,
@@ -363,7 +365,6 @@ int drm_atomic_set_mode_prop_for_crtc(struct drm_crtc_state *state,
                 DRM_DEBUG_ATOMIC("Set [MODE:%s] for CRTC state %p\n",
                                  state->mode.name, state);
         } else {
-                memset(&state->mode, 0, sizeof(state->mode));
                 state->enable = false;
                 DRM_DEBUG_ATOMIC("Set [NOMODE] for CRTC state %p\n",
                                  state);
@@ -1295,14 +1296,39 @@ EXPORT_SYMBOL(drm_atomic_add_affected_planes);
  */
 void drm_atomic_legacy_backoff(struct drm_atomic_state *state)
 {
+        struct drm_device *dev = state->dev;
+        unsigned crtc_mask = 0;
+        struct drm_crtc *crtc;
         int ret;
+        bool global = false;
+
+        drm_for_each_crtc(crtc, dev) {
+                if (crtc->acquire_ctx != state->acquire_ctx)
+                        continue;
+
+                crtc_mask |= drm_crtc_mask(crtc);
+                crtc->acquire_ctx = NULL;
+        }
+
+        if (WARN_ON(dev->mode_config.acquire_ctx == state->acquire_ctx)) {
+                global = true;
+
+                dev->mode_config.acquire_ctx = NULL;
+        }
 
 retry:
         drm_modeset_backoff(state->acquire_ctx);
 
-        ret = drm_modeset_lock_all_ctx(state->dev, state->acquire_ctx);
+        ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
         if (ret)
                 goto retry;
+
+        drm_for_each_crtc(crtc, dev)
+                if (drm_crtc_mask(crtc) & crtc_mask)
+                        crtc->acquire_ctx = state->acquire_ctx;
+
+        if (global)
+                dev->mode_config.acquire_ctx = state->acquire_ctx;
 }
 EXPORT_SYMBOL(drm_atomic_legacy_backoff);
 
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index d2a6d958ca76..0e3cc66aa8b7 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -2821,8 +2821,6 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
                         goto out;
                 }
 
-                drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
-
                 /*
                  * Check whether the primary plane supports the fb pixel format.
                  * Drivers not implementing the universal planes API use a
@@ -4841,7 +4839,8 @@ bool drm_property_change_valid_get(struct drm_property *property,
                 if (value == 0)
                         return true;
 
-                return _object_find(property->dev, value, property->values[0]) != NULL;
+                *ref = _object_find(property->dev, value, property->values[0]);
+                return *ref != NULL;
         }
 
         for (i = 0; i < property->num_values; i++)
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index a6e42433ef0e..26feb2f8453f 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -528,11 +528,11 @@ drm_crtc_helper_disable(struct drm_crtc *crtc)
 int drm_crtc_helper_set_config(struct drm_mode_set *set)
 {
         struct drm_device *dev;
-        struct drm_crtc *new_crtc;
-        struct drm_encoder *save_encoders, *new_encoder, *encoder;
+        struct drm_crtc **save_encoder_crtcs, *new_crtc;
+        struct drm_encoder **save_connector_encoders, *new_encoder, *encoder;
         bool mode_changed = false; /* if true do a full mode set */
         bool fb_changed = false; /* if true and !mode_changed just do a flip */
-        struct drm_connector *save_connectors, *connector;
+        struct drm_connector *connector;
         int count = 0, ro, fail = 0;
         const struct drm_crtc_helper_funcs *crtc_funcs;
         struct drm_mode_set save_set;
@@ -574,15 +574,15 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
          * Allocate space for the backup of all (non-pointer) encoder and
          * connector data.
          */
-        save_encoders = kzalloc(dev->mode_config.num_encoder *
-                                sizeof(struct drm_encoder), GFP_KERNEL);
-        if (!save_encoders)
+        save_encoder_crtcs = kzalloc(dev->mode_config.num_encoder *
+                                sizeof(struct drm_crtc *), GFP_KERNEL);
+        if (!save_encoder_crtcs)
                 return -ENOMEM;
 
-        save_connectors = kzalloc(dev->mode_config.num_connector *
-                                sizeof(struct drm_connector), GFP_KERNEL);
-        if (!save_connectors) {
-                kfree(save_encoders);
+        save_connector_encoders = kzalloc(dev->mode_config.num_connector *
+                                sizeof(struct drm_encoder *), GFP_KERNEL);
+        if (!save_connector_encoders) {
+                kfree(save_encoder_crtcs);
                 return -ENOMEM;
         }
 
@@ -593,12 +593,12 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
          */
         count = 0;
         drm_for_each_encoder(encoder, dev) {
-                save_encoders[count++] = *encoder;
+                save_encoder_crtcs[count++] = encoder->crtc;
         }
 
         count = 0;
         drm_for_each_connector(connector, dev) {
-                save_connectors[count++] = *connector;
+                save_connector_encoders[count++] = connector->encoder;
         }
 
         save_set.crtc = set->crtc;
@@ -631,8 +631,12 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
                 mode_changed = true;
         }
 
-        /* take a reference on all connectors in set */
+        /* take a reference on all unbound connectors in set, reuse the
+         * already taken reference for bound connectors
+         */
         for (ro = 0; ro < set->num_connectors; ro++) {
+                if (set->connectors[ro]->encoder)
+                        continue;
                 drm_connector_reference(set->connectors[ro]);
         }
 
@@ -754,30 +758,28 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
                 }
         }
 
-        /* after fail drop reference on all connectors in save set */
-        count = 0;
-        drm_for_each_connector(connector, dev) {
-                drm_connector_unreference(&save_connectors[count++]);
-        }
-
-        kfree(save_connectors);
-        kfree(save_encoders);
+        kfree(save_connector_encoders);
+        kfree(save_encoder_crtcs);
         return 0;
 
 fail:
         /* Restore all previous data. */
         count = 0;
         drm_for_each_encoder(encoder, dev) {
-                *encoder = save_encoders[count++];
+                encoder->crtc = save_encoder_crtcs[count++];
         }
 
         count = 0;
         drm_for_each_connector(connector, dev) {
-                *connector = save_connectors[count++];
+                connector->encoder = save_connector_encoders[count++];
         }
 
-        /* after fail drop reference on all connectors in set */
+        /* after fail drop reference on all unbound connectors in set, let
+         * bound connectors keep their reference
+         */
         for (ro = 0; ro < set->num_connectors; ro++) {
+                if (set->connectors[ro]->encoder)
+                        continue;
                 drm_connector_unreference(set->connectors[ro]);
         }
 
@@ -787,8 +789,8 @@ fail:
                                       save_set.y, save_set.fb))
                 DRM_ERROR("failed to restore config after modeset failure\n");
 
-        kfree(save_connectors);
-        kfree(save_encoders);
+        kfree(save_connector_encoders);
+        kfree(save_encoder_crtcs);
         return ret;
 }
 EXPORT_SYMBOL(drm_crtc_helper_set_config);
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index a13edf5de2d6..6537908050d7 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -2927,11 +2927,9 @@ static void drm_dp_destroy_connector_work(struct work_struct *work)
                 drm_dp_port_teardown_pdt(port, port->pdt);
 
                 if (!port->input && port->vcpi.vcpi > 0) {
-                        if (mgr->mst_state) {
-                                drm_dp_mst_reset_vcpi_slots(mgr, port);
-                                drm_dp_update_payload_part1(mgr);
-                                drm_dp_mst_put_payload_id(mgr, port->vcpi.vcpi);
-                        }
+                        drm_dp_mst_reset_vcpi_slots(mgr, port);
+                        drm_dp_update_payload_part1(mgr);
+                        drm_dp_mst_put_payload_id(mgr, port->vcpi.vcpi);
                 }
 
                 kref_put(&port->kref, drm_dp_free_mst_port);
diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c b/drivers/gpu/drm/drm_fb_cma_helper.c
index 172cafe11c71..5075fae3c4e2 100644
--- a/drivers/gpu/drm/drm_fb_cma_helper.c
+++ b/drivers/gpu/drm/drm_fb_cma_helper.c
@@ -445,7 +445,7 @@ err_cma_destroy:
 err_fb_info_destroy:
         drm_fb_helper_release_fbi(helper);
 err_gem_free_object:
-        dev->driver->gem_free_object(&obj->base);
+        drm_gem_object_unreference_unlocked(&obj->base);
         return ret;
 }
 EXPORT_SYMBOL(drm_fbdev_cma_create_with_funcs);
diff --git a/drivers/gpu/drm/drm_gem_cma_helper.c b/drivers/gpu/drm/drm_gem_cma_helper.c
index e1ab008b3f08..1d6c335584ec 100644
--- a/drivers/gpu/drm/drm_gem_cma_helper.c
+++ b/drivers/gpu/drm/drm_gem_cma_helper.c
@@ -121,7 +121,7 @@ struct drm_gem_cma_object *drm_gem_cma_create(struct drm_device *drm,
         return cma_obj;
 
 error:
-        drm->driver->gem_free_object(&cma_obj->base);
+        drm_gem_object_unreference_unlocked(&cma_obj->base);
         return ERR_PTR(ret);
 }
 EXPORT_SYMBOL_GPL(drm_gem_cma_create);
@@ -162,18 +162,12 @@ drm_gem_cma_create_with_handle(struct drm_file *file_priv,
          * and handle has the id what user can see.
          */
         ret = drm_gem_handle_create(file_priv, gem_obj, handle);
-        if (ret)
-                goto err_handle_create;
-
         /* drop reference from allocate - handle holds it now. */
         drm_gem_object_unreference_unlocked(gem_obj);
+        if (ret)
+                return ERR_PTR(ret);
 
         return cma_obj;
-
-err_handle_create:
-        drm->driver->gem_free_object(gem_obj);
-
-        return ERR_PTR(ret);
 }
 
 /**
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 7def3d58da18..e5e6f504d8cc 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -1518,6 +1518,8 @@ int drm_mode_convert_umode(struct drm_display_mode *out,
         if (out->status != MODE_OK)
                 goto out;
 
+        drm_mode_set_crtcinfo(out, CRTC_INTERLACE_HALVE_V);
+
         ret = 0;
 
 out:
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_iommu.c b/drivers/gpu/drm/etnaviv/etnaviv_iommu.c
index 522cfd447892..16353ee81651 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_iommu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_iommu.c
@@ -225,6 +225,7 @@ struct iommu_domain *etnaviv_iommu_domain_alloc(struct etnaviv_gpu *gpu)
 
         etnaviv_domain->domain.type = __IOMMU_DOMAIN_PAGING;
         etnaviv_domain->domain.ops = &etnaviv_iommu_ops.ops;
+        etnaviv_domain->domain.pgsize_bitmap = SZ_4K;
         etnaviv_domain->domain.geometry.aperture_start = GPU_MEM_START;
         etnaviv_domain->domain.geometry.aperture_end = GPU_MEM_START + PT_ENTRIES * SZ_4K - 1;
 
diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
index f6223f907c15..7f9901b7777b 100644
--- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
@@ -31,7 +31,6 @@
 #include "exynos_drm_plane.h"
 #include "exynos_drm_drv.h"
 #include "exynos_drm_fb.h"
-#include "exynos_drm_fbdev.h"
 #include "exynos_drm_iommu.h"
 
 /*
diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
index 468498e3fec1..4c1fb3f8b5a6 100644
--- a/drivers/gpu/drm/exynos/exynos_dp.c
+++ b/drivers/gpu/drm/exynos/exynos_dp.c
@@ -34,7 +34,7 @@
 
 struct exynos_dp_device {
         struct drm_encoder         encoder;
-        struct drm_connector       connector;
+        struct drm_connector       *connector;
         struct drm_bridge          *ptn_bridge;
         struct drm_device          *drm_dev;
         struct device              *dev;
@@ -70,7 +70,7 @@ static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data)
 static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data)
 {
         struct exynos_dp_device *dp = to_dp(plat_data);
-        struct drm_connector *connector = &dp->connector;
+        struct drm_connector *connector = dp->connector;
         struct drm_display_mode *mode;
         int num_modes = 0;
 
@@ -103,6 +103,7 @@ static int exynos_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
         int ret;
 
         drm_connector_register(connector);
+        dp->connector = connector;
 
         /* Pre-empt DP connector creation if there's a bridge */
         if (dp->ptn_bridge) {
diff --git a/drivers/gpu/drm/exynos/exynos_drm_core.c b/drivers/gpu/drm/exynos/exynos_drm_core.c
index 011211e4167d..edbd98ff293e 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_core.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_core.c
@@ -15,7 +15,6 @@
 #include <drm/drmP.h>
 #include "exynos_drm_drv.h"
 #include "exynos_drm_crtc.h"
-#include "exynos_drm_fbdev.h"
 
 static LIST_HEAD(exynos_drm_subdrv_list);
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 3efe1aa89416..d47216488985 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -30,7 +30,6 @@
 
 #include "exynos_drm_drv.h"
 #include "exynos_drm_fb.h"
-#include "exynos_drm_fbdev.h"
 #include "exynos_drm_crtc.h"
 #include "exynos_drm_plane.h"
 #include "exynos_drm_iommu.h"
@@ -120,7 +119,6 @@ static struct fimd_driver_data s3c64xx_fimd_driver_data = {
         .timing_base = 0x0,
         .has_clksel = 1,
         .has_limited_fmt = 1,
-        .has_hw_trigger = 1,
 };
 
 static struct fimd_driver_data exynos3_fimd_driver_data = {
@@ -171,14 +169,11 @@ static struct fimd_driver_data exynos5420_fimd_driver_data = {
         .lcdblk_vt_shift = 24,
         .lcdblk_bypass_shift = 15,
         .lcdblk_mic_bypass_shift = 11,
-        .trg_type = I80_HW_TRG,
         .has_shadowcon = 1,
         .has_vidoutcon = 1,
         .has_vtsel = 1,
         .has_mic_bypass = 1,
         .has_dp_clk = 1,
-        .has_hw_trigger = 1,
-        .has_trigger_per_te = 1,
 };
 
 struct fimd_context {
diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
index 493552368295..8564c3da0d22 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
@@ -48,13 +48,13 @@
 
 /* registers for base address */
 #define G2D_SRC_BASE_ADDR               0x0304
-#define G2D_SRC_STRIDE_REG              0x0308
+#define G2D_SRC_STRIDE                  0x0308
 #define G2D_SRC_COLOR_MODE              0x030C
 #define G2D_SRC_LEFT_TOP                0x0310
 #define G2D_SRC_RIGHT_BOTTOM            0x0314
 #define G2D_SRC_PLANE2_BASE_ADDR        0x0318
 #define G2D_DST_BASE_ADDR               0x0404
-#define G2D_DST_STRIDE_REG              0x0408
+#define G2D_DST_STRIDE                  0x0408
 #define G2D_DST_COLOR_MODE              0x040C
 #define G2D_DST_LEFT_TOP                0x0410
 #define G2D_DST_RIGHT_BOTTOM            0x0414
@@ -563,7 +563,7 @@ static enum g2d_reg_type g2d_get_reg_type(int reg_offset)
 
         switch (reg_offset) {
         case G2D_SRC_BASE_ADDR:
-        case G2D_SRC_STRIDE_REG:
+        case G2D_SRC_STRIDE:
         case G2D_SRC_COLOR_MODE:
         case G2D_SRC_LEFT_TOP:
         case G2D_SRC_RIGHT_BOTTOM:
@@ -573,7 +573,7 @@ static enum g2d_reg_type g2d_get_reg_type(int reg_offset)
                 reg_type = REG_TYPE_SRC_PLANE2;
                 break;
         case G2D_DST_BASE_ADDR:
-        case G2D_DST_STRIDE_REG:
+        case G2D_DST_STRIDE:
         case G2D_DST_COLOR_MODE:
         case G2D_DST_LEFT_TOP:
         case G2D_DST_RIGHT_BOTTOM:
@@ -968,8 +968,8 @@ static int g2d_check_reg_offset(struct device *dev,
                         } else
                                 buf_info->types[reg_type] = BUF_TYPE_GEM;
                         break;
-                case G2D_SRC_STRIDE_REG:
-                case G2D_DST_STRIDE_REG:
+                case G2D_SRC_STRIDE:
+                case G2D_DST_STRIDE:
                         if (for_addr)
                                 goto err;
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index 55f1d37c666a..77f12c00abf9 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -242,7 +242,7 @@ exynos_drm_plane_check_size(const struct exynos_drm_plane_config *config,
             state->v_ratio == (1 << 15))
                 height_ok = true;
 
-        if (width_ok & height_ok)
+        if (width_ok && height_ok)
                 return 0;
 
         DRM_DEBUG_KMS("scaling mode is not supported");
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index 0ec1ad961e0d..dc723f7ead7d 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -42,9 +42,10 @@ static const struct regmap_config fsl_dcu_regmap_config = {
         .reg_bits = 32,
         .reg_stride = 4,
         .val_bits = 32,
-        .cache_type = REGCACHE_RBTREE,
+        .cache_type = REGCACHE_FLAT,
 
         .volatile_reg = fsl_dcu_drm_is_volatile_reg,
+        .max_register = 0x11fc,
 };
 
 static int fsl_dcu_drm_irq_init(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5faacc6e548d..7c334e902266 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3481,6 +3481,7 @@ int intel_bios_init(struct drm_i915_private *dev_priv);
 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
+bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index b235b6e88ead..b9022fa053d6 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -139,6 +139,11 @@ fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode,
         else
                 panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC;
 
+        panel_fixed_mode->width_mm = (dvo_timing->himage_hi << 8) |
+                dvo_timing->himage_lo;
+        panel_fixed_mode->height_mm = (dvo_timing->vimage_hi << 8) |
+                dvo_timing->vimage_lo;
+
         /* Some VBTs have bogus h/vtotal values */
         if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
                 panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
@@ -1187,7 +1192,7 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
         }
         if (bdb->version < 106) {
                 expected_size = 22;
-        } else if (bdb->version < 109) {
+        } else if (bdb->version < 111) {
                 expected_size = 27;
         } else if (bdb->version < 195) {
                 BUILD_BUG_ON(sizeof(struct old_child_dev_config) != 33);
@@ -1546,6 +1551,45 @@ bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin)
 }
 
 /**
+ * intel_bios_is_port_present - is the specified digital port present
+ * @dev_priv:   i915 device instance
+ * @port:       port to check
+ *
+ * Return true if the device in %port is present.
+ */
+bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port)
+{
+        static const struct {
+                u16 dp, hdmi;
+        } port_mapping[] = {
+                [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, },
+                [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
+                [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
+                [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
+        };
+        int i;
+
+        /* FIXME maybe deal with port A as well? */
+        if (WARN_ON(port == PORT_A) || port >= ARRAY_SIZE(port_mapping))
+                return false;
+
+        if (!dev_priv->vbt.child_dev_num)
+                return false;
+
+        for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
+                const union child_device_config *p_child =
+                        &dev_priv->vbt.child_dev[i];
+                if ((p_child->common.dvo_port == port_mapping[port].dp ||
+                     p_child->common.dvo_port == port_mapping[port].hdmi) &&
+                    (p_child->common.device_type & (DEVICE_TYPE_TMDS_DVI_SIGNALING |
+                                                    DEVICE_TYPE_DISPLAYPORT_OUTPUT)))
+                        return true;
+        }
+
+        return false;
+}
+
+/**
  * intel_bios_is_port_edp - is the device in given port eDP
  * @dev_priv:   i915 device instance
  * @port:       port to check
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2113f401f0ba..56a1637c864f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8275,12 +8275,14 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_encoder *encoder;
+        int i;
         u32 val, final;
         bool has_lvds = false;
         bool has_cpu_edp = false;
         bool has_panel = false;
         bool has_ck505 = false;
         bool can_ssc = false;
+        bool using_ssc_source = false;
 
         /* We need to take the global config into account */
         for_each_intel_encoder(dev, encoder) {
@@ -8307,8 +8309,22 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
                 can_ssc = true;
         }
 
-        DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
-                      has_panel, has_lvds, has_ck505);
+        /* Check if any DPLLs are using the SSC source */
+        for (i = 0; i < dev_priv->num_shared_dpll; i++) {
+                u32 temp = I915_READ(PCH_DPLL(i));
+
+                if (!(temp & DPLL_VCO_ENABLE))
+                        continue;
+
+                if ((temp & PLL_REF_INPUT_MASK) ==
+                    PLLB_REF_INPUT_SPREADSPECTRUMIN) {
+                        using_ssc_source = true;
+                        break;
+                }
+        }
+
+        DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
+                      has_panel, has_lvds, has_ck505, using_ssc_source);
 
         /* Ironlake: try to setup display ref clock before DPLL
          * enabling. This is only under driver's control after
@@ -8345,9 +8361,9 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
                 } else
                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
-        } else {
-                final |= DREF_SSC_SOURCE_DISABLE;
-                final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
+        } else if (using_ssc_source) {
+                final |= DREF_SSC_SOURCE_ENABLE;
+                final |= DREF_SSC1_ENABLE;
         }
 
         if (final == val)
@@ -8393,7 +8409,7 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
                 POSTING_READ(PCH_DREF_CONTROL);
                 udelay(200);
         } else {
-                DRM_DEBUG_KMS("Disabling SSC entirely\n");
+                DRM_DEBUG_KMS("Disabling CPU source output\n");
 
                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
 
@@ -8404,16 +8420,20 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
                 POSTING_READ(PCH_DREF_CONTROL);
                 udelay(200);
 
-                /* Turn off the SSC source */
-                val &= ~DREF_SSC_SOURCE_MASK;
-                val |= DREF_SSC_SOURCE_DISABLE;
+                if (!using_ssc_source) {
+                        DRM_DEBUG_KMS("Disabling SSC source\n");
 
-                /* Turn off SSC1 */
-                val &= ~DREF_SSC1_ENABLE;
+                        /* Turn off the SSC source */
+                        val &= ~DREF_SSC_SOURCE_MASK;
+                        val |= DREF_SSC_SOURCE_DISABLE;
 
-                I915_WRITE(PCH_DREF_CONTROL, val);
-                POSTING_READ(PCH_DREF_CONTROL);
-                udelay(200);
+                        /* Turn off SSC1 */
+                        val &= ~DREF_SSC1_ENABLE;
+
+                        I915_WRITE(PCH_DREF_CONTROL, val);
+                        POSTING_READ(PCH_DREF_CONTROL);
+                        udelay(200);
+                }
         }
 
         BUG_ON(val != final);
@@ -14554,6 +14574,8 @@ static void intel_setup_outputs(struct drm_device *dev)
                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
                         intel_dp_init(dev, PCH_DP_D, PORT_D);
         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+                bool has_edp, has_port;
+
                 /*
                  * The DP_DETECTED bit is the latched state of the DDC
                  * SDA pin at boot. However since eDP doesn't require DDC
@@ -14562,27 +14584,37 @@ static void intel_setup_outputs(struct drm_device *dev)
                  * Thus we can't rely on the DP_DETECTED bit alone to detect
                  * eDP ports. Consult the VBT as well as DP_DETECTED to
                  * detect eDP ports.
+                 *
+                 * Sadly the straps seem to be missing sometimes even for HDMI
+                 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
+                 * and VBT for the presence of the port. Additionally we can't
+                 * trust the port type the VBT declares as we've seen at least
+                 * HDMI ports that the VBT claim are DP or eDP.
                  */
-                if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
-                    !intel_dp_is_edp(dev, PORT_B))
+                has_edp = intel_dp_is_edp(dev, PORT_B);
+                has_port = intel_bios_is_port_present(dev_priv, PORT_B);
+                if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
+                        has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
+                if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
-                if (I915_READ(VLV_DP_B) & DP_DETECTED ||
-                    intel_dp_is_edp(dev, PORT_B))
-                        intel_dp_init(dev, VLV_DP_B, PORT_B);
 
-                if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
-                    !intel_dp_is_edp(dev, PORT_C))
+                has_edp = intel_dp_is_edp(dev, PORT_C);
+                has_port = intel_bios_is_port_present(dev_priv, PORT_C);
+                if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
+                        has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
+                if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
-                if (I915_READ(VLV_DP_C) & DP_DETECTED ||
-                    intel_dp_is_edp(dev, PORT_C))
-                        intel_dp_init(dev, VLV_DP_C, PORT_C);
 
                 if (IS_CHERRYVIEW(dev)) {
-                        /* eDP not supported on port D, so don't check VBT */
-                        if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
-                                intel_hdmi_init(dev, CHV_HDMID, PORT_D);
-                        if (I915_READ(CHV_DP_D) & DP_DETECTED)
+                        /*
+                         * eDP not supported on port D,
+                         * so no need to worry about it
+                         */
+                        has_port = intel_bios_is_port_present(dev_priv, PORT_D);
+                        if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
+                        if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
+                                intel_hdmi_init(dev, CHV_HDMID, PORT_D);
                 }
 
                 intel_dsi_init(dev);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f192f58708c2..79cf2d5f5a20 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4977,9 +4977,6 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
         intel_display_power_get(dev_priv, power_domain);
 
         if (long_hpd) {
-                /* indicate that we need to restart link training */
-                intel_dp->train_set_valid = false;
-
                 intel_dp_long_pulse(intel_dp->attached_connector);
                 if (intel_dp->is_mst)
                         ret = IRQ_HANDLED;
@@ -5725,8 +5722,11 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
                 fixed_mode = drm_mode_duplicate(dev,
                                         dev_priv->vbt.lfp_lvds_vbt_mode);
-                if (fixed_mode)
+                if (fixed_mode) {
                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
+                        connector->display_info.width_mm = fixed_mode->width_mm;
+                        connector->display_info.height_mm = fixed_mode->height_mm;
+                }
         }
         mutex_unlock(&dev->mode_config.mutex);
 
@@ -5923,9 +5923,9 @@ fail:
         return false;
 }
 
-void
-intel_dp_init(struct drm_device *dev,
-              i915_reg_t output_reg, enum port port)
+bool intel_dp_init(struct drm_device *dev,
+                   i915_reg_t output_reg,
+                   enum port port)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_digital_port *intel_dig_port;
@@ -5935,7 +5935,7 @@ intel_dp_init(struct drm_device *dev,
 
         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
         if (!intel_dig_port)
-                return;
+                return false;
 
         intel_connector = intel_connector_alloc();
         if (!intel_connector)
@@ -5992,7 +5992,7 @@ intel_dp_init(struct drm_device *dev,
         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
                 goto err_init_connector;
 
-        return;
+        return true;
 
 err_init_connector:
         drm_encoder_cleanup(encoder);
@@ -6000,8 +6000,7 @@ err_encoder_init:
         kfree(intel_connector);
 err_connector_alloc:
         kfree(intel_dig_port);
-
-        return;
+        return false;
 }
 
 void intel_dp_mst_suspend(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 0b8eefc2acc5..60fb39cd220b 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -85,8 +85,7 @@ static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
                         uint8_t dp_train_pat)
 {
-        if (!intel_dp->train_set_valid)
-                memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
+        memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
         intel_dp_set_signal_levels(intel_dp);
         return intel_dp_set_link_train(intel_dp, dp_train_pat);
 }
@@ -161,23 +160,6 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
                         break;
                 }
 
-                /*
-                 * if we used previously trained voltage and pre-emphasis values
-                 * and we don't get clock recovery, reset link training values
-                 */
-                if (intel_dp->train_set_valid) {
-                        DRM_DEBUG_KMS("clock recovery not ok, reset");
-                        /* clear the flag as we are not reusing train set */
-                        intel_dp->train_set_valid = false;
-                        if (!intel_dp_reset_link_train(intel_dp,
-                                                       DP_TRAINING_PATTERN_1 |
-                                                       DP_LINK_SCRAMBLING_DISABLE)) {
-                                DRM_ERROR("failed to enable link training\n");
-                                return;
-                        }
-                        continue;
-                }
-
                 /* Check to see if we've tried the max voltage */
                 for (i = 0; i < intel_dp->lane_count; i++)
                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
@@ -284,7 +266,6 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
                 /* Make sure clock is still ok */
                 if (!drm_dp_clock_recovery_ok(link_status,
                                               intel_dp->lane_count)) {
-                        intel_dp->train_set_valid = false;
                         intel_dp_link_training_clock_recovery(intel_dp);
                         intel_dp_set_link_train(intel_dp,
                                                 training_pattern |
@@ -301,7 +282,6 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 
                 /* Try 5 times, then try clock recovery if that fails */
                 if (tries > 5) {
-                        intel_dp->train_set_valid = false;
                         intel_dp_link_training_clock_recovery(intel_dp);
                         intel_dp_set_link_train(intel_dp,
                                                 training_pattern |
@@ -322,10 +302,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 
         intel_dp_set_idle_link_train(intel_dp);
 
-        if (channel_eq) {
-                intel_dp->train_set_valid = true;
+        if (channel_eq)
                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
-        }
 }
 
 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 3ac705936b04..baf6f5584cbd 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -366,6 +366,9 @@ ibx_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
                                              DPLL_ID_PCH_PLL_B);
         }
 
+        if (!pll)
+                return NULL;
+
         /* reference the pll */
         intel_reference_shared_dpll(pll, crtc_state);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a28b4aac1e02..f7f0f01814f6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -863,8 +863,6 @@ struct intel_dp {
         /* This is called before a link training is starterd */
         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 
-        bool train_set_valid;
-
         /* Displayport compliance testing */
         unsigned long compliance_test_type;
         unsigned long compliance_test_data;
@@ -1284,7 +1282,7 @@ void intel_csr_ucode_suspend(struct drm_i915_private *);
 void intel_csr_ucode_resume(struct drm_i915_private *);
 
 /* intel_dp.c */
-void intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
+bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
                              struct intel_connector *intel_connector);
 void intel_dp_set_link_params(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 366ad6c67ce4..4756ef639648 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1545,6 +1545,9 @@ void intel_dsi_init(struct drm_device *dev)
                 goto err;
         }
 
+        connector->display_info.width_mm = fixed_mode->width_mm;
+        connector->display_info.height_mm = fixed_mode->height_mm;
+
         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
 
         intel_dsi_add_properties(intel_connector);
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index d5a7cfec589b..647127f3aaff 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -824,8 +824,7 @@ static bool intel_fbc_can_choose(struct intel_crtc *crtc)
 {
         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
         struct intel_fbc *fbc = &dev_priv->fbc;
-        bool enable_by_default = IS_HASWELL(dev_priv) ||
-                                 IS_BROADWELL(dev_priv);
+        bool enable_by_default = IS_BROADWELL(dev_priv);
 
         if (intel_vgpu_active(dev_priv->dev)) {
                 fbc->no_fbc_reason = "VGPU is active";
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 2c3bd9c2573e..a8844702d11b 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2142,6 +2142,9 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
         enum port port = intel_dig_port->port;
         uint8_t alternate_ddc_pin;
 
+        DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
+                      port_name(port));
+
         if (WARN(intel_dig_port->max_lanes < 4,
                  "Not enough lanes (%d) for HDMI on port %c\n",
                  intel_dig_port->max_lanes, port_name(port)))
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index bc53c0dd34d0..96281e628d2a 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -1082,6 +1082,8 @@ void intel_lvds_init(struct drm_device *dev)
                 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
                 if (fixed_mode) {
                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
+                        connector->display_info.width_mm = fixed_mode->width_mm;
+                        connector->display_info.height_mm = fixed_mode->height_mm;
                         goto out;
                 }
         }
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
index c15051de8023..44fb0b35eed3 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -403,9 +403,10 @@ struct lvds_dvo_timing {
         u8 vsync_off:4;
         u8 rsvd0:6;
         u8 hsync_off_hi:2;
-        u8 h_image;
-        u8 v_image;
-        u8 max_hv;
+        u8 himage_lo;
+        u8 vimage_lo;
+        u8 vimage_hi:4;
+        u8 himage_hi:4;
         u8 h_border;
         u8 v_border;
         u8 rsvd1:3;
diff --git a/drivers/gpu/drm/imx/imx-drm-core.c b/drivers/gpu/drm/imx/imx-drm-core.c
index 1f14b602882b..82656654fb21 100644
--- a/drivers/gpu/drm/imx/imx-drm-core.c
+++ b/drivers/gpu/drm/imx/imx-drm-core.c
@@ -97,8 +97,8 @@ static struct imx_drm_crtc *imx_drm_find_crtc(struct drm_crtc *crtc)
         return NULL;
 }
 
-int imx_drm_set_bus_format_pins(struct drm_encoder *encoder, u32 bus_format,
-                int hsync_pin, int vsync_pin)
+int imx_drm_set_bus_config(struct drm_encoder *encoder, u32 bus_format,
+                int hsync_pin, int vsync_pin, u32 bus_flags)
 {
         struct imx_drm_crtc_helper_funcs *helper;
         struct imx_drm_crtc *imx_crtc;
@@ -110,14 +110,17 @@ int imx_drm_set_bus_format_pins(struct drm_encoder *encoder, u32 bus_format,
         helper = &imx_crtc->imx_drm_helper_funcs;
         if (helper->set_interface_pix_fmt)
                 return helper->set_interface_pix_fmt(encoder->crtc,
-                                        bus_format, hsync_pin, vsync_pin);
+                                        bus_format, hsync_pin, vsync_pin,
+                                        bus_flags);
         return 0;
 }
-EXPORT_SYMBOL_GPL(imx_drm_set_bus_format_pins);
+EXPORT_SYMBOL_GPL(imx_drm_set_bus_config);
 
 int imx_drm_set_bus_format(struct drm_encoder *encoder, u32 bus_format)
 {
-        return imx_drm_set_bus_format_pins(encoder, bus_format, 2, 3);
+        return imx_drm_set_bus_config(encoder, bus_format, 2, 3,
+                                      DRM_BUS_FLAG_DE_HIGH |
+                                      DRM_BUS_FLAG_PIXDATA_NEGEDGE);
 }
 EXPORT_SYMBOL_GPL(imx_drm_set_bus_format);
 
diff --git a/drivers/gpu/drm/imx/imx-drm.h b/drivers/gpu/drm/imx/imx-drm.h
index b0241b9d1334..74320a1723b7 100644
--- a/drivers/gpu/drm/imx/imx-drm.h
+++ b/drivers/gpu/drm/imx/imx-drm.h
@@ -19,7 +19,8 @@ struct imx_drm_crtc_helper_funcs {
         int (*enable_vblank)(struct drm_crtc *crtc);
         void (*disable_vblank)(struct drm_crtc *crtc);
         int (*set_interface_pix_fmt)(struct drm_crtc *crtc,
-                        u32 bus_format, int hsync_pin, int vsync_pin);
+                        u32 bus_format, int hsync_pin, int vsync_pin,
+                        u32 bus_flags);
         const struct drm_crtc_helper_funcs *crtc_helper_funcs;
         const struct drm_crtc_funcs *crtc_funcs;
 };
@@ -41,8 +42,8 @@ void imx_drm_mode_config_init(struct drm_device *drm);
 
 struct drm_gem_cma_object *imx_drm_fb_get_obj(struct drm_framebuffer *fb);
 
-int imx_drm_set_bus_format_pins(struct drm_encoder *encoder,
-                u32 bus_format, int hsync_pin, int vsync_pin);
+int imx_drm_set_bus_config(struct drm_encoder *encoder, u32 bus_format,
+                int hsync_pin, int vsync_pin, u32 bus_flags);
 int imx_drm_set_bus_format(struct drm_encoder *encoder,
                 u32 bus_format);
 
diff --git a/drivers/gpu/drm/imx/imx-ldb.c b/drivers/gpu/drm/imx/imx-ldb.c
index a58eee59550a..beff793bb717 100644
--- a/drivers/gpu/drm/imx/imx-ldb.c
+++ b/drivers/gpu/drm/imx/imx-ldb.c
@@ -25,6 +25,7 @@
 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
 #include <linux/of_device.h>
 #include <linux/of_graph.h>
+#include <video/of_display_timing.h>
 #include <video/of_videomode.h>
 #include <linux/regmap.h>
 #include <linux/videodev2.h>
@@ -59,6 +60,7 @@ struct imx_ldb_channel {
         struct drm_encoder encoder;
         struct drm_panel *panel;
         struct device_node *child;
+        struct i2c_adapter *ddc;
         int chno;
         void *edid;
         int edid_len;
@@ -107,6 +109,9 @@ static int imx_ldb_connector_get_modes(struct drm_connector *connector)
                         return num_modes;
         }
 
+        if (!imx_ldb_ch->edid && imx_ldb_ch->ddc)
+                imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc);
+
         if (imx_ldb_ch->edid) {
                 drm_mode_connector_update_edid_property(connector,
                                                         imx_ldb_ch->edid);
@@ -553,7 +558,8 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
 
         for_each_child_of_node(np, child) {
                 struct imx_ldb_channel *channel;
-                struct device_node *port;
+                struct device_node *ddc_node;
+                struct device_node *ep;
 
                 ret = of_property_read_u32(child, "reg", &i);
                 if (ret || i < 0 || i > 1)
@@ -576,33 +582,54 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
                  * The output port is port@4 with an external 4-port mux or
                  * port@2 with the internal 2-port mux.
                  */
-                port = of_graph_get_port_by_id(child, imx_ldb->lvds_mux ? 4 : 2);
-                if (port) {
-                        struct device_node *endpoint, *remote;
-
-                        endpoint = of_get_child_by_name(port, "endpoint");
-                        if (endpoint) {
-                                remote = of_graph_get_remote_port_parent(endpoint);
-                                if (remote)
-                                        channel->panel = of_drm_find_panel(remote);
-                                else
-                                        return -EPROBE_DEFER;
-                                if (!channel->panel) {
-                                        dev_err(dev, "panel not found: %s\n",
-                                                remote->full_name);
-                                        return -EPROBE_DEFER;
-                                }
+                ep = of_graph_get_endpoint_by_regs(child,
+                                                   imx_ldb->lvds_mux ? 4 : 2,
+                                                   -1);
+                if (ep) {
+                        struct device_node *remote;
+
+                        remote = of_graph_get_remote_port_parent(ep);
+                        of_node_put(ep);
+                        if (remote)
+                                channel->panel = of_drm_find_panel(remote);
+                        else
+                                return -EPROBE_DEFER;
+                        of_node_put(remote);
+                        if (!channel->panel) {
+                                dev_err(dev, "panel not found: %s\n",
+                                        remote->full_name);
+                                return -EPROBE_DEFER;
                         }
                 }
 
-                edidp = of_get_property(child, "edid", &channel->edid_len);
-                if (edidp) {
-                        channel->edid = kmemdup(edidp, channel->edid_len,
-                                                GFP_KERNEL);
-                } else if (!channel->panel) {
-                        ret = of_get_drm_display_mode(child, &channel->mode, 0);
-                        if (!ret)
-                                channel->mode_valid = 1;
+                ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0);
+                if (ddc_node) {
+                        channel->ddc = of_find_i2c_adapter_by_node(ddc_node);
+                        of_node_put(ddc_node);
+                        if (!channel->ddc) {
+                                dev_warn(dev, "failed to get ddc i2c adapter\n");
+                                return -EPROBE_DEFER;
+                        }
+                }
+
+                if (!channel->ddc) {
+                        /* if no DDC available, fallback to hardcoded EDID */
+                        dev_dbg(dev, "no ddc available\n");
+
+                        edidp = of_get_property(child, "edid",
+                                                &channel->edid_len);
+                        if (edidp) {
+                                channel->edid = kmemdup(edidp,
+                                                        channel->edid_len,
+                                                        GFP_KERNEL);
+                        } else if (!channel->panel) {
+                                /* fallback to display-timings node */
+                                ret = of_get_drm_display_mode(child,
+                                                              &channel->mode,
+                                                              OF_USE_NATIVE_MODE);
+                                if (!ret)
+                                        channel->mode_valid = 1;
+                        }
                 }
 
                 channel->bus_format = of_get_bus_format(dev, child);
@@ -647,6 +674,7 @@ static void imx_ldb_unbind(struct device *dev, struct device *master,
                 channel->encoder.funcs->destroy(&channel->encoder);
 
                 kfree(channel->edid);
+                i2c_put_adapter(channel->ddc);
         }
 }
 
diff --git a/drivers/gpu/drm/imx/imx-tve.c b/drivers/gpu/drm/imx/imx-tve.c
index ae7a9fb3b8a2..baf788121287 100644
--- a/drivers/gpu/drm/imx/imx-tve.c
+++ b/drivers/gpu/drm/imx/imx-tve.c
@@ -294,8 +294,10 @@ static void imx_tve_encoder_prepare(struct drm_encoder *encoder)
 
         switch (tve->mode) {
         case TVE_MODE_VGA:
-                imx_drm_set_bus_format_pins(encoder, MEDIA_BUS_FMT_GBR888_1X24,
-                                            tve->hsync_pin, tve->vsync_pin);
+                imx_drm_set_bus_config(encoder, MEDIA_BUS_FMT_GBR888_1X24,
+                                       tve->hsync_pin, tve->vsync_pin,
+                                       DRM_BUS_FLAG_DE_HIGH |
+                                       DRM_BUS_FLAG_PIXDATA_NEGEDGE);
                 break;
         case TVE_MODE_TVOUT:
                 imx_drm_set_bus_format(encoder, MEDIA_BUS_FMT_YUV8_1X24);
diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c
index b2c30b8d9816..fc040417e1e8 100644
--- a/drivers/gpu/drm/imx/ipuv3-crtc.c
+++ b/drivers/gpu/drm/imx/ipuv3-crtc.c
@@ -66,6 +66,7 @@ struct ipu_crtc {
         struct ipu_flip_work    *flip_work;
         int                     irq;
         u32                     bus_format;
+        u32                     bus_flags;
         int                     di_hsync_pin;
         int                     di_vsync_pin;
 };
@@ -271,8 +272,10 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
         else
                 sig_cfg.clkflags = 0;
 
-        sig_cfg.enable_pol = 1;
-        sig_cfg.clk_pol = 0;
+        sig_cfg.enable_pol = !(ipu_crtc->bus_flags & DRM_BUS_FLAG_DE_LOW);
+        /* Default to driving pixel data on negative clock edges */
+        sig_cfg.clk_pol = !!(ipu_crtc->bus_flags &
+                             DRM_BUS_FLAG_PIXDATA_POSEDGE);
         sig_cfg.bus_format = ipu_crtc->bus_format;
         sig_cfg.v_to_h_sync = 0;
         sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
@@ -396,11 +399,12 @@ static void ipu_disable_vblank(struct drm_crtc *crtc)
 }
 
 static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc,
-                u32 bus_format, int hsync_pin, int vsync_pin)
+                u32 bus_format, int hsync_pin, int vsync_pin, u32 bus_flags)
 {
         struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
 
         ipu_crtc->bus_format = bus_format;
+        ipu_crtc->bus_flags = bus_flags;
         ipu_crtc->di_hsync_pin = hsync_pin;
         ipu_crtc->di_vsync_pin = vsync_pin;
 
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3-plane.c
index 681ec6eb77d9..a4bb44118d33 100644
--- a/drivers/gpu/drm/imx/ipuv3-plane.c
+++ b/drivers/gpu/drm/imx/ipuv3-plane.c
@@ -38,6 +38,8 @@ static const uint32_t ipu_plane_formats[] = {
         DRM_FORMAT_RGBX8888,
         DRM_FORMAT_BGRA8888,
         DRM_FORMAT_BGRA8888,
+        DRM_FORMAT_UYVY,
+        DRM_FORMAT_VYUY,
         DRM_FORMAT_YUYV,
         DRM_FORMAT_YVYU,
         DRM_FORMAT_YUV420,
@@ -428,7 +430,6 @@ static int ipu_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
         if (crtc != plane->crtc)
                 dev_dbg(plane->dev->dev, "crtc change: %p -> %p\n",
                                 plane->crtc, crtc);
-        plane->crtc = crtc;
 
         if (!ipu_plane->enabled)
                 ipu_plane_enable(ipu_plane);
@@ -461,7 +462,7 @@ static void ipu_plane_destroy(struct drm_plane *plane)
         kfree(ipu_plane);
 }
 
-static struct drm_plane_funcs ipu_plane_funcs = {
+static const struct drm_plane_funcs ipu_plane_funcs = {
         .update_plane   = ipu_update_plane,
         .disable_plane  = ipu_disable_plane,
         .destroy        = ipu_plane_destroy,
diff --git a/drivers/gpu/drm/imx/parallel-display.c b/drivers/gpu/drm/imx/parallel-display.c
index 363e2c7741e2..2d1fd02cd3d6 100644
--- a/drivers/gpu/drm/imx/parallel-display.c
+++ b/drivers/gpu/drm/imx/parallel-display.c
@@ -35,7 +35,6 @@ struct imx_parallel_display {
         void *edid;
         int edid_len;
         u32 bus_format;
-        int mode_valid;
         struct drm_display_mode mode;
         struct drm_panel *panel;
 };
@@ -68,17 +67,6 @@ static int imx_pd_connector_get_modes(struct drm_connector *connector)
                 num_modes = drm_add_edid_modes(connector, imxpd->edid);
         }
 
-        if (imxpd->mode_valid) {
-                struct drm_display_mode *mode = drm_mode_create(connector->dev);
-
-                if (!mode)
-                        return -EINVAL;
-                drm_mode_copy(mode, &imxpd->mode);
-                mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
-                drm_mode_probed_add(connector, mode);
-                num_modes++;
-        }
-
         if (np) {
                 struct drm_display_mode *mode = drm_mode_create(connector->dev);
 
@@ -115,8 +103,8 @@ static void imx_pd_encoder_dpms(struct drm_encoder *encoder, int mode)
 static void imx_pd_encoder_prepare(struct drm_encoder *encoder)
 {
         struct imx_parallel_display *imxpd = enc_to_imxpd(encoder);
-
-        imx_drm_set_bus_format(encoder, imxpd->bus_format);
+        imx_drm_set_bus_config(encoder, imxpd->bus_format, 2, 3,
+                               imxpd->connector.display_info.bus_flags);
 }
 
 static void imx_pd_encoder_commit(struct drm_encoder *encoder)
@@ -203,7 +191,7 @@ static int imx_pd_bind(struct device *dev, struct device *master, void *data)
 {
         struct drm_device *drm = data;
         struct device_node *np = dev->of_node;
-        struct device_node *port;
+        struct device_node *ep;
         const u8 *edidp;
         struct imx_parallel_display *imxpd;
         int ret;
@@ -230,18 +218,18 @@ static int imx_pd_bind(struct device *dev, struct device *master, void *data)
         }
 
         /* port@1 is the output port */
-        port = of_graph_get_port_by_id(np, 1);
-        if (port) {
-                struct device_node *endpoint, *remote;
-
-                endpoint = of_get_child_by_name(port, "endpoint");
-                if (endpoint) {
-                        remote = of_graph_get_remote_port_parent(endpoint);
-                        if (remote)
-                                imxpd->panel = of_drm_find_panel(remote);
-                        if (!imxpd->panel)
-                                return -EPROBE_DEFER;
+        ep = of_graph_get_endpoint_by_regs(np, 1, -1);
+        if (ep) {
+                struct device_node *remote;
+
+                remote = of_graph_get_remote_port_parent(ep);
+                of_node_put(ep);
+                if (remote) {
+                        imxpd->panel = of_drm_find_panel(remote);
+                        of_node_put(remote);
                 }
+                if (!imxpd->panel)
+                        return -EPROBE_DEFER;
         }
 
         imxpd->dev = dev;
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index d05ca7901315..0186e500d2a5 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -432,11 +432,6 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
         unsigned long pll_rate;
         unsigned int factor;
 
-        if (!dpi) {
-                dev_err(dpi->dev, "invalid argument\n");
-                return -EINVAL;
-        }
-
         pix_rate = 1000UL * mode->clock;
         if (mode->clock <= 74000)
                 factor = 8 * 3;
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 2d808e59fefd..769559124562 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -695,10 +695,8 @@ static void mtk_dsi_destroy_conn_enc(struct mtk_dsi *dsi)
 {
         drm_encoder_cleanup(&dsi->encoder);
         /* Skip connector cleanup if creation was delegated to the bridge */
-        if (dsi->conn.dev) {
-                drm_connector_unregister(&dsi->conn);
+        if (dsi->conn.dev)
                 drm_connector_cleanup(&dsi->conn);
-        }
 }
 
 static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp)
diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c b/drivers/gpu/drm/mgag200/mgag200_mode.c
index 14e64e08909e..d347dca17267 100644
--- a/drivers/gpu/drm/mgag200/mgag200_mode.c
+++ b/drivers/gpu/drm/mgag200/mgag200_mode.c
@@ -182,7 +182,7 @@ static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
                         }
                 }
 
-                fvv = pllreffreq * testn / testm;
+                fvv = pllreffreq * (n + 1) / (m + 1);
                 fvv = (fvv - 800000) / 50000;
 
                 if (fvv > 15)
@@ -202,6 +202,14 @@ static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
         WREG_DAC(MGA1064_PIX_PLLC_M, m);
         WREG_DAC(MGA1064_PIX_PLLC_N, n);
         WREG_DAC(MGA1064_PIX_PLLC_P, p);
+
+        if (mdev->unique_rev_id >= 0x04) {
+                WREG_DAC(0x1a, 0x09);
+                msleep(20);
+                WREG_DAC(0x1a, 0x01);
+
+        }
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index fbe304ee6c80..2aec27dbb5bb 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -408,7 +408,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
         }
 
         adreno_gpu->memptrs = msm_gem_vaddr(adreno_gpu->memptrs_bo);
-        if (!adreno_gpu->memptrs) {
+        if (IS_ERR(adreno_gpu->memptrs)) {
                 dev_err(drm->dev, "could not vmap memptrs\n");
                 return -ENOMEM;
         }
diff --git a/drivers/gpu/drm/msm/msm_fbdev.c b/drivers/gpu/drm/msm/msm_fbdev.c
index d9759bf3482e..c6cf837c5193 100644
--- a/drivers/gpu/drm/msm/msm_fbdev.c
+++ b/drivers/gpu/drm/msm/msm_fbdev.c
@@ -159,6 +159,10 @@ static int msm_fbdev_create(struct drm_fb_helper *helper,
         dev->mode_config.fb_base = paddr;
 
         fbi->screen_base = msm_gem_vaddr_locked(fbdev->bo);
+        if (IS_ERR(fbi->screen_base)) {
+                ret = PTR_ERR(fbi->screen_base);
+                goto fail_unlock;
+        }
         fbi->screen_size = fbdev->bo->size;
         fbi->fix.smem_start = paddr;
         fbi->fix.smem_len = fbdev->bo->size;
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 7daf4054dd2b..69836f5685b1 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -398,6 +398,8 @@ void *msm_gem_vaddr_locked(struct drm_gem_object *obj)
                         return ERR_CAST(pages);
                 msm_obj->vaddr = vmap(pages, obj->size >> PAGE_SHIFT,
                                 VM_MAP, pgprot_writecombine(PAGE_KERNEL));
+                if (msm_obj->vaddr == NULL)
+                        return ERR_PTR(-ENOMEM);
         }
         return msm_obj->vaddr;
 }
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c
index b89ca5174863..eb4bb8b2f3a5 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -40,12 +40,14 @@ static struct msm_gem_submit *submit_create(struct drm_device *dev,
 
         submit->dev = dev;
         submit->gpu = gpu;
+        submit->fence = NULL;
         submit->pid = get_pid(task_pid(current));
 
         /* initially, until copy_from_user() and bo lookup succeeds: */
         submit->nr_bos = 0;
         submit->nr_cmds = 0;
 
+        INIT_LIST_HEAD(&submit->node);
         INIT_LIST_HEAD(&submit->bo_list);
         ww_acquire_init(&submit->ticket, &reservation_ww_class);
 
@@ -75,6 +77,11 @@ static int submit_lookup_objects(struct msm_gem_submit *submit,
                 void __user *userptr =
                         u64_to_user_ptr(args->bos + (i * sizeof(submit_bo)));
 
+                /* make sure we don't have garbage flags, in case we hit
+                 * error path before flags is initialized:
+                 */
+                submit->bos[i].flags = 0;
+
                 ret = copy_from_user(&submit_bo, userptr, sizeof(submit_bo));
                 if (ret) {
                         ret = -EFAULT;
diff --git a/drivers/gpu/drm/msm/msm_rd.c b/drivers/gpu/drm/msm/msm_rd.c
index b48f73ac6389..0857710c2ff2 100644
--- a/drivers/gpu/drm/msm/msm_rd.c
+++ b/drivers/gpu/drm/msm/msm_rd.c
@@ -312,6 +312,9 @@ void msm_rd_dump_submit(struct msm_gem_submit *submit)
                 struct msm_gem_object *obj = submit->bos[idx].obj;
                 const char *buf = msm_gem_vaddr_locked(&obj->base);
 
+                if (IS_ERR(buf))
+                        continue;
+
                 buf += iova - submit->bos[idx].iova;
 
                 rd_write_section(rd, RD_GPUADDR,
diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c
index 1f14b908b221..42f5359cf988 100644
--- a/drivers/gpu/drm/msm/msm_ringbuffer.c
+++ b/drivers/gpu/drm/msm/msm_ringbuffer.c
@@ -40,6 +40,10 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int size)
         }
 
         ring->start = msm_gem_vaddr_locked(ring->bo);
+        if (IS_ERR(ring->start)) {
+                ret = PTR_ERR(ring->start);
+                goto fail;
+        }
         ring->end   = ring->start + (size / 4);
         ring->cur   = ring->start;
 
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index c612dc1f1eb4..126a85cc81bc 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -16,9 +16,9 @@ enum nvkm_devidx {
         NVKM_SUBDEV_MC,
         NVKM_SUBDEV_BUS,
         NVKM_SUBDEV_TIMER,
+        NVKM_SUBDEV_INSTMEM,
         NVKM_SUBDEV_FB,
         NVKM_SUBDEV_LTC,
-        NVKM_SUBDEV_INSTMEM,
         NVKM_SUBDEV_MMU,
         NVKM_SUBDEV_BAR,
         NVKM_SUBDEV_PMU,
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h
index db10c11f0595..c5a6ebd5a478 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h
@@ -25,7 +25,8 @@ u16 nvbios_outp_match(struct nvkm_bios *, u16 type, u16 mask,
                       u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_outp *);
 
 struct nvbios_ocfg {
-        u16 match;
+        u8  proto;
+        u8  flags;
         u16 clkcmp[2];
 };
 
@@ -33,7 +34,7 @@ u16 nvbios_ocfg_entry(struct nvkm_bios *, u16 outp, u8 idx,
                       u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
 u16 nvbios_ocfg_parse(struct nvkm_bios *, u16 outp, u8 idx,
                       u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ocfg *);
-u16 nvbios_ocfg_match(struct nvkm_bios *, u16 outp, u16 type,
+u16 nvbios_ocfg_match(struct nvkm_bios *, u16 outp, u8 proto, u8 flags,
                       u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ocfg *);
 u16 nvbios_oclk_match(struct nvkm_bios *, u16 cmp, u32 khz);
 #endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 57aaf98a26f9..d1f248fd3506 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -552,6 +552,8 @@ nouveau_fbcon_init(struct drm_device *dev)
         if (ret)
                 goto fini;
 
+        if (fbcon->helper.fbdev)
+                fbcon->helper.fbdev->pixmap.buf_align = 4;
         return 0;
 
 fini:
diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c
index 0f3e4bb411cc..7d9248b8c664 100644
--- a/drivers/gpu/drm/nouveau/nv04_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c
@@ -82,7 +82,6 @@ nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
         uint32_t fg;
         uint32_t bg;
         uint32_t dsize;
-        uint32_t width;
         uint32_t *data = (uint32_t *)image->data;
         int ret;
 
@@ -93,9 +92,6 @@ nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
         if (ret)
                 return ret;
 
-        width = ALIGN(image->width, 8);
-        dsize = ALIGN(width * image->height, 32) >> 5;
-
         if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
             info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
                 fg = ((uint32_t *) info->pseudo_palette)[image->fg_color];
@@ -111,10 +107,11 @@ nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
                          ((image->dx + image->width) & 0xffff));
         OUT_RING(chan, bg);
         OUT_RING(chan, fg);
-        OUT_RING(chan, (image->height << 16) | width);
+        OUT_RING(chan, (image->height << 16) | image->width);
         OUT_RING(chan, (image->height << 16) | image->width);
         OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));
 
+        dsize = ALIGN(image->width * image->height, 32) >> 5;
         while (dsize) {
                 int iter_len = dsize > 128 ? 128 : dsize;
 
diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c
index 33d9ee0fac40..1aeb698e9707 100644
--- a/drivers/gpu/drm/nouveau/nv50_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c
@@ -95,7 +95,7 @@ nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
         struct nouveau_fbdev *nfbdev = info->par;
         struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
         struct nouveau_channel *chan = drm->channel;
-        uint32_t width, dwords, *data = (uint32_t *)image->data;
+        uint32_t dwords, *data = (uint32_t *)image->data;
         uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel));
         uint32_t *palette = info->pseudo_palette;
         int ret;
@@ -107,9 +107,6 @@ nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
         if (ret)
                 return ret;
 
-        width = ALIGN(image->width, 32);
-        dwords = (width * image->height) >> 5;
-
         BEGIN_NV04(chan, NvSub2D, 0x0814, 2);
         if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
             info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
@@ -128,6 +125,7 @@ nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
         OUT_RING(chan, 0);
         OUT_RING(chan, image->dy);
 
+        dwords = ALIGN(image->width * image->height, 32) >> 5;
         while (dwords) {
                 int push = dwords > 2047 ? 2047 : dwords;
 
diff --git a/drivers/gpu/drm/nouveau/nvc0_fbcon.c b/drivers/gpu/drm/nouveau/nvc0_fbcon.c
index a0913359ac05..839f4c8c1805 100644
--- a/drivers/gpu/drm/nouveau/nvc0_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nvc0_fbcon.c
@@ -95,7 +95,7 @@ nvc0_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
         struct nouveau_fbdev *nfbdev = info->par;
         struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
         struct nouveau_channel *chan = drm->channel;
-        uint32_t width, dwords, *data = (uint32_t *)image->data;
+        uint32_t dwords, *data = (uint32_t *)image->data;
         uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel));
         uint32_t *palette = info->pseudo_palette;
         int ret;
@@ -107,9 +107,6 @@ nvc0_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
         if (ret)
                 return ret;
 
-        width = ALIGN(image->width, 32);
-        dwords = (width * image->height) >> 5;
-
         BEGIN_NVC0(chan, NvSub2D, 0x0814, 2);
         if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
             info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
@@ -128,6 +125,7 @@ nvc0_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
         OUT_RING  (chan, 0);
         OUT_RING  (chan, image->dy);
 
+        dwords = ALIGN(image->width * image->height, 32) >> 5;
         while (dwords) {
                 int push = dwords > 2047 ? 2047 : dwords;
 
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c
index 18fab3973ce5..62ad0300cfa5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c
@@ -1614,7 +1614,7 @@ nvkm_device_pci_func = {
         .fini = nvkm_device_pci_fini,
         .resource_addr = nvkm_device_pci_resource_addr,
         .resource_size = nvkm_device_pci_resource_size,
-        .cpu_coherent = !IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_ARM64),
+        .cpu_coherent = !IS_ENABLED(CONFIG_ARM),
 };
 
 int
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
index a74c5dd27dc0..e2a64ed14b22 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
@@ -18,6 +18,7 @@ nvkm-y += nvkm/engine/disp/piornv50.o
 nvkm-y += nvkm/engine/disp/sornv50.o
 nvkm-y += nvkm/engine/disp/sorg94.o
 nvkm-y += nvkm/engine/disp/sorgf119.o
+nvkm-y += nvkm/engine/disp/sorgm107.o
 nvkm-y += nvkm/engine/disp/sorgm200.o
 nvkm-y += nvkm/engine/disp/dport.o
 
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
index f0314664349c..5dd34382f55a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
@@ -76,6 +76,7 @@ exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl,
         mask |= 0x0001 << or;
         mask |= 0x0100 << head;
 
+
         list_for_each_entry(outp, &disp->base.outp, head) {
                 if ((outp->info.hasht & 0xff) == type &&
                     (outp->info.hashm & mask) == mask) {
@@ -155,25 +156,21 @@ exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf)
         if (!outp)
                 return NULL;
 
+        *conf = (ctrl & 0x00000f00) >> 8;
         switch (outp->info.type) {
         case DCB_OUTPUT_TMDS:
-                *conf = (ctrl & 0x00000f00) >> 8;
                 if (*conf == 5)
                         *conf |= 0x0100;
                 break;
         case DCB_OUTPUT_LVDS:
-                *conf = disp->sor.lvdsconf;
-                break;
-        case DCB_OUTPUT_DP:
-                *conf = (ctrl & 0x00000f00) >> 8;
+                *conf |= disp->sor.lvdsconf;
                 break;
-        case DCB_OUTPUT_ANALOG:
         default:
-                *conf = 0x00ff;
                 break;
         }
 
-        data = nvbios_ocfg_match(bios, data, *conf, &ver, &hdr, &cnt, &len, &info2);
+        data = nvbios_ocfg_match(bios, data, *conf & 0xff, *conf >> 8,
+                                 &ver, &hdr, &cnt, &len, &info2);
         if (data && id < 0xff) {
                 data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
                 if (data) {
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
index b6944142d616..f4b9cf8574be 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
@@ -36,7 +36,7 @@ gm107_disp = {
         .outp.internal.crt = nv50_dac_output_new,
         .outp.internal.tmds = nv50_sor_output_new,
         .outp.internal.lvds = nv50_sor_output_new,
-        .outp.internal.dp = gf119_sor_dp_new,
+        .outp.internal.dp = gm107_sor_dp_new,
         .dac.nr = 3,
         .dac.power = nv50_dac_power,
         .dac.sense = nv50_dac_sense,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
index 4226d2153b9c..fcb1b0c46d64 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
@@ -387,22 +387,17 @@ exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf)
         if (!outp)
                 return NULL;
 
+        *conf = (ctrl & 0x00000f00) >> 8;
         if (outp->info.location == 0) {
                 switch (outp->info.type) {
                 case DCB_OUTPUT_TMDS:
-                        *conf = (ctrl & 0x00000f00) >> 8;
                         if (*conf == 5)
                                 *conf |= 0x0100;
                         break;
                 case DCB_OUTPUT_LVDS:
-                        *conf = disp->sor.lvdsconf;
+                        *conf |= disp->sor.lvdsconf;
                         break;
-                case DCB_OUTPUT_DP:
-                        *conf = (ctrl & 0x00000f00) >> 8;
-                        break;
-                case DCB_OUTPUT_ANALOG:
                 default:
-                        *conf = 0x00ff;
                         break;
                 }
         } else {
@@ -410,7 +405,8 @@ exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf)
                 pclk = pclk / 2;
         }
 
-        data = nvbios_ocfg_match(bios, data, *conf, &ver, &hdr, &cnt, &len, &info2);
+        data = nvbios_ocfg_match(bios, data, *conf & 0xff, *conf >> 8,
+                                 &ver, &hdr, &cnt, &len, &info2);
         if (data && id < 0xff) {
                 data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
                 if (data) {
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.h
index e9067ba4e179..4e983f6d7032 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.h
@@ -62,7 +62,12 @@ int g94_sor_dp_lnk_pwr(struct nvkm_output_dp *, int);
 int gf119_sor_dp_new(struct nvkm_disp *, int, struct dcb_output *,
                      struct nvkm_output **);
 int gf119_sor_dp_lnk_ctl(struct nvkm_output_dp *, int, int, bool);
+int gf119_sor_dp_drv_ctl(struct nvkm_output_dp *, int, int, int, int);
 
-int  gm200_sor_dp_new(struct nvkm_disp *, int, struct dcb_output *,
-                      struct nvkm_output **);
+int gm107_sor_dp_new(struct nvkm_disp *, int, struct dcb_output *,
+                     struct nvkm_output **);
+int gm107_sor_dp_pattern(struct nvkm_output_dp *, int);
+
+int gm200_sor_dp_new(struct nvkm_disp *, int, struct dcb_output *,
+                     struct nvkm_output **);
 #endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c
index b4b41b135643..22706c0a54b5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c
@@ -40,8 +40,7 @@ static int
 gf119_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
 {
         struct nvkm_device *device = outp->base.disp->engine.subdev.device;
-        const u32 loff = gf119_sor_loff(outp);
-        nvkm_mask(device, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern);
+        nvkm_mask(device, 0x61c110, 0x0f0f0f0f, 0x01010101 * pattern);
         return 0;
 }
 
@@ -64,7 +63,7 @@ gf119_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
         return 0;
 }
 
-static int
+int
 gf119_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
                      int ln, int vs, int pe, int pc)
 {
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c
new file mode 100644
index 000000000000..37790b2617c5
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2016 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+#include "nv50.h"
+#include "outpdp.h"
+
+int
+gm107_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
+{
+        struct nvkm_device *device = outp->base.disp->engine.subdev.device;
+        const u32 soff = outp->base.or * 0x800;
+        const u32 data = 0x01010101 * pattern;
+        if (outp->base.info.sorconf.link & 1)
+                nvkm_mask(device, 0x61c110 + soff, 0x0f0f0f0f, data);
+        else
+                nvkm_mask(device, 0x61c12c + soff, 0x0f0f0f0f, data);
+        return 0;
+}
+
+static const struct nvkm_output_dp_func
+gm107_sor_dp_func = {
+        .pattern = gm107_sor_dp_pattern,
+        .lnk_pwr = g94_sor_dp_lnk_pwr,
+        .lnk_ctl = gf119_sor_dp_lnk_ctl,
+        .drv_ctl = gf119_sor_dp_drv_ctl,
+};
+
+int
+gm107_sor_dp_new(struct nvkm_disp *disp, int index,
+                 struct dcb_output *dcbE, struct nvkm_output **poutp)
+{
+        return nvkm_output_dp_new_(&gm107_sor_dp_func, disp, index, dcbE, poutp);
+}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c
index 2cfbef9c344f..c44fa7ea672a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c
@@ -57,19 +57,6 @@ gm200_sor_dp_lane_map(struct nvkm_device *device, u8 lane)
 }
 
 static int
-gm200_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
-{
-        struct nvkm_device *device = outp->base.disp->engine.subdev.device;
-        const u32 soff = gm200_sor_soff(outp);
-        const u32 data = 0x01010101 * pattern;
-        if (outp->base.info.sorconf.link & 1)
-                nvkm_mask(device, 0x61c110 + soff, 0x0f0f0f0f, data);
-        else
-                nvkm_mask(device, 0x61c12c + soff, 0x0f0f0f0f, data);
-        return 0;
-}
-
-static int
 gm200_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
 {
         struct nvkm_device *device = outp->base.disp->engine.subdev.device;
@@ -129,7 +116,7 @@ gm200_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
 
 static const struct nvkm_output_dp_func
 gm200_sor_dp_func = {
-        .pattern = gm200_sor_dp_pattern,
+        .pattern = gm107_sor_dp_pattern,
         .lnk_pwr = gm200_sor_dp_lnk_pwr,
         .lnk_ctl = gf119_sor_dp_lnk_ctl,
         .drv_ctl = gm200_sor_dp_drv_ctl,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
index 9513badb8220..ae9ab5b1ab97 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
@@ -949,22 +949,41 @@ gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc)
 }
 
 static const struct nvkm_enum gf100_mp_warp_error[] = {
-        { 0x00, "NO_ERROR" },
-        { 0x01, "STACK_MISMATCH" },
+        { 0x01, "STACK_ERROR" },
+        { 0x02, "API_STACK_ERROR" },
+        { 0x03, "RET_EMPTY_STACK_ERROR" },
+        { 0x04, "PC_WRAP" },
         { 0x05, "MISALIGNED_PC" },
-        { 0x08, "MISALIGNED_GPR" },
-        { 0x09, "INVALID_OPCODE" },
-        { 0x0d, "GPR_OUT_OF_BOUNDS" },
-        { 0x0e, "MEM_OUT_OF_BOUNDS" },
-        { 0x0f, "UNALIGNED_MEM_ACCESS" },
+        { 0x06, "PC_OVERFLOW" },
+        { 0x07, "MISALIGNED_IMMC_ADDR" },
+        { 0x08, "MISALIGNED_REG" },
+        { 0x09, "ILLEGAL_INSTR_ENCODING" },
+        { 0x0a, "ILLEGAL_SPH_INSTR_COMBO" },
+        { 0x0b, "ILLEGAL_INSTR_PARAM" },
+        { 0x0c, "INVALID_CONST_ADDR" },
+        { 0x0d, "OOR_REG" },
+        { 0x0e, "OOR_ADDR" },
+        { 0x0f, "MISALIGNED_ADDR" },
         { 0x10, "INVALID_ADDR_SPACE" },
-        { 0x11, "INVALID_PARAM" },
+        { 0x11, "ILLEGAL_INSTR_PARAM2" },
+        { 0x12, "INVALID_CONST_ADDR_LDC" },
+        { 0x13, "GEOMETRY_SM_ERROR" },
+        { 0x14, "DIVERGENT" },
+        { 0x15, "WARP_EXIT" },
         {}
 };
 
 static const struct nvkm_bitfield gf100_mp_global_error[] = {
+        { 0x00000001, "SM_TO_SM_FAULT" },
+        { 0x00000002, "L1_ERROR" },
         { 0x00000004, "MULTIPLE_WARP_ERRORS" },
-        { 0x00000008, "OUT_OF_STACK_SPACE" },
+        { 0x00000008, "PHYSICAL_STACK_OVERFLOW" },
+        { 0x00000010, "BPT_INT" },
+        { 0x00000020, "BPT_PAUSE" },
+        { 0x00000040, "SINGLE_STEP_COMPLETE" },
+        { 0x20000000, "ECC_SEC_ERROR" },
+        { 0x40000000, "ECC_DED_ERROR" },
+        { 0x80000000, "TIMEOUT" },
         {}
 };
 
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.c
index a5e92135cd77..9efb1b48cd54 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.c
@@ -141,7 +141,8 @@ nvbios_ocfg_parse(struct nvkm_bios *bios, u16 outp, u8 idx,
 {
         u16 data = nvbios_ocfg_entry(bios, outp, idx, ver, hdr, cnt, len);
         if (data) {
-                info->match     = nvbios_rd16(bios, data + 0x00);
+                info->proto     = nvbios_rd08(bios, data + 0x00);
+                info->flags     = nvbios_rd16(bios, data + 0x01);
                 info->clkcmp[0] = nvbios_rd16(bios, data + 0x02);
                 info->clkcmp[1] = nvbios_rd16(bios, data + 0x04);
         }
@@ -149,12 +150,13 @@ nvbios_ocfg_parse(struct nvkm_bios *bios, u16 outp, u8 idx,
 }
 
 u16
-nvbios_ocfg_match(struct nvkm_bios *bios, u16 outp, u16 type,
+nvbios_ocfg_match(struct nvkm_bios *bios, u16 outp, u8 proto, u8 flags,
                   u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ocfg *info)
 {
         u16 data, idx = 0;
         while ((data = nvbios_ocfg_parse(bios, outp, idx++, ver, hdr, cnt, len, info))) {
-                if (info->match == type)
+                if ((info->proto == proto || info->proto == 0xff) &&
+                    (info->flags == flags))
                         break;
         }
         return data;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c
index 323c79abe468..41bd5d0f7692 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c
@@ -276,6 +276,8 @@ nvkm_iccsense_oneinit(struct nvkm_subdev *subdev)
                 struct pwr_rail_t *r = &stbl.rail[i];
                 struct nvkm_iccsense_rail *rail;
                 struct nvkm_iccsense_sensor *sensor;
+                int (*read)(struct nvkm_iccsense *,
+                            struct nvkm_iccsense_rail *);
 
                 if (!r->mode || r->resistor_mohm == 0)
                         continue;
@@ -284,31 +286,31 @@ nvkm_iccsense_oneinit(struct nvkm_subdev *subdev)
                 if (!sensor)
                         continue;
 
-                rail = kmalloc(sizeof(*rail), GFP_KERNEL);
-                if (!rail)
-                        return -ENOMEM;
-
                 switch (sensor->type) {
                 case NVBIOS_EXTDEV_INA209:
                         if (r->rail != 0)
                                 continue;
-                        rail->read = nvkm_iccsense_ina209_read;
+                        read = nvkm_iccsense_ina209_read;
                         break;
                 case NVBIOS_EXTDEV_INA219:
                         if (r->rail != 0)
                                 continue;
-                        rail->read = nvkm_iccsense_ina219_read;
+                        read = nvkm_iccsense_ina219_read;
                         break;
                 case NVBIOS_EXTDEV_INA3221:
                         if (r->rail >= 3)
                                 continue;
-                        rail->read = nvkm_iccsense_ina3221_read;
+                        read = nvkm_iccsense_ina3221_read;
                         break;
                 default:
                         continue;
                 }
 
+                rail = kmalloc(sizeof(*rail), GFP_KERNEL);
+                if (!rail)
+                        return -ENOMEM;
                 sensor->rail_mask |= 1 << r->rail;
+                rail->read = read;
                 rail->sensor = sensor;
                 rail->idx = r->rail;
                 rail->mohm = r->resistor_mohm;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c
index e292f5679418..389fb13a1998 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c
@@ -69,11 +69,11 @@ gm107_ltc_zbc_clear_depth(struct nvkm_ltc *ltc, int i, const u32 depth)
 }
 
 static void
-gm107_ltc_lts_isr(struct nvkm_ltc *ltc, int c, int s)
+gm107_ltc_intr_lts(struct nvkm_ltc *ltc, int c, int s)
 {
         struct nvkm_subdev *subdev = &ltc->subdev;
         struct nvkm_device *device = subdev->device;
-        u32 base = 0x140000 + (c * 0x2000) + (s * 0x200);
+        u32 base = 0x140400 + (c * 0x2000) + (s * 0x200);
         u32 stat = nvkm_rd32(device, base + 0x00c);
 
         if (stat) {
@@ -92,7 +92,7 @@ gm107_ltc_intr(struct nvkm_ltc *ltc)
         while (mask) {
                 u32 s, c = __ffs(mask);
                 for (s = 0; s < ltc->lts_nr; s++)
-                        gm107_ltc_lts_isr(ltc, c, s);
+                        gm107_ltc_intr_lts(ltc, c, s);
                 mask &= ~(1 << c);
         }
 }
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.c
index 2a29bfd5125a..e18e0dc19ec8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.c
@@ -46,7 +46,7 @@ static const struct nvkm_ltc_func
 gm200_ltc = {
         .oneinit = gm200_ltc_oneinit,
         .init = gm200_ltc_init,
-        .intr = gm107_ltc_intr, /*XXX: not validated */
+        .intr = gm107_ltc_intr,
         .cbc_clear = gm107_ltc_cbc_clear,
         .cbc_wait = gm107_ltc_cbc_wait,
         .zbc = 16,
diff --git a/drivers/gpu/drm/omapdrm/Kconfig b/drivers/gpu/drm/omapdrm/Kconfig
index 73241c4eb7aa..336ad4de9981 100644
--- a/drivers/gpu/drm/omapdrm/Kconfig
+++ b/drivers/gpu/drm/omapdrm/Kconfig
@@ -2,6 +2,7 @@ config DRM_OMAP
         tristate "OMAP DRM"
         depends on DRM
         depends on ARCH_OMAP2PLUS || ARCH_MULTIPLATFORM
+        select OMAP2_DSS
         select DRM_KMS_HELPER
         select DRM_KMS_FB_HELPER
         select FB_SYS_FILLRECT
diff --git a/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c b/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c
index 225fd8d6ab31..667ca4a24ece 100644
--- a/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c
+++ b/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c
@@ -9,6 +9,7 @@
  * the Free Software Foundation.
  */
 
+#include <linux/gpio/consumer.h>
 #include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
diff --git a/drivers/gpu/drm/omapdrm/displays/encoder-opa362.c b/drivers/gpu/drm/omapdrm/displays/encoder-opa362.c
index 8c246c213e06..9594ff7a2b0c 100644
--- a/drivers/gpu/drm/omapdrm/displays/encoder-opa362.c
+++ b/drivers/gpu/drm/omapdrm/displays/encoder-opa362.c
@@ -14,7 +14,7 @@
  * the Free Software Foundation.
  */
 
-#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
diff --git a/drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c b/drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c
index 2fd5602880a7..671806ca7d6a 100644
--- a/drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c
+++ b/drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c
@@ -9,7 +9,7 @@
  * the Free Software Foundation.
  */
 
-#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-dpi.c b/drivers/gpu/drm/omapdrm/displays/panel-dpi.c
index e780fd4f8b46..7c2331be8d15 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-dpi.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-dpi.c
@@ -9,7 +9,7 @@
  * the Free Software Foundation.
  */
 
-#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c b/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c
index 36485c2137ce..2b118071b5a1 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c
@@ -14,7 +14,7 @@
 #include <linux/backlight.h>
 #include <linux/delay.h>
 #include <linux/fb.h>
-#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
 #include <linux/interrupt.h>
 #include <linux/jiffies.h>
 #include <linux/module.h>
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c b/drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c
index 458f77bc473d..ac680e1de603 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c
@@ -15,6 +15,7 @@
 #include <linux/spi/spi.h>
 #include <linux/mutex.h>
 #include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
 
 #include <video/omapdss.h>
 #include <video/omap-panel-data.h>
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c b/drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c
index 780cb263a318..38d2920a95e6 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c
@@ -15,7 +15,7 @@
 #include <linux/delay.h>
 #include <linux/spi/spi.h>
 #include <linux/fb.h>
-#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
 #include <linux/of_gpio.h>
 
 #include <video/omapdss.h>
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c b/drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c
index 529a017602e4..4363fffc87e3 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c
@@ -10,7 +10,7 @@
  */
 
 #include <linux/delay.h>
-#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_gpio.h>
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c b/drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c
index 31efcca801bd..deb416736aad 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c
@@ -29,7 +29,7 @@
 #include <linux/sched.h>
 #include <linux/backlight.h>
 #include <linux/fb.h>
-#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
 #include <linux/of.h>
 #include <linux/of_gpio.h>
 
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c b/drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c
index 03e2beb7b4f0..d93175b03a12 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c
@@ -14,7 +14,7 @@
 #include <linux/delay.h>
 #include <linux/spi/spi.h>
 #include <linux/regulator/consumer.h>
-#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/of_gpio.h>
diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c
index 8730646a0cbb..56c43f355ce3 100644
--- a/drivers/gpu/drm/omapdrm/dss/dsi.c
+++ b/drivers/gpu/drm/omapdrm/dss/dsi.c
@@ -1167,7 +1167,6 @@ static int dsi_regulator_init(struct platform_device *dsidev)
 {
         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
         struct regulator *vdds_dsi;
-        int r;
 
         if (dsi->vdds_dsi_reg != NULL)
                 return 0;
@@ -1180,15 +1179,6 @@ static int dsi_regulator_init(struct platform_device *dsidev)
                 return PTR_ERR(vdds_dsi);
         }
 
-        if (regulator_can_change_voltage(vdds_dsi)) {
-                r = regulator_set_voltage(vdds_dsi, 1800000, 1800000);
-                if (r) {
-                        devm_regulator_put(vdds_dsi);
-                        DSSERR("can't set the DSI regulator voltage\n");
-                        return r;
-                }
-        }
-
         dsi->vdds_dsi_reg = vdds_dsi;
 
         return 0;
diff --git a/drivers/gpu/drm/omapdrm/dss/dss.c b/drivers/gpu/drm/omapdrm/dss/dss.c
index f95ff319e68e..3303cfad4838 100644
--- a/drivers/gpu/drm/omapdrm/dss/dss.c
+++ b/drivers/gpu/drm/omapdrm/dss/dss.c
@@ -30,6 +30,7 @@
 #include <linux/delay.h>
 #include <linux/seq_file.h>
 #include <linux/clk.h>
+#include <linux/pinctrl/consumer.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/gfp.h>
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4.c b/drivers/gpu/drm/omapdrm/dss/hdmi4.c
index f892ae157ff3..4d46cdf7a037 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi4.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4.c
@@ -33,6 +33,7 @@
 #include <linux/gpio.h>
 #include <linux/regulator/consumer.h>
 #include <linux/component.h>
+#include <linux/of.h>
 #include <video/omapdss.h>
 #include <sound/omap-hdmi-audio.h>
 
@@ -100,7 +101,6 @@ static irqreturn_t hdmi_irq_handler(int irq, void *data)
 
 static int hdmi_init_regulator(void)
 {
-        int r;
         struct regulator *reg;
 
         if (hdmi.vdda_reg != NULL)
@@ -114,15 +114,6 @@ static int hdmi_init_regulator(void)
                 return PTR_ERR(reg);
         }
 
-        if (regulator_can_change_voltage(reg)) {
-                r = regulator_set_voltage(reg, 1800000, 1800000);
-                if (r) {
-                        devm_regulator_put(reg);
-                        DSSWARN("can't set the regulator voltage\n");
-                        return r;
-                }
-        }
-
         hdmi.vdda_reg = reg;
 
         return 0;
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
index fa72e735dad2..ef3afe99e487 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
@@ -211,7 +211,7 @@ static void hdmi_core_init(struct hdmi_core_video_config *video_cfg)
 static void hdmi_core_powerdown_disable(struct hdmi_core_data *core)
 {
         DSSDBG("Enter hdmi_core_powerdown_disable\n");
-        REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x0, 0, 0);
+        REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x1, 0, 0);
 }
 
 static void hdmi_core_swreset_release(struct hdmi_core_data *core)
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5.c b/drivers/gpu/drm/omapdrm/dss/hdmi5.c
index a43f7b10e113..9255c0e1e4a7 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi5.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi5.c
@@ -38,6 +38,7 @@
 #include <linux/gpio.h>
 #include <linux/regulator/consumer.h>
 #include <linux/component.h>
+#include <linux/of.h>
 #include <video/omapdss.h>
 #include <sound/omap-hdmi-audio.h>
 
@@ -119,7 +120,6 @@ static irqreturn_t hdmi_irq_handler(int irq, void *data)
 
 static int hdmi_init_regulator(void)
 {
-        int r;
         struct regulator *reg;
 
         if (hdmi.vdda_reg != NULL)
@@ -131,15 +131,6 @@ static int hdmi_init_regulator(void)
                 return PTR_ERR(reg);
         }
 
-        if (regulator_can_change_voltage(reg)) {
-                r = regulator_set_voltage(reg, 1800000, 1800000);
-                if (r) {
-                        devm_regulator_put(reg);
-                        DSSWARN("can't set the regulator voltage\n");
-                        return r;
-                }
-        }
-
         hdmi.vdda_reg = reg;
 
         return 0;
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
index 6a397520cae5..8ab2093daa12 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
@@ -51,8 +51,8 @@ static void hdmi_core_ddc_init(struct hdmi_core_data *core)
 {
         void __iomem *base = core->base;
         const unsigned long long iclk = 266000000;      /* DSS L3 ICLK */
-        const unsigned ss_scl_high = 4000;              /* ns */
-        const unsigned ss_scl_low = 4700;               /* ns */
+        const unsigned ss_scl_high = 4600;              /* ns */
+        const unsigned ss_scl_low = 5400;               /* ns */
         const unsigned fs_scl_high = 600;               /* ns */
         const unsigned fs_scl_low = 1300;               /* ns */
         const unsigned sda_hold = 1000;                 /* ns */
@@ -458,7 +458,7 @@ static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core,
 
         c = (ptr[1] >> 6) & 0x3;
         m = (ptr[1] >> 4) & 0x3;
-        r = (ptr[1] >> 0) & 0x3;
+        r = (ptr[1] >> 0) & 0xf;
 
         itc = (ptr[2] >> 7) & 0x1;
         ec = (ptr[2] >> 4) & 0x7;
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_phy.c b/drivers/gpu/drm/omapdrm/dss/hdmi_phy.c
index 1f5d19c119ce..f98b750fc499 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi_phy.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi_phy.c
@@ -13,6 +13,7 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
+#include <linux/seq_file.h>
 #include <video/omapdss.h>
 
 #include "dss.h"
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_pll.c b/drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
index 06e23a7c432c..f1015e8b8267 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
@@ -16,6 +16,7 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
+#include <linux/seq_file.h>
 
 #include <video/omapdss.h>
 
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
index 13442b9052d1..055f62fca5dc 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
@@ -14,6 +14,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/seq_file.h>
 #include <video/omapdss.h>
 
 #include "dss.h"
diff --git a/drivers/gpu/drm/omapdrm/omap_debugfs.c b/drivers/gpu/drm/omapdrm/omap_debugfs.c
index 6f5fc14fc015..479bf24050f8 100644
--- a/drivers/gpu/drm/omapdrm/omap_debugfs.c
+++ b/drivers/gpu/drm/omapdrm/omap_debugfs.c
@@ -17,6 +17,8 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <linux/seq_file.h>
+
 #include <drm/drm_crtc.h>
 #include <drm/drm_fb_helper.h>
 
diff --git a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
index de275a5be1db..4ceed7a9762f 100644
--- a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
+++ b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
@@ -27,6 +27,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h> /* platform_device() */
 #include <linux/sched.h>
+#include <linux/seq_file.h>
 #include <linux/slab.h>
 #include <linux/time.h>
 #include <linux/vmalloc.h>
diff --git a/drivers/gpu/drm/omapdrm/omap_fb.c b/drivers/gpu/drm/omapdrm/omap_fb.c
index 94ec06d3d737..f84570d1636c 100644
--- a/drivers/gpu/drm/omapdrm/omap_fb.c
+++ b/drivers/gpu/drm/omapdrm/omap_fb.c
@@ -17,6 +17,8 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <linux/seq_file.h>
+
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
 
diff --git a/drivers/gpu/drm/omapdrm/omap_gem.c b/drivers/gpu/drm/omapdrm/omap_gem.c
index b97afc281778..03698b6c806c 100644
--- a/drivers/gpu/drm/omapdrm/omap_gem.c
+++ b/drivers/gpu/drm/omapdrm/omap_gem.c
@@ -17,6 +17,7 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <linux/seq_file.h>
 #include <linux/shmem_fs.h>
 #include <linux/spinlock.h>
 #include <linux/pfn_t.h>
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 2e216e2ea78c..259cd6e6d71c 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -589,7 +589,8 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
                 /* use frac fb div on RS780/RS880 */
-                if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
+                if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
+                    && !radeon_crtc->ss_enabled)
                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
                 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
@@ -626,7 +627,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                         if (radeon_crtc->ss.refdiv) {
                                 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
                                 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
-                                if (ASIC_IS_AVIVO(rdev))
+                                if (rdev->family >= CHIP_RV770)
                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
                         }
                 }
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index e721e6b2766e..21c44b2293bc 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -630,6 +630,23 @@ void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 /*
  * GPU helpers function.
  */
+
+/**
+ * radeon_device_is_virtual - check if we are running is a virtual environment
+ *
+ * Check if the asic has been passed through to a VM (all asics).
+ * Used at driver startup.
+ * Returns true if virtual or false if not.
+ */
+static bool radeon_device_is_virtual(void)
+{
+#ifdef CONFIG_X86
+        return boot_cpu_has(X86_FEATURE_HYPERVISOR);
+#else
+        return false;
+#endif
+}
+
 /**
  * radeon_card_posted - check if the hw has already been initialized
  *
@@ -643,6 +660,10 @@ bool radeon_card_posted(struct radeon_device *rdev)
 {
         uint32_t reg;
 
+        /* for pass through, always force asic_init */
+        if (radeon_device_is_virtual())
+                return false;
+
         /* required for EFI mode on macbook2,1 which uses an r5xx asic */
         if (efi_enabled(EFI_BOOT) &&
             (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
@@ -1631,7 +1652,7 @@ int radeon_suspend_kms(struct drm_device *dev, bool suspend,
         radeon_agp_suspend(rdev);
 
         pci_save_state(dev->pdev);
-        if (freeze && rdev->family >= CHIP_R600) {
+        if (freeze && rdev->family >= CHIP_CEDAR) {
                 rdev->asic->asic_reset(rdev, true);
                 pci_restore_state(dev->pdev);
         } else if (suspend) {
diff --git a/drivers/gpu/drm/sti/sti_crtc.c b/drivers/gpu/drm/sti/sti_crtc.c
index 505620c7c2c8..e04deedabd4a 100644
--- a/drivers/gpu/drm/sti/sti_crtc.c
+++ b/drivers/gpu/drm/sti/sti_crtc.c
@@ -51,15 +51,6 @@ static void sti_crtc_disabling(struct drm_crtc *crtc)
         mixer->status = STI_MIXER_DISABLING;
 }
 
-static bool sti_crtc_mode_fixup(struct drm_crtc *crtc,
-                                const struct drm_display_mode *mode,
-                                struct drm_display_mode *adjusted_mode)
-{
-        /* accept the provided drm_display_mode, do not fix it up */
-        drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
-        return true;
-}
-
 static int
 sti_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode)
 {
@@ -230,7 +221,6 @@ static void sti_crtc_atomic_flush(struct drm_crtc *crtc,
 static const struct drm_crtc_helper_funcs sti_crtc_helper_funcs = {
         .enable = sti_crtc_enable,
         .disable = sti_crtc_disabling,
-        .mode_fixup = sti_crtc_mode_fixup,
         .mode_set = drm_helper_crtc_mode_set,
         .mode_set_nofb = sti_crtc_mode_set_nofb,
         .mode_set_base = drm_helper_crtc_mode_set_base,
diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
index 99510e64e91a..a4b357db8856 100644
--- a/drivers/gpu/drm/sun4i/Kconfig
+++ b/drivers/gpu/drm/sun4i/Kconfig
@@ -1,6 +1,6 @@
 config DRM_SUN4I
         tristate "DRM Support for Allwinner A10 Display Engine"
-        depends on DRM && ARM
+        depends on DRM && ARM && COMMON_CLK
         depends on ARCH_SUNXI || COMPILE_TEST
         select DRM_GEM_CMA_HELPER
         select DRM_KMS_HELPER
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c
index f7a15c1a93bf..3ab560450a82 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -190,7 +190,7 @@ int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
         /* Get the physical address of the buffer in memory */
         gem = drm_fb_cma_get_gem_obj(fb, 0);
 
-        DRM_DEBUG_DRIVER("Using GEM @ 0x%x\n", gem->paddr);
+        DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr);
 
         /* Compute the start of the displayed memory */
         bpp = drm_format_plane_cpp(fb->pixel_format, 0);
@@ -198,7 +198,7 @@ int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
         paddr += (state->src_x >> 16) * bpp;
         paddr += (state->src_y >> 16) * fb->pitches[0];
 
-        DRM_DEBUG_DRIVER("Setting buffer address to 0x%x\n", paddr);
+        DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
 
         /* Write the 32 lower bits of the address (in bits) */
         lo_paddr = paddr << 3;
diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
index 3ff668cb463c..5b3463197c48 100644
--- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c
+++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
@@ -72,14 +72,40 @@ static unsigned long sun4i_dclk_recalc_rate(struct clk_hw *hw,
 static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
                                   unsigned long *parent_rate)
 {
-        return *parent_rate / DIV_ROUND_CLOSEST(*parent_rate, rate);
+        unsigned long best_parent = 0;
+        u8 best_div = 1;
+        int i;
+
+        for (i = 6; i < 127; i++) {
+                unsigned long ideal = rate * i;
+                unsigned long rounded;
+
+                rounded = clk_hw_round_rate(clk_hw_get_parent(hw),
+                                            ideal);
+
+                if (rounded == ideal) {
+                        best_parent = rounded;
+                        best_div = i;
+                        goto out;
+                }
+
+                if ((rounded < ideal) && (rounded > best_parent)) {
+                        best_parent = rounded;
+                        best_div = i;
+                }
+        }
+
+out:
+        *parent_rate = best_parent;
+
+        return best_parent / best_div;
 }
 
 static int sun4i_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
                                unsigned long parent_rate)
 {
         struct sun4i_dclk *dclk = hw_to_dclk(hw);
-        int div = DIV_ROUND_CLOSEST(parent_rate, rate);
+        u8 div = parent_rate / rate;
 
         return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
                                   GENMASK(6, 0), div);
@@ -127,10 +153,14 @@ int sun4i_dclk_create(struct device *dev, struct sun4i_tcon *tcon)
         const char *clk_name, *parent_name;
         struct clk_init_data init;
         struct sun4i_dclk *dclk;
+        int ret;
 
         parent_name = __clk_get_name(tcon->sclk0);
-        of_property_read_string_index(dev->of_node, "clock-output-names", 0,
-                                      &clk_name);
+        ret = of_property_read_string_index(dev->of_node,
+                                            "clock-output-names", 0,
+                                            &clk_name);
+        if (ret)
+                return ret;
 
         dclk = devm_kzalloc(dev, sizeof(*dclk), GFP_KERNEL);
         if (!dclk)
@@ -140,6 +170,7 @@ int sun4i_dclk_create(struct device *dev, struct sun4i_tcon *tcon)
         init.ops = &sun4i_dclk_ops;
         init.parent_names = &parent_name;
         init.num_parents = 1;
+        init.flags = CLK_SET_RATE_PARENT;
 
         dclk->regmap = tcon->regs;
         dclk->hw.init = &init;
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 76e922bb60e5..257d2b4f3645 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -24,34 +24,6 @@
 #include "sun4i_layer.h"
 #include "sun4i_tcon.h"
 
-static int sun4i_drv_connector_plug_all(struct drm_device *drm)
-{
-        struct drm_connector *connector, *failed;
-        int ret;
-
-        mutex_lock(&drm->mode_config.mutex);
-        list_for_each_entry(connector, &drm->mode_config.connector_list, head) {
-                ret = drm_connector_register(connector);
-                if (ret) {
-                        failed = connector;
-                        goto err;
-                }
-        }
-        mutex_unlock(&drm->mode_config.mutex);
-        return 0;
-
-err:
-        list_for_each_entry(connector, &drm->mode_config.connector_list, head) {
-                if (failed == connector)
-                        break;
-
-                drm_connector_unregister(connector);
-        }
-        mutex_unlock(&drm->mode_config.mutex);
-
-        return ret;
-}
-
 static int sun4i_drv_enable_vblank(struct drm_device *drm, unsigned int pipe)
 {
         struct sun4i_drv *drv = drm->dev_private;
@@ -125,6 +97,22 @@ static struct drm_driver sun4i_drv_driver = {
         .disable_vblank         = sun4i_drv_disable_vblank,
 };
 
+static void sun4i_remove_framebuffers(void)
+{
+        struct apertures_struct *ap;
+
+        ap = alloc_apertures(1);
+        if (!ap)
+                return;
+
+        /* The framebuffer can be located anywhere in RAM */
+        ap->ranges[0].base = 0;
+        ap->ranges[0].size = ~0;
+
+        remove_conflicting_framebuffers(ap, "sun4i-drm-fb", false);
+        kfree(ap);
+}
+
 static int sun4i_drv_bind(struct device *dev)
 {
         struct drm_device *drm;
@@ -172,6 +160,9 @@ static int sun4i_drv_bind(struct device *dev)
         }
         drm->irq_enabled = true;
 
+        /* Remove early framebuffers (ie. simplefb) */
+        sun4i_remove_framebuffers();
+
         /* Create our framebuffer */
         drv->fbdev = sun4i_framebuffer_init(drm);
         if (IS_ERR(drv->fbdev)) {
@@ -187,7 +178,7 @@ static int sun4i_drv_bind(struct device *dev)
         if (ret)
                 goto free_drm;
 
-        ret = sun4i_drv_connector_plug_all(drm);
+        ret = drm_connector_register_all(drm);
         if (ret)
                 goto unregister_drm;
 
@@ -204,6 +195,7 @@ static void sun4i_drv_unbind(struct device *dev)
 {
         struct drm_device *drm = dev_get_drvdata(dev);
 
+        drm_connector_unregister_all(drm);
         drm_dev_unregister(drm);
         drm_kms_helper_poll_fini(drm);
         sun4i_framebuffer_free(drm);
diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c b/drivers/gpu/drm/sun4i/sun4i_rgb.c
index ab6494818050..aaffe9e64ffb 100644
--- a/drivers/gpu/drm/sun4i/sun4i_rgb.c
+++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
@@ -54,8 +54,13 @@ static int sun4i_rgb_get_modes(struct drm_connector *connector)
 static int sun4i_rgb_mode_valid(struct drm_connector *connector,
                                 struct drm_display_mode *mode)
 {
+        struct sun4i_rgb *rgb = drm_connector_to_sun4i_rgb(connector);
+        struct sun4i_drv *drv = rgb->drv;
+        struct sun4i_tcon *tcon = drv->tcon;
         u32 hsync = mode->hsync_end - mode->hsync_start;
         u32 vsync = mode->vsync_end - mode->vsync_start;
+        unsigned long rate = mode->clock * 1000;
+        long rounded_rate;
 
         DRM_DEBUG_DRIVER("Validating modes...\n");
 
@@ -87,6 +92,15 @@ static int sun4i_rgb_mode_valid(struct drm_connector *connector,
 
         DRM_DEBUG_DRIVER("Vertical parameters OK\n");
 
+        rounded_rate = clk_round_rate(tcon->dclk, rate);
+        if (rounded_rate < rate)
+                return MODE_CLOCK_LOW;
+
+        if (rounded_rate > rate)
+                return MODE_CLOCK_HIGH;
+
+        DRM_DEBUG_DRIVER("Clock rate OK\n");
+
         return MODE_OK;
 }
 
@@ -203,7 +217,7 @@ int sun4i_rgb_init(struct drm_device *drm)
         int ret;
 
         /* If we don't have a panel, there's no point in going on */
-        if (!tcon->panel)
+        if (IS_ERR(tcon->panel))
                 return -ENODEV;
 
         rgb = devm_kzalloc(drm->dev, sizeof(*rgb), GFP_KERNEL);
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 9f19b0e08560..652385f09735 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -425,11 +425,11 @@ static struct drm_panel *sun4i_tcon_find_panel(struct device_node *node)
 
         remote = of_graph_get_remote_port_parent(end_node);
         if (!remote) {
-                DRM_DEBUG_DRIVER("Enable to parse remote node\n");
+                DRM_DEBUG_DRIVER("Unable to parse remote node\n");
                 return ERR_PTR(-EINVAL);
         }
 
-        return of_drm_find_panel(remote);
+        return of_drm_find_panel(remote) ?: ERR_PTR(-EPROBE_DEFER);
 }
 
 static int sun4i_tcon_bind(struct device *dev, struct device *master,
@@ -490,7 +490,11 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
                 return 0;
         }
 
-        return sun4i_rgb_init(drm);
+        ret = sun4i_rgb_init(drm);
+        if (ret < 0)
+                goto err_free_clocks;
+
+        return 0;
 
 err_free_clocks:
         sun4i_tcon_free_clocks(tcon);
@@ -522,12 +526,13 @@ static int sun4i_tcon_probe(struct platform_device *pdev)
          * Defer the probe.
          */
         panel = sun4i_tcon_find_panel(node);
-        if (IS_ERR(panel)) {
-                /*
-                 * If we don't have a panel endpoint, just go on
-                 */
-                if (PTR_ERR(panel) != -ENODEV)
-                        return -EPROBE_DEFER;
+
+        /*
+         * If we don't have a panel endpoint, just go on
+         */
+        if (PTR_ERR(panel) == -EPROBE_DEFER) {
+                DRM_DEBUG_DRIVER("Still waiting for our panel. Deferring...\n");
+                return -EPROBE_DEFER;
         }
 
         return component_add(&pdev->dev, &sun4i_tcon_ops);
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 904d0754ad78..0f18b76c7906 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -456,14 +456,6 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
 
         WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
 
-        HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
-                  vc4_state->mm.start);
-
-        if (debug_dump_regs) {
-                DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
-                vc4_hvs_dump_state(dev);
-        }
-
         if (crtc->state->event) {
                 unsigned long flags;
 
@@ -473,8 +465,20 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
 
                 spin_lock_irqsave(&dev->event_lock, flags);
                 vc4_crtc->event = crtc->state->event;
-                spin_unlock_irqrestore(&dev->event_lock, flags);
                 crtc->state->event = NULL;
+
+                HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
+                          vc4_state->mm.start);
+
+                spin_unlock_irqrestore(&dev->event_lock, flags);
+        } else {
+                HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
+                          vc4_state->mm.start);
+        }
+
+        if (debug_dump_regs) {
+                DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
+                vc4_hvs_dump_state(dev);
         }
 }
 
@@ -500,12 +504,17 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 {
         struct drm_crtc *crtc = &vc4_crtc->base;
         struct drm_device *dev = crtc->dev;
+        struct vc4_dev *vc4 = to_vc4_dev(dev);
+        struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
+        u32 chan = vc4_crtc->channel;
         unsigned long flags;
 
         spin_lock_irqsave(&dev->event_lock, flags);
-        if (vc4_crtc->event) {
+        if (vc4_crtc->event &&
+            (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
                 vc4_crtc->event = NULL;
+                drm_crtc_vblank_put(crtc);
         }
         spin_unlock_irqrestore(&dev->event_lock, flags);
 }
@@ -556,6 +565,7 @@ vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
                 spin_unlock_irqrestore(&dev->event_lock, flags);
         }
 
+        drm_crtc_vblank_put(crtc);
         drm_framebuffer_unreference(flip_state->fb);
         kfree(flip_state);
 
@@ -598,6 +608,8 @@ static int vc4_async_page_flip(struct drm_crtc *crtc,
                 return ret;
         }
 
+        WARN_ON(drm_crtc_vblank_get(crtc) != 0);
+
         /* Immediately update the plane's legacy fb pointer, so that later
          * modeset prep sees the state that will be present when the semaphore
          * is released.
diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
index 3446ece21b4a..250ed7e3754c 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.c
+++ b/drivers/gpu/drm/vc4/vc4_drv.c
@@ -66,12 +66,12 @@ static const struct file_operations vc4_drm_fops = {
 };
 
 static const struct drm_ioctl_desc vc4_drm_ioctls[] = {
-        DRM_IOCTL_DEF_DRV(VC4_SUBMIT_CL, vc4_submit_cl_ioctl, 0),
-        DRM_IOCTL_DEF_DRV(VC4_WAIT_SEQNO, vc4_wait_seqno_ioctl, 0),
-        DRM_IOCTL_DEF_DRV(VC4_WAIT_BO, vc4_wait_bo_ioctl, 0),
-        DRM_IOCTL_DEF_DRV(VC4_CREATE_BO, vc4_create_bo_ioctl, 0),
-        DRM_IOCTL_DEF_DRV(VC4_MMAP_BO, vc4_mmap_bo_ioctl, 0),
-        DRM_IOCTL_DEF_DRV(VC4_CREATE_SHADER_BO, vc4_create_shader_bo_ioctl, 0),
+        DRM_IOCTL_DEF_DRV(VC4_SUBMIT_CL, vc4_submit_cl_ioctl, DRM_RENDER_ALLOW),
+        DRM_IOCTL_DEF_DRV(VC4_WAIT_SEQNO, vc4_wait_seqno_ioctl, DRM_RENDER_ALLOW),
+        DRM_IOCTL_DEF_DRV(VC4_WAIT_BO, vc4_wait_bo_ioctl, DRM_RENDER_ALLOW),
+        DRM_IOCTL_DEF_DRV(VC4_CREATE_BO, vc4_create_bo_ioctl, DRM_RENDER_ALLOW),
+        DRM_IOCTL_DEF_DRV(VC4_MMAP_BO, vc4_mmap_bo_ioctl, DRM_RENDER_ALLOW),
+        DRM_IOCTL_DEF_DRV(VC4_CREATE_SHADER_BO, vc4_create_shader_bo_ioctl, DRM_RENDER_ALLOW),
         DRM_IOCTL_DEF_DRV(VC4_GET_HANG_STATE, vc4_get_hang_state_ioctl,
                           DRM_ROOT_ONLY),
 };
@@ -91,7 +91,7 @@ static struct drm_driver vc4_drm_driver = {
 
         .enable_vblank = vc4_enable_vblank,
         .disable_vblank = vc4_disable_vblank,
-        .get_vblank_counter = drm_vblank_count,
+        .get_vblank_counter = drm_vblank_no_hw_counter,
 
 #if defined(CONFIG_DEBUG_FS)
         .debugfs_init = vc4_debugfs_init,
diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index cb37751bc99f..861a623bc185 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -117,10 +117,18 @@ static int vc4_atomic_commit(struct drm_device *dev,
                 return -ENOMEM;
 
         /* Make sure that any outstanding modesets have finished. */
-        ret = down_interruptible(&vc4->async_modeset);
-        if (ret) {
-                kfree(c);
-                return ret;
+        if (nonblock) {
+                ret = down_trylock(&vc4->async_modeset);
+                if (ret) {
+                        kfree(c);
+                        return -EBUSY;
+                }
+        } else {
+                ret = down_interruptible(&vc4->async_modeset);
+                if (ret) {
+                        kfree(c);
+                        return ret;
+                }
         }
 
         ret = drm_atomic_helper_prepare_planes(dev, state);
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index 6163b95c5411..f99eece4cc97 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -341,6 +341,10 @@
 #define SCALER_DISPLACT0                        0x00000030
 #define SCALER_DISPLACT1                        0x00000034
 #define SCALER_DISPLACT2                        0x00000038
+#define SCALER_DISPLACTX(x)                     (SCALER_DISPLACT0 +     \
+                                                 (x) * (SCALER_DISPLACT1 - \
+                                                        SCALER_DISPLACT0))
+
 #define SCALER_DISPCTRL0                        0x00000040
 # define SCALER_DISPCTRLX_ENABLE                BIT(31)
 # define SCALER_DISPCTRLX_RESET                 BIT(30)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c b/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
index 6de283c8fa3e..f0374f9b56ca 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
@@ -28,6 +28,7 @@
 #include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
+#include <linux/frame.h>
 #include <asm/hypervisor.h>
 #include "drmP.h"
 #include "vmwgfx_msg.h"
@@ -194,7 +195,7 @@ static int vmw_send_msg(struct rpc_channel *channel, const char *msg)
 
         return -EINVAL;
 }
-
+STACK_FRAME_NON_STANDARD(vmw_send_msg);
 
 
 /**
@@ -304,6 +305,7 @@ static int vmw_recv_msg(struct rpc_channel *channel, void **msg,
 
         return 0;
 }
+STACK_FRAME_NON_STANDARD(vmw_recv_msg);
 
 
 /**