diff options
Diffstat (limited to 'drivers/gpu/drm')
56 files changed, 716 insertions, 811 deletions
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 910ff8ab9c9c..d8135adb2238 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | |||
@@ -645,6 +645,7 @@ static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm, | |||
645 | pr_debug(" sdma queue id: %d\n", q->properties.sdma_queue_id); | 645 | pr_debug(" sdma queue id: %d\n", q->properties.sdma_queue_id); |
646 | pr_debug(" sdma engine id: %d\n", q->properties.sdma_engine_id); | 646 | pr_debug(" sdma engine id: %d\n", q->properties.sdma_engine_id); |
647 | 647 | ||
648 | init_sdma_vm(dqm, q, qpd); | ||
648 | retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj, | 649 | retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj, |
649 | &q->gart_mqd_addr, &q->properties); | 650 | &q->gart_mqd_addr, &q->properties); |
650 | if (retval != 0) { | 651 | if (retval != 0) { |
@@ -652,7 +653,14 @@ static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm, | |||
652 | return retval; | 653 | return retval; |
653 | } | 654 | } |
654 | 655 | ||
655 | init_sdma_vm(dqm, q, qpd); | 656 | retval = mqd->load_mqd(mqd, q->mqd, 0, |
657 | 0, NULL); | ||
658 | if (retval != 0) { | ||
659 | deallocate_sdma_queue(dqm, q->sdma_id); | ||
660 | mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj); | ||
661 | return retval; | ||
662 | } | ||
663 | |||
656 | return 0; | 664 | return 0; |
657 | } | 665 | } |
658 | 666 | ||
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c index e415a2a9207e..c7d298e62c96 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | |||
@@ -44,7 +44,7 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev, | |||
44 | BUG_ON(!kq || !dev); | 44 | BUG_ON(!kq || !dev); |
45 | BUG_ON(type != KFD_QUEUE_TYPE_DIQ && type != KFD_QUEUE_TYPE_HIQ); | 45 | BUG_ON(type != KFD_QUEUE_TYPE_DIQ && type != KFD_QUEUE_TYPE_HIQ); |
46 | 46 | ||
47 | pr_debug("kfd: In func %s initializing queue type %d size %d\n", | 47 | pr_debug("amdkfd: In func %s initializing queue type %d size %d\n", |
48 | __func__, KFD_QUEUE_TYPE_HIQ, queue_size); | 48 | __func__, KFD_QUEUE_TYPE_HIQ, queue_size); |
49 | 49 | ||
50 | nop.opcode = IT_NOP; | 50 | nop.opcode = IT_NOP; |
@@ -69,12 +69,16 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev, | |||
69 | 69 | ||
70 | prop.doorbell_ptr = kfd_get_kernel_doorbell(dev, &prop.doorbell_off); | 70 | prop.doorbell_ptr = kfd_get_kernel_doorbell(dev, &prop.doorbell_off); |
71 | 71 | ||
72 | if (prop.doorbell_ptr == NULL) | 72 | if (prop.doorbell_ptr == NULL) { |
73 | pr_err("amdkfd: error init doorbell"); | ||
73 | goto err_get_kernel_doorbell; | 74 | goto err_get_kernel_doorbell; |
75 | } | ||
74 | 76 | ||
75 | retval = kfd_gtt_sa_allocate(dev, queue_size, &kq->pq); | 77 | retval = kfd_gtt_sa_allocate(dev, queue_size, &kq->pq); |
76 | if (retval != 0) | 78 | if (retval != 0) { |
79 | pr_err("amdkfd: error init pq queues size (%d)\n", queue_size); | ||
77 | goto err_pq_allocate_vidmem; | 80 | goto err_pq_allocate_vidmem; |
81 | } | ||
78 | 82 | ||
79 | kq->pq_kernel_addr = kq->pq->cpu_ptr; | 83 | kq->pq_kernel_addr = kq->pq->cpu_ptr; |
80 | kq->pq_gpu_addr = kq->pq->gpu_addr; | 84 | kq->pq_gpu_addr = kq->pq->gpu_addr; |
@@ -165,10 +169,8 @@ err_rptr_allocate_vidmem: | |||
165 | err_eop_allocate_vidmem: | 169 | err_eop_allocate_vidmem: |
166 | kfd_gtt_sa_free(dev, kq->pq); | 170 | kfd_gtt_sa_free(dev, kq->pq); |
167 | err_pq_allocate_vidmem: | 171 | err_pq_allocate_vidmem: |
168 | pr_err("kfd: error init pq\n"); | ||
169 | kfd_release_kernel_doorbell(dev, prop.doorbell_ptr); | 172 | kfd_release_kernel_doorbell(dev, prop.doorbell_ptr); |
170 | err_get_kernel_doorbell: | 173 | err_get_kernel_doorbell: |
171 | pr_err("kfd: error init doorbell"); | ||
172 | return false; | 174 | return false; |
173 | 175 | ||
174 | } | 176 | } |
@@ -187,6 +189,8 @@ static void uninitialize(struct kernel_queue *kq) | |||
187 | else if (kq->queue->properties.type == KFD_QUEUE_TYPE_DIQ) | 189 | else if (kq->queue->properties.type == KFD_QUEUE_TYPE_DIQ) |
188 | kfd_gtt_sa_free(kq->dev, kq->fence_mem_obj); | 190 | kfd_gtt_sa_free(kq->dev, kq->fence_mem_obj); |
189 | 191 | ||
192 | kq->mqd->uninit_mqd(kq->mqd, kq->queue->mqd, kq->queue->mqd_mem_obj); | ||
193 | |||
190 | kfd_gtt_sa_free(kq->dev, kq->rptr_mem); | 194 | kfd_gtt_sa_free(kq->dev, kq->rptr_mem); |
191 | kfd_gtt_sa_free(kq->dev, kq->wptr_mem); | 195 | kfd_gtt_sa_free(kq->dev, kq->wptr_mem); |
192 | kq->ops_asic_specific.uninitialize(kq); | 196 | kq->ops_asic_specific.uninitialize(kq); |
@@ -211,7 +215,7 @@ static int acquire_packet_buffer(struct kernel_queue *kq, | |||
211 | queue_address = (unsigned int *)kq->pq_kernel_addr; | 215 | queue_address = (unsigned int *)kq->pq_kernel_addr; |
212 | queue_size_dwords = kq->queue->properties.queue_size / sizeof(uint32_t); | 216 | queue_size_dwords = kq->queue->properties.queue_size / sizeof(uint32_t); |
213 | 217 | ||
214 | pr_debug("kfd: In func %s\nrptr: %d\nwptr: %d\nqueue_address 0x%p\n", | 218 | pr_debug("amdkfd: In func %s\nrptr: %d\nwptr: %d\nqueue_address 0x%p\n", |
215 | __func__, rptr, wptr, queue_address); | 219 | __func__, rptr, wptr, queue_address); |
216 | 220 | ||
217 | available_size = (rptr - 1 - wptr + queue_size_dwords) % | 221 | available_size = (rptr - 1 - wptr + queue_size_dwords) % |
@@ -296,7 +300,7 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev, | |||
296 | } | 300 | } |
297 | 301 | ||
298 | if (kq->ops.initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE) == false) { | 302 | if (kq->ops.initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE) == false) { |
299 | pr_err("kfd: failed to init kernel queue\n"); | 303 | pr_err("amdkfd: failed to init kernel queue\n"); |
300 | kfree(kq); | 304 | kfree(kq); |
301 | return NULL; | 305 | return NULL; |
302 | } | 306 | } |
@@ -319,7 +323,7 @@ static __attribute__((unused)) void test_kq(struct kfd_dev *dev) | |||
319 | 323 | ||
320 | BUG_ON(!dev); | 324 | BUG_ON(!dev); |
321 | 325 | ||
322 | pr_err("kfd: starting kernel queue test\n"); | 326 | pr_err("amdkfd: starting kernel queue test\n"); |
323 | 327 | ||
324 | kq = kernel_queue_init(dev, KFD_QUEUE_TYPE_HIQ); | 328 | kq = kernel_queue_init(dev, KFD_QUEUE_TYPE_HIQ); |
325 | BUG_ON(!kq); | 329 | BUG_ON(!kq); |
@@ -330,7 +334,7 @@ static __attribute__((unused)) void test_kq(struct kfd_dev *dev) | |||
330 | buffer[i] = kq->nop_packet; | 334 | buffer[i] = kq->nop_packet; |
331 | kq->ops.submit_packet(kq); | 335 | kq->ops.submit_packet(kq); |
332 | 336 | ||
333 | pr_err("kfd: ending kernel queue test\n"); | 337 | pr_err("amdkfd: ending kernel queue test\n"); |
334 | } | 338 | } |
335 | 339 | ||
336 | 340 | ||
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 6b6b07ff720b..679b10e34fb5 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c | |||
@@ -43,9 +43,10 @@ | |||
43 | #include "drm_crtc_internal.h" | 43 | #include "drm_crtc_internal.h" |
44 | #include "drm_internal.h" | 44 | #include "drm_internal.h" |
45 | 45 | ||
46 | static struct drm_framebuffer *add_framebuffer_internal(struct drm_device *dev, | 46 | static struct drm_framebuffer * |
47 | struct drm_mode_fb_cmd2 *r, | 47 | internal_framebuffer_create(struct drm_device *dev, |
48 | struct drm_file *file_priv); | 48 | struct drm_mode_fb_cmd2 *r, |
49 | struct drm_file *file_priv); | ||
49 | 50 | ||
50 | /* Avoid boilerplate. I'm tired of typing. */ | 51 | /* Avoid boilerplate. I'm tired of typing. */ |
51 | #define DRM_ENUM_NAME_FN(fnname, list) \ | 52 | #define DRM_ENUM_NAME_FN(fnname, list) \ |
@@ -524,17 +525,6 @@ void drm_framebuffer_reference(struct drm_framebuffer *fb) | |||
524 | } | 525 | } |
525 | EXPORT_SYMBOL(drm_framebuffer_reference); | 526 | EXPORT_SYMBOL(drm_framebuffer_reference); |
526 | 527 | ||
527 | static void drm_framebuffer_free_bug(struct kref *kref) | ||
528 | { | ||
529 | BUG(); | ||
530 | } | ||
531 | |||
532 | static void __drm_framebuffer_unreference(struct drm_framebuffer *fb) | ||
533 | { | ||
534 | DRM_DEBUG("%p: FB ID: %d (%d)\n", fb, fb->base.id, atomic_read(&fb->refcount.refcount)); | ||
535 | kref_put(&fb->refcount, drm_framebuffer_free_bug); | ||
536 | } | ||
537 | |||
538 | /** | 528 | /** |
539 | * drm_framebuffer_unregister_private - unregister a private fb from the lookup idr | 529 | * drm_framebuffer_unregister_private - unregister a private fb from the lookup idr |
540 | * @fb: fb to unregister | 530 | * @fb: fb to unregister |
@@ -1319,7 +1309,7 @@ void drm_plane_force_disable(struct drm_plane *plane) | |||
1319 | return; | 1309 | return; |
1320 | } | 1310 | } |
1321 | /* disconnect the plane from the fb and crtc: */ | 1311 | /* disconnect the plane from the fb and crtc: */ |
1322 | __drm_framebuffer_unreference(plane->old_fb); | 1312 | drm_framebuffer_unreference(plane->old_fb); |
1323 | plane->old_fb = NULL; | 1313 | plane->old_fb = NULL; |
1324 | plane->fb = NULL; | 1314 | plane->fb = NULL; |
1325 | plane->crtc = NULL; | 1315 | plane->crtc = NULL; |
@@ -2908,13 +2898,11 @@ static int drm_mode_cursor_universal(struct drm_crtc *crtc, | |||
2908 | */ | 2898 | */ |
2909 | if (req->flags & DRM_MODE_CURSOR_BO) { | 2899 | if (req->flags & DRM_MODE_CURSOR_BO) { |
2910 | if (req->handle) { | 2900 | if (req->handle) { |
2911 | fb = add_framebuffer_internal(dev, &fbreq, file_priv); | 2901 | fb = internal_framebuffer_create(dev, &fbreq, file_priv); |
2912 | if (IS_ERR(fb)) { | 2902 | if (IS_ERR(fb)) { |
2913 | DRM_DEBUG_KMS("failed to wrap cursor buffer in drm framebuffer\n"); | 2903 | DRM_DEBUG_KMS("failed to wrap cursor buffer in drm framebuffer\n"); |
2914 | return PTR_ERR(fb); | 2904 | return PTR_ERR(fb); |
2915 | } | 2905 | } |
2916 | |||
2917 | drm_framebuffer_reference(fb); | ||
2918 | } else { | 2906 | } else { |
2919 | fb = NULL; | 2907 | fb = NULL; |
2920 | } | 2908 | } |
@@ -3267,9 +3255,10 @@ static int framebuffer_check(const struct drm_mode_fb_cmd2 *r) | |||
3267 | return 0; | 3255 | return 0; |
3268 | } | 3256 | } |
3269 | 3257 | ||
3270 | static struct drm_framebuffer *add_framebuffer_internal(struct drm_device *dev, | 3258 | static struct drm_framebuffer * |
3271 | struct drm_mode_fb_cmd2 *r, | 3259 | internal_framebuffer_create(struct drm_device *dev, |
3272 | struct drm_file *file_priv) | 3260 | struct drm_mode_fb_cmd2 *r, |
3261 | struct drm_file *file_priv) | ||
3273 | { | 3262 | { |
3274 | struct drm_mode_config *config = &dev->mode_config; | 3263 | struct drm_mode_config *config = &dev->mode_config; |
3275 | struct drm_framebuffer *fb; | 3264 | struct drm_framebuffer *fb; |
@@ -3301,12 +3290,6 @@ static struct drm_framebuffer *add_framebuffer_internal(struct drm_device *dev, | |||
3301 | return fb; | 3290 | return fb; |
3302 | } | 3291 | } |
3303 | 3292 | ||
3304 | mutex_lock(&file_priv->fbs_lock); | ||
3305 | r->fb_id = fb->base.id; | ||
3306 | list_add(&fb->filp_head, &file_priv->fbs); | ||
3307 | DRM_DEBUG_KMS("[FB:%d]\n", fb->base.id); | ||
3308 | mutex_unlock(&file_priv->fbs_lock); | ||
3309 | |||
3310 | return fb; | 3293 | return fb; |
3311 | } | 3294 | } |
3312 | 3295 | ||
@@ -3328,15 +3311,24 @@ static struct drm_framebuffer *add_framebuffer_internal(struct drm_device *dev, | |||
3328 | int drm_mode_addfb2(struct drm_device *dev, | 3311 | int drm_mode_addfb2(struct drm_device *dev, |
3329 | void *data, struct drm_file *file_priv) | 3312 | void *data, struct drm_file *file_priv) |
3330 | { | 3313 | { |
3314 | struct drm_mode_fb_cmd2 *r = data; | ||
3331 | struct drm_framebuffer *fb; | 3315 | struct drm_framebuffer *fb; |
3332 | 3316 | ||
3333 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | 3317 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3334 | return -EINVAL; | 3318 | return -EINVAL; |
3335 | 3319 | ||
3336 | fb = add_framebuffer_internal(dev, data, file_priv); | 3320 | fb = internal_framebuffer_create(dev, r, file_priv); |
3337 | if (IS_ERR(fb)) | 3321 | if (IS_ERR(fb)) |
3338 | return PTR_ERR(fb); | 3322 | return PTR_ERR(fb); |
3339 | 3323 | ||
3324 | /* Transfer ownership to the filp for reaping on close */ | ||
3325 | |||
3326 | DRM_DEBUG_KMS("[FB:%d]\n", fb->base.id); | ||
3327 | mutex_lock(&file_priv->fbs_lock); | ||
3328 | r->fb_id = fb->base.id; | ||
3329 | list_add(&fb->filp_head, &file_priv->fbs); | ||
3330 | mutex_unlock(&file_priv->fbs_lock); | ||
3331 | |||
3340 | return 0; | 3332 | return 0; |
3341 | } | 3333 | } |
3342 | 3334 | ||
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 9a5b68717ec8..379ab4555756 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c | |||
@@ -733,10 +733,14 @@ static bool check_txmsg_state(struct drm_dp_mst_topology_mgr *mgr, | |||
733 | struct drm_dp_sideband_msg_tx *txmsg) | 733 | struct drm_dp_sideband_msg_tx *txmsg) |
734 | { | 734 | { |
735 | bool ret; | 735 | bool ret; |
736 | mutex_lock(&mgr->qlock); | 736 | |
737 | /* | ||
738 | * All updates to txmsg->state are protected by mgr->qlock, and the two | ||
739 | * cases we check here are terminal states. For those the barriers | ||
740 | * provided by the wake_up/wait_event pair are enough. | ||
741 | */ | ||
737 | ret = (txmsg->state == DRM_DP_SIDEBAND_TX_RX || | 742 | ret = (txmsg->state == DRM_DP_SIDEBAND_TX_RX || |
738 | txmsg->state == DRM_DP_SIDEBAND_TX_TIMEOUT); | 743 | txmsg->state == DRM_DP_SIDEBAND_TX_TIMEOUT); |
739 | mutex_unlock(&mgr->qlock); | ||
740 | return ret; | 744 | return ret; |
741 | } | 745 | } |
742 | 746 | ||
@@ -1363,12 +1367,13 @@ static int process_single_tx_qlock(struct drm_dp_mst_topology_mgr *mgr, | |||
1363 | return 0; | 1367 | return 0; |
1364 | } | 1368 | } |
1365 | 1369 | ||
1366 | /* must be called holding qlock */ | ||
1367 | static void process_single_down_tx_qlock(struct drm_dp_mst_topology_mgr *mgr) | 1370 | static void process_single_down_tx_qlock(struct drm_dp_mst_topology_mgr *mgr) |
1368 | { | 1371 | { |
1369 | struct drm_dp_sideband_msg_tx *txmsg; | 1372 | struct drm_dp_sideband_msg_tx *txmsg; |
1370 | int ret; | 1373 | int ret; |
1371 | 1374 | ||
1375 | WARN_ON(!mutex_is_locked(&mgr->qlock)); | ||
1376 | |||
1372 | /* construct a chunk from the first msg in the tx_msg queue */ | 1377 | /* construct a chunk from the first msg in the tx_msg queue */ |
1373 | if (list_empty(&mgr->tx_msg_downq)) { | 1378 | if (list_empty(&mgr->tx_msg_downq)) { |
1374 | mgr->tx_down_in_progress = false; | 1379 | mgr->tx_down_in_progress = false; |
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c index 04a209e2b66d..1134526286c8 100644 --- a/drivers/gpu/drm/drm_mm.c +++ b/drivers/gpu/drm/drm_mm.c | |||
@@ -91,29 +91,29 @@ | |||
91 | */ | 91 | */ |
92 | 92 | ||
93 | static struct drm_mm_node *drm_mm_search_free_generic(const struct drm_mm *mm, | 93 | static struct drm_mm_node *drm_mm_search_free_generic(const struct drm_mm *mm, |
94 | unsigned long size, | 94 | u64 size, |
95 | unsigned alignment, | 95 | unsigned alignment, |
96 | unsigned long color, | 96 | unsigned long color, |
97 | enum drm_mm_search_flags flags); | 97 | enum drm_mm_search_flags flags); |
98 | static struct drm_mm_node *drm_mm_search_free_in_range_generic(const struct drm_mm *mm, | 98 | static struct drm_mm_node *drm_mm_search_free_in_range_generic(const struct drm_mm *mm, |
99 | unsigned long size, | 99 | u64 size, |
100 | unsigned alignment, | 100 | unsigned alignment, |
101 | unsigned long color, | 101 | unsigned long color, |
102 | unsigned long start, | 102 | u64 start, |
103 | unsigned long end, | 103 | u64 end, |
104 | enum drm_mm_search_flags flags); | 104 | enum drm_mm_search_flags flags); |
105 | 105 | ||
106 | static void drm_mm_insert_helper(struct drm_mm_node *hole_node, | 106 | static void drm_mm_insert_helper(struct drm_mm_node *hole_node, |
107 | struct drm_mm_node *node, | 107 | struct drm_mm_node *node, |
108 | unsigned long size, unsigned alignment, | 108 | u64 size, unsigned alignment, |
109 | unsigned long color, | 109 | unsigned long color, |
110 | enum drm_mm_allocator_flags flags) | 110 | enum drm_mm_allocator_flags flags) |
111 | { | 111 | { |
112 | struct drm_mm *mm = hole_node->mm; | 112 | struct drm_mm *mm = hole_node->mm; |
113 | unsigned long hole_start = drm_mm_hole_node_start(hole_node); | 113 | u64 hole_start = drm_mm_hole_node_start(hole_node); |
114 | unsigned long hole_end = drm_mm_hole_node_end(hole_node); | 114 | u64 hole_end = drm_mm_hole_node_end(hole_node); |
115 | unsigned long adj_start = hole_start; | 115 | u64 adj_start = hole_start; |
116 | unsigned long adj_end = hole_end; | 116 | u64 adj_end = hole_end; |
117 | 117 | ||
118 | BUG_ON(node->allocated); | 118 | BUG_ON(node->allocated); |
119 | 119 | ||
@@ -124,12 +124,15 @@ static void drm_mm_insert_helper(struct drm_mm_node *hole_node, | |||
124 | adj_start = adj_end - size; | 124 | adj_start = adj_end - size; |
125 | 125 | ||
126 | if (alignment) { | 126 | if (alignment) { |
127 | unsigned tmp = adj_start % alignment; | 127 | u64 tmp = adj_start; |
128 | if (tmp) { | 128 | unsigned rem; |
129 | |||
130 | rem = do_div(tmp, alignment); | ||
131 | if (rem) { | ||
129 | if (flags & DRM_MM_CREATE_TOP) | 132 | if (flags & DRM_MM_CREATE_TOP) |
130 | adj_start -= tmp; | 133 | adj_start -= rem; |
131 | else | 134 | else |
132 | adj_start += alignment - tmp; | 135 | adj_start += alignment - rem; |
133 | } | 136 | } |
134 | } | 137 | } |
135 | 138 | ||
@@ -176,9 +179,9 @@ static void drm_mm_insert_helper(struct drm_mm_node *hole_node, | |||
176 | int drm_mm_reserve_node(struct drm_mm *mm, struct drm_mm_node *node) | 179 | int drm_mm_reserve_node(struct drm_mm *mm, struct drm_mm_node *node) |
177 | { | 180 | { |
178 | struct drm_mm_node *hole; | 181 | struct drm_mm_node *hole; |
179 | unsigned long end = node->start + node->size; | 182 | u64 end = node->start + node->size; |
180 | unsigned long hole_start; | 183 | u64 hole_start; |
181 | unsigned long hole_end; | 184 | u64 hole_end; |
182 | 185 | ||
183 | BUG_ON(node == NULL); | 186 | BUG_ON(node == NULL); |
184 | 187 | ||
@@ -227,7 +230,7 @@ EXPORT_SYMBOL(drm_mm_reserve_node); | |||
227 | * 0 on success, -ENOSPC if there's no suitable hole. | 230 | * 0 on success, -ENOSPC if there's no suitable hole. |
228 | */ | 231 | */ |
229 | int drm_mm_insert_node_generic(struct drm_mm *mm, struct drm_mm_node *node, | 232 | int drm_mm_insert_node_generic(struct drm_mm *mm, struct drm_mm_node *node, |
230 | unsigned long size, unsigned alignment, | 233 | u64 size, unsigned alignment, |
231 | unsigned long color, | 234 | unsigned long color, |
232 | enum drm_mm_search_flags sflags, | 235 | enum drm_mm_search_flags sflags, |
233 | enum drm_mm_allocator_flags aflags) | 236 | enum drm_mm_allocator_flags aflags) |
@@ -246,16 +249,16 @@ EXPORT_SYMBOL(drm_mm_insert_node_generic); | |||
246 | 249 | ||
247 | static void drm_mm_insert_helper_range(struct drm_mm_node *hole_node, | 250 | static void drm_mm_insert_helper_range(struct drm_mm_node *hole_node, |
248 | struct drm_mm_node *node, | 251 | struct drm_mm_node *node, |
249 | unsigned long size, unsigned alignment, | 252 | u64 size, unsigned alignment, |
250 | unsigned long color, | 253 | unsigned long color, |
251 | unsigned long start, unsigned long end, | 254 | u64 start, u64 end, |
252 | enum drm_mm_allocator_flags flags) | 255 | enum drm_mm_allocator_flags flags) |
253 | { | 256 | { |
254 | struct drm_mm *mm = hole_node->mm; | 257 | struct drm_mm *mm = hole_node->mm; |
255 | unsigned long hole_start = drm_mm_hole_node_start(hole_node); | 258 | u64 hole_start = drm_mm_hole_node_start(hole_node); |
256 | unsigned long hole_end = drm_mm_hole_node_end(hole_node); | 259 | u64 hole_end = drm_mm_hole_node_end(hole_node); |
257 | unsigned long adj_start = hole_start; | 260 | u64 adj_start = hole_start; |
258 | unsigned long adj_end = hole_end; | 261 | u64 adj_end = hole_end; |
259 | 262 | ||
260 | BUG_ON(!hole_node->hole_follows || node->allocated); | 263 | BUG_ON(!hole_node->hole_follows || node->allocated); |
261 | 264 | ||
@@ -271,12 +274,15 @@ static void drm_mm_insert_helper_range(struct drm_mm_node *hole_node, | |||
271 | mm->color_adjust(hole_node, color, &adj_start, &adj_end); | 274 | mm->color_adjust(hole_node, color, &adj_start, &adj_end); |
272 | 275 | ||
273 | if (alignment) { | 276 | if (alignment) { |
274 | unsigned tmp = adj_start % alignment; | 277 | u64 tmp = adj_start; |
275 | if (tmp) { | 278 | unsigned rem; |
279 | |||
280 | rem = do_div(tmp, alignment); | ||
281 | if (rem) { | ||
276 | if (flags & DRM_MM_CREATE_TOP) | 282 | if (flags & DRM_MM_CREATE_TOP) |
277 | adj_start -= tmp; | 283 | adj_start -= rem; |
278 | else | 284 | else |
279 | adj_start += alignment - tmp; | 285 | adj_start += alignment - rem; |
280 | } | 286 | } |
281 | } | 287 | } |
282 | 288 | ||
@@ -324,9 +330,9 @@ static void drm_mm_insert_helper_range(struct drm_mm_node *hole_node, | |||
324 | * 0 on success, -ENOSPC if there's no suitable hole. | 330 | * 0 on success, -ENOSPC if there's no suitable hole. |
325 | */ | 331 | */ |
326 | int drm_mm_insert_node_in_range_generic(struct drm_mm *mm, struct drm_mm_node *node, | 332 | int drm_mm_insert_node_in_range_generic(struct drm_mm *mm, struct drm_mm_node *node, |
327 | unsigned long size, unsigned alignment, | 333 | u64 size, unsigned alignment, |
328 | unsigned long color, | 334 | unsigned long color, |
329 | unsigned long start, unsigned long end, | 335 | u64 start, u64 end, |
330 | enum drm_mm_search_flags sflags, | 336 | enum drm_mm_search_flags sflags, |
331 | enum drm_mm_allocator_flags aflags) | 337 | enum drm_mm_allocator_flags aflags) |
332 | { | 338 | { |
@@ -387,32 +393,34 @@ void drm_mm_remove_node(struct drm_mm_node *node) | |||
387 | } | 393 | } |
388 | EXPORT_SYMBOL(drm_mm_remove_node); | 394 | EXPORT_SYMBOL(drm_mm_remove_node); |
389 | 395 | ||
390 | static int check_free_hole(unsigned long start, unsigned long end, | 396 | static int check_free_hole(u64 start, u64 end, u64 size, unsigned alignment) |
391 | unsigned long size, unsigned alignment) | ||
392 | { | 397 | { |
393 | if (end - start < size) | 398 | if (end - start < size) |
394 | return 0; | 399 | return 0; |
395 | 400 | ||
396 | if (alignment) { | 401 | if (alignment) { |
397 | unsigned tmp = start % alignment; | 402 | u64 tmp = start; |
398 | if (tmp) | 403 | unsigned rem; |
399 | start += alignment - tmp; | 404 | |
405 | rem = do_div(tmp, alignment); | ||
406 | if (rem) | ||
407 | start += alignment - rem; | ||
400 | } | 408 | } |
401 | 409 | ||
402 | return end >= start + size; | 410 | return end >= start + size; |
403 | } | 411 | } |
404 | 412 | ||
405 | static struct drm_mm_node *drm_mm_search_free_generic(const struct drm_mm *mm, | 413 | static struct drm_mm_node *drm_mm_search_free_generic(const struct drm_mm *mm, |
406 | unsigned long size, | 414 | u64 size, |
407 | unsigned alignment, | 415 | unsigned alignment, |
408 | unsigned long color, | 416 | unsigned long color, |
409 | enum drm_mm_search_flags flags) | 417 | enum drm_mm_search_flags flags) |
410 | { | 418 | { |
411 | struct drm_mm_node *entry; | 419 | struct drm_mm_node *entry; |
412 | struct drm_mm_node *best; | 420 | struct drm_mm_node *best; |
413 | unsigned long adj_start; | 421 | u64 adj_start; |
414 | unsigned long adj_end; | 422 | u64 adj_end; |
415 | unsigned long best_size; | 423 | u64 best_size; |
416 | 424 | ||
417 | BUG_ON(mm->scanned_blocks); | 425 | BUG_ON(mm->scanned_blocks); |
418 | 426 | ||
@@ -421,7 +429,7 @@ static struct drm_mm_node *drm_mm_search_free_generic(const struct drm_mm *mm, | |||
421 | 429 | ||
422 | __drm_mm_for_each_hole(entry, mm, adj_start, adj_end, | 430 | __drm_mm_for_each_hole(entry, mm, adj_start, adj_end, |
423 | flags & DRM_MM_SEARCH_BELOW) { | 431 | flags & DRM_MM_SEARCH_BELOW) { |
424 | unsigned long hole_size = adj_end - adj_start; | 432 | u64 hole_size = adj_end - adj_start; |
425 | 433 | ||
426 | if (mm->color_adjust) { | 434 | if (mm->color_adjust) { |
427 | mm->color_adjust(entry, color, &adj_start, &adj_end); | 435 | mm->color_adjust(entry, color, &adj_start, &adj_end); |
@@ -445,18 +453,18 @@ static struct drm_mm_node *drm_mm_search_free_generic(const struct drm_mm *mm, | |||
445 | } | 453 | } |
446 | 454 | ||
447 | static struct drm_mm_node *drm_mm_search_free_in_range_generic(const struct drm_mm *mm, | 455 | static struct drm_mm_node *drm_mm_search_free_in_range_generic(const struct drm_mm *mm, |
448 | unsigned long size, | 456 | u64 size, |
449 | unsigned alignment, | 457 | unsigned alignment, |
450 | unsigned long color, | 458 | unsigned long color, |
451 | unsigned long start, | 459 | u64 start, |
452 | unsigned long end, | 460 | u64 end, |
453 | enum drm_mm_search_flags flags) | 461 | enum drm_mm_search_flags flags) |
454 | { | 462 | { |
455 | struct drm_mm_node *entry; | 463 | struct drm_mm_node *entry; |
456 | struct drm_mm_node *best; | 464 | struct drm_mm_node *best; |
457 | unsigned long adj_start; | 465 | u64 adj_start; |
458 | unsigned long adj_end; | 466 | u64 adj_end; |
459 | unsigned long best_size; | 467 | u64 best_size; |
460 | 468 | ||
461 | BUG_ON(mm->scanned_blocks); | 469 | BUG_ON(mm->scanned_blocks); |
462 | 470 | ||
@@ -465,7 +473,7 @@ static struct drm_mm_node *drm_mm_search_free_in_range_generic(const struct drm_ | |||
465 | 473 | ||
466 | __drm_mm_for_each_hole(entry, mm, adj_start, adj_end, | 474 | __drm_mm_for_each_hole(entry, mm, adj_start, adj_end, |
467 | flags & DRM_MM_SEARCH_BELOW) { | 475 | flags & DRM_MM_SEARCH_BELOW) { |
468 | unsigned long hole_size = adj_end - adj_start; | 476 | u64 hole_size = adj_end - adj_start; |
469 | 477 | ||
470 | if (adj_start < start) | 478 | if (adj_start < start) |
471 | adj_start = start; | 479 | adj_start = start; |
@@ -561,7 +569,7 @@ EXPORT_SYMBOL(drm_mm_replace_node); | |||
561 | * adding/removing nodes to/from the scan list are allowed. | 569 | * adding/removing nodes to/from the scan list are allowed. |
562 | */ | 570 | */ |
563 | void drm_mm_init_scan(struct drm_mm *mm, | 571 | void drm_mm_init_scan(struct drm_mm *mm, |
564 | unsigned long size, | 572 | u64 size, |
565 | unsigned alignment, | 573 | unsigned alignment, |
566 | unsigned long color) | 574 | unsigned long color) |
567 | { | 575 | { |
@@ -594,11 +602,11 @@ EXPORT_SYMBOL(drm_mm_init_scan); | |||
594 | * adding/removing nodes to/from the scan list are allowed. | 602 | * adding/removing nodes to/from the scan list are allowed. |
595 | */ | 603 | */ |
596 | void drm_mm_init_scan_with_range(struct drm_mm *mm, | 604 | void drm_mm_init_scan_with_range(struct drm_mm *mm, |
597 | unsigned long size, | 605 | u64 size, |
598 | unsigned alignment, | 606 | unsigned alignment, |
599 | unsigned long color, | 607 | unsigned long color, |
600 | unsigned long start, | 608 | u64 start, |
601 | unsigned long end) | 609 | u64 end) |
602 | { | 610 | { |
603 | mm->scan_color = color; | 611 | mm->scan_color = color; |
604 | mm->scan_alignment = alignment; | 612 | mm->scan_alignment = alignment; |
@@ -627,8 +635,8 @@ bool drm_mm_scan_add_block(struct drm_mm_node *node) | |||
627 | { | 635 | { |
628 | struct drm_mm *mm = node->mm; | 636 | struct drm_mm *mm = node->mm; |
629 | struct drm_mm_node *prev_node; | 637 | struct drm_mm_node *prev_node; |
630 | unsigned long hole_start, hole_end; | 638 | u64 hole_start, hole_end; |
631 | unsigned long adj_start, adj_end; | 639 | u64 adj_start, adj_end; |
632 | 640 | ||
633 | mm->scanned_blocks++; | 641 | mm->scanned_blocks++; |
634 | 642 | ||
@@ -731,7 +739,7 @@ EXPORT_SYMBOL(drm_mm_clean); | |||
731 | * | 739 | * |
732 | * Note that @mm must be cleared to 0 before calling this function. | 740 | * Note that @mm must be cleared to 0 before calling this function. |
733 | */ | 741 | */ |
734 | void drm_mm_init(struct drm_mm * mm, unsigned long start, unsigned long size) | 742 | void drm_mm_init(struct drm_mm * mm, u64 start, u64 size) |
735 | { | 743 | { |
736 | INIT_LIST_HEAD(&mm->hole_stack); | 744 | INIT_LIST_HEAD(&mm->hole_stack); |
737 | mm->scanned_blocks = 0; | 745 | mm->scanned_blocks = 0; |
@@ -766,18 +774,17 @@ void drm_mm_takedown(struct drm_mm * mm) | |||
766 | } | 774 | } |
767 | EXPORT_SYMBOL(drm_mm_takedown); | 775 | EXPORT_SYMBOL(drm_mm_takedown); |
768 | 776 | ||
769 | static unsigned long drm_mm_debug_hole(struct drm_mm_node *entry, | 777 | static u64 drm_mm_debug_hole(struct drm_mm_node *entry, |
770 | const char *prefix) | 778 | const char *prefix) |
771 | { | 779 | { |
772 | unsigned long hole_start, hole_end, hole_size; | 780 | u64 hole_start, hole_end, hole_size; |
773 | 781 | ||
774 | if (entry->hole_follows) { | 782 | if (entry->hole_follows) { |
775 | hole_start = drm_mm_hole_node_start(entry); | 783 | hole_start = drm_mm_hole_node_start(entry); |
776 | hole_end = drm_mm_hole_node_end(entry); | 784 | hole_end = drm_mm_hole_node_end(entry); |
777 | hole_size = hole_end - hole_start; | 785 | hole_size = hole_end - hole_start; |
778 | printk(KERN_DEBUG "%s 0x%08lx-0x%08lx: %8lu: free\n", | 786 | pr_debug("%s %#llx-%#llx: %llu: free\n", prefix, hole_start, |
779 | prefix, hole_start, hole_end, | 787 | hole_end, hole_size); |
780 | hole_size); | ||
781 | return hole_size; | 788 | return hole_size; |
782 | } | 789 | } |
783 | 790 | ||
@@ -792,35 +799,34 @@ static unsigned long drm_mm_debug_hole(struct drm_mm_node *entry, | |||
792 | void drm_mm_debug_table(struct drm_mm *mm, const char *prefix) | 799 | void drm_mm_debug_table(struct drm_mm *mm, const char *prefix) |
793 | { | 800 | { |
794 | struct drm_mm_node *entry; | 801 | struct drm_mm_node *entry; |
795 | unsigned long total_used = 0, total_free = 0, total = 0; | 802 | u64 total_used = 0, total_free = 0, total = 0; |
796 | 803 | ||
797 | total_free += drm_mm_debug_hole(&mm->head_node, prefix); | 804 | total_free += drm_mm_debug_hole(&mm->head_node, prefix); |
798 | 805 | ||
799 | drm_mm_for_each_node(entry, mm) { | 806 | drm_mm_for_each_node(entry, mm) { |
800 | printk(KERN_DEBUG "%s 0x%08lx-0x%08lx: %8lu: used\n", | 807 | pr_debug("%s %#llx-%#llx: %llu: used\n", prefix, entry->start, |
801 | prefix, entry->start, entry->start + entry->size, | 808 | entry->start + entry->size, entry->size); |
802 | entry->size); | ||
803 | total_used += entry->size; | 809 | total_used += entry->size; |
804 | total_free += drm_mm_debug_hole(entry, prefix); | 810 | total_free += drm_mm_debug_hole(entry, prefix); |
805 | } | 811 | } |
806 | total = total_free + total_used; | 812 | total = total_free + total_used; |
807 | 813 | ||
808 | printk(KERN_DEBUG "%s total: %lu, used %lu free %lu\n", prefix, total, | 814 | pr_debug("%s total: %llu, used %llu free %llu\n", prefix, total, |
809 | total_used, total_free); | 815 | total_used, total_free); |
810 | } | 816 | } |
811 | EXPORT_SYMBOL(drm_mm_debug_table); | 817 | EXPORT_SYMBOL(drm_mm_debug_table); |
812 | 818 | ||
813 | #if defined(CONFIG_DEBUG_FS) | 819 | #if defined(CONFIG_DEBUG_FS) |
814 | static unsigned long drm_mm_dump_hole(struct seq_file *m, struct drm_mm_node *entry) | 820 | static u64 drm_mm_dump_hole(struct seq_file *m, struct drm_mm_node *entry) |
815 | { | 821 | { |
816 | unsigned long hole_start, hole_end, hole_size; | 822 | u64 hole_start, hole_end, hole_size; |
817 | 823 | ||
818 | if (entry->hole_follows) { | 824 | if (entry->hole_follows) { |
819 | hole_start = drm_mm_hole_node_start(entry); | 825 | hole_start = drm_mm_hole_node_start(entry); |
820 | hole_end = drm_mm_hole_node_end(entry); | 826 | hole_end = drm_mm_hole_node_end(entry); |
821 | hole_size = hole_end - hole_start; | 827 | hole_size = hole_end - hole_start; |
822 | seq_printf(m, "0x%08lx-0x%08lx: 0x%08lx: free\n", | 828 | seq_printf(m, "%#llx-%#llx: %llu: free\n", hole_start, |
823 | hole_start, hole_end, hole_size); | 829 | hole_end, hole_size); |
824 | return hole_size; | 830 | return hole_size; |
825 | } | 831 | } |
826 | 832 | ||
@@ -835,20 +841,20 @@ static unsigned long drm_mm_dump_hole(struct seq_file *m, struct drm_mm_node *en | |||
835 | int drm_mm_dump_table(struct seq_file *m, struct drm_mm *mm) | 841 | int drm_mm_dump_table(struct seq_file *m, struct drm_mm *mm) |
836 | { | 842 | { |
837 | struct drm_mm_node *entry; | 843 | struct drm_mm_node *entry; |
838 | unsigned long total_used = 0, total_free = 0, total = 0; | 844 | u64 total_used = 0, total_free = 0, total = 0; |
839 | 845 | ||
840 | total_free += drm_mm_dump_hole(m, &mm->head_node); | 846 | total_free += drm_mm_dump_hole(m, &mm->head_node); |
841 | 847 | ||
842 | drm_mm_for_each_node(entry, mm) { | 848 | drm_mm_for_each_node(entry, mm) { |
843 | seq_printf(m, "0x%08lx-0x%08lx: 0x%08lx: used\n", | 849 | seq_printf(m, "%#016llx-%#016llx: %llu: used\n", entry->start, |
844 | entry->start, entry->start + entry->size, | 850 | entry->start + entry->size, entry->size); |
845 | entry->size); | ||
846 | total_used += entry->size; | 851 | total_used += entry->size; |
847 | total_free += drm_mm_dump_hole(m, entry); | 852 | total_free += drm_mm_dump_hole(m, entry); |
848 | } | 853 | } |
849 | total = total_free + total_used; | 854 | total = total_free + total_used; |
850 | 855 | ||
851 | seq_printf(m, "total: %lu, used %lu free %lu\n", total, total_used, total_free); | 856 | seq_printf(m, "total: %llu, used %llu free %llu\n", total, |
857 | total_used, total_free); | ||
852 | return 0; | 858 | return 0; |
853 | } | 859 | } |
854 | EXPORT_SYMBOL(drm_mm_dump_table); | 860 | EXPORT_SYMBOL(drm_mm_dump_table); |
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig index a5e74612100e..0a6780367d28 100644 --- a/drivers/gpu/drm/exynos/Kconfig +++ b/drivers/gpu/drm/exynos/Kconfig | |||
@@ -50,7 +50,7 @@ config DRM_EXYNOS_DSI | |||
50 | 50 | ||
51 | config DRM_EXYNOS_DP | 51 | config DRM_EXYNOS_DP |
52 | bool "EXYNOS DRM DP driver support" | 52 | bool "EXYNOS DRM DP driver support" |
53 | depends on (DRM_EXYNOS_FIMD || DRM_EXYNOS7DECON) && ARCH_EXYNOS && (DRM_PTN3460=n || DRM_PTN3460=y || DRM_PTN3460=DRM_EXYNOS) | 53 | depends on (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON) && ARCH_EXYNOS && (DRM_PTN3460=n || DRM_PTN3460=y || DRM_PTN3460=DRM_EXYNOS) |
54 | default DRM_EXYNOS | 54 | default DRM_EXYNOS |
55 | select DRM_PANEL | 55 | select DRM_PANEL |
56 | help | 56 | help |
diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c index 63f02e2380ae..970046199608 100644 --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c | |||
@@ -888,8 +888,8 @@ static int decon_probe(struct platform_device *pdev) | |||
888 | of_node_put(i80_if_timings); | 888 | of_node_put(i80_if_timings); |
889 | 889 | ||
890 | ctx->regs = of_iomap(dev->of_node, 0); | 890 | ctx->regs = of_iomap(dev->of_node, 0); |
891 | if (IS_ERR(ctx->regs)) { | 891 | if (!ctx->regs) { |
892 | ret = PTR_ERR(ctx->regs); | 892 | ret = -ENOMEM; |
893 | goto err_del_component; | 893 | goto err_del_component; |
894 | } | 894 | } |
895 | 895 | ||
diff --git a/drivers/gpu/drm/exynos/exynos_drm_connector.c b/drivers/gpu/drm/exynos/exynos_drm_connector.c deleted file mode 100644 index ba9b3d5ed672..000000000000 --- a/drivers/gpu/drm/exynos/exynos_drm_connector.c +++ /dev/null | |||
@@ -1,245 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
3 | * Authors: | ||
4 | * Inki Dae <inki.dae@samsung.com> | ||
5 | * Joonyoung Shim <jy0922.shim@samsung.com> | ||
6 | * Seung-Woo Kim <sw0312.kim@samsung.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms of the GNU General Public License as published by the | ||
10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
11 | * option) any later version. | ||
12 | */ | ||
13 | |||
14 | #include <drm/drmP.h> | ||
15 | #include <drm/drm_crtc_helper.h> | ||
16 | |||
17 | #include <drm/exynos_drm.h> | ||
18 | #include "exynos_drm_drv.h" | ||
19 | #include "exynos_drm_encoder.h" | ||
20 | #include "exynos_drm_connector.h" | ||
21 | |||
22 | #define to_exynos_connector(x) container_of(x, struct exynos_drm_connector,\ | ||
23 | drm_connector) | ||
24 | |||
25 | struct exynos_drm_connector { | ||
26 | struct drm_connector drm_connector; | ||
27 | uint32_t encoder_id; | ||
28 | struct exynos_drm_display *display; | ||
29 | }; | ||
30 | |||
31 | static int exynos_drm_connector_get_modes(struct drm_connector *connector) | ||
32 | { | ||
33 | struct exynos_drm_connector *exynos_connector = | ||
34 | to_exynos_connector(connector); | ||
35 | struct exynos_drm_display *display = exynos_connector->display; | ||
36 | struct edid *edid = NULL; | ||
37 | unsigned int count = 0; | ||
38 | int ret; | ||
39 | |||
40 | /* | ||
41 | * if get_edid() exists then get_edid() callback of hdmi side | ||
42 | * is called to get edid data through i2c interface else | ||
43 | * get timing from the FIMD driver(display controller). | ||
44 | * | ||
45 | * P.S. in case of lcd panel, count is always 1 if success | ||
46 | * because lcd panel has only one mode. | ||
47 | */ | ||
48 | if (display->ops->get_edid) { | ||
49 | edid = display->ops->get_edid(display, connector); | ||
50 | if (IS_ERR_OR_NULL(edid)) { | ||
51 | ret = PTR_ERR(edid); | ||
52 | edid = NULL; | ||
53 | DRM_ERROR("Panel operation get_edid failed %d\n", ret); | ||
54 | goto out; | ||
55 | } | ||
56 | |||
57 | count = drm_add_edid_modes(connector, edid); | ||
58 | if (!count) { | ||
59 | DRM_ERROR("Add edid modes failed %d\n", count); | ||
60 | goto out; | ||
61 | } | ||
62 | |||
63 | drm_mode_connector_update_edid_property(connector, edid); | ||
64 | } else { | ||
65 | struct exynos_drm_panel_info *panel; | ||
66 | struct drm_display_mode *mode = drm_mode_create(connector->dev); | ||
67 | if (!mode) { | ||
68 | DRM_ERROR("failed to create a new display mode.\n"); | ||
69 | return 0; | ||
70 | } | ||
71 | |||
72 | if (display->ops->get_panel) | ||
73 | panel = display->ops->get_panel(display); | ||
74 | else { | ||
75 | drm_mode_destroy(connector->dev, mode); | ||
76 | return 0; | ||
77 | } | ||
78 | |||
79 | drm_display_mode_from_videomode(&panel->vm, mode); | ||
80 | mode->width_mm = panel->width_mm; | ||
81 | mode->height_mm = panel->height_mm; | ||
82 | connector->display_info.width_mm = mode->width_mm; | ||
83 | connector->display_info.height_mm = mode->height_mm; | ||
84 | |||
85 | mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; | ||
86 | drm_mode_set_name(mode); | ||
87 | drm_mode_probed_add(connector, mode); | ||
88 | |||
89 | count = 1; | ||
90 | } | ||
91 | |||
92 | out: | ||
93 | kfree(edid); | ||
94 | return count; | ||
95 | } | ||
96 | |||
97 | static int exynos_drm_connector_mode_valid(struct drm_connector *connector, | ||
98 | struct drm_display_mode *mode) | ||
99 | { | ||
100 | struct exynos_drm_connector *exynos_connector = | ||
101 | to_exynos_connector(connector); | ||
102 | struct exynos_drm_display *display = exynos_connector->display; | ||
103 | int ret = MODE_BAD; | ||
104 | |||
105 | DRM_DEBUG_KMS("%s\n", __FILE__); | ||
106 | |||
107 | if (display->ops->check_mode) | ||
108 | if (!display->ops->check_mode(display, mode)) | ||
109 | ret = MODE_OK; | ||
110 | |||
111 | return ret; | ||
112 | } | ||
113 | |||
114 | static struct drm_encoder *exynos_drm_best_encoder( | ||
115 | struct drm_connector *connector) | ||
116 | { | ||
117 | struct drm_device *dev = connector->dev; | ||
118 | struct exynos_drm_connector *exynos_connector = | ||
119 | to_exynos_connector(connector); | ||
120 | return drm_encoder_find(dev, exynos_connector->encoder_id); | ||
121 | } | ||
122 | |||
123 | static struct drm_connector_helper_funcs exynos_connector_helper_funcs = { | ||
124 | .get_modes = exynos_drm_connector_get_modes, | ||
125 | .mode_valid = exynos_drm_connector_mode_valid, | ||
126 | .best_encoder = exynos_drm_best_encoder, | ||
127 | }; | ||
128 | |||
129 | static int exynos_drm_connector_fill_modes(struct drm_connector *connector, | ||
130 | unsigned int max_width, unsigned int max_height) | ||
131 | { | ||
132 | struct exynos_drm_connector *exynos_connector = | ||
133 | to_exynos_connector(connector); | ||
134 | struct exynos_drm_display *display = exynos_connector->display; | ||
135 | unsigned int width, height; | ||
136 | |||
137 | width = max_width; | ||
138 | height = max_height; | ||
139 | |||
140 | /* | ||
141 | * if specific driver want to find desired_mode using maxmum | ||
142 | * resolution then get max width and height from that driver. | ||
143 | */ | ||
144 | if (display->ops->get_max_resol) | ||
145 | display->ops->get_max_resol(display, &width, &height); | ||
146 | |||
147 | return drm_helper_probe_single_connector_modes(connector, width, | ||
148 | height); | ||
149 | } | ||
150 | |||
151 | /* get detection status of display device. */ | ||
152 | static enum drm_connector_status | ||
153 | exynos_drm_connector_detect(struct drm_connector *connector, bool force) | ||
154 | { | ||
155 | struct exynos_drm_connector *exynos_connector = | ||
156 | to_exynos_connector(connector); | ||
157 | struct exynos_drm_display *display = exynos_connector->display; | ||
158 | enum drm_connector_status status = connector_status_disconnected; | ||
159 | |||
160 | if (display->ops->is_connected) { | ||
161 | if (display->ops->is_connected(display)) | ||
162 | status = connector_status_connected; | ||
163 | else | ||
164 | status = connector_status_disconnected; | ||
165 | } | ||
166 | |||
167 | return status; | ||
168 | } | ||
169 | |||
170 | static void exynos_drm_connector_destroy(struct drm_connector *connector) | ||
171 | { | ||
172 | struct exynos_drm_connector *exynos_connector = | ||
173 | to_exynos_connector(connector); | ||
174 | |||
175 | drm_connector_unregister(connector); | ||
176 | drm_connector_cleanup(connector); | ||
177 | kfree(exynos_connector); | ||
178 | } | ||
179 | |||
180 | static struct drm_connector_funcs exynos_connector_funcs = { | ||
181 | .dpms = drm_helper_connector_dpms, | ||
182 | .fill_modes = exynos_drm_connector_fill_modes, | ||
183 | .detect = exynos_drm_connector_detect, | ||
184 | .destroy = exynos_drm_connector_destroy, | ||
185 | }; | ||
186 | |||
187 | struct drm_connector *exynos_drm_connector_create(struct drm_device *dev, | ||
188 | struct drm_encoder *encoder) | ||
189 | { | ||
190 | struct exynos_drm_connector *exynos_connector; | ||
191 | struct exynos_drm_display *display = exynos_drm_get_display(encoder); | ||
192 | struct drm_connector *connector; | ||
193 | int type; | ||
194 | int err; | ||
195 | |||
196 | exynos_connector = kzalloc(sizeof(*exynos_connector), GFP_KERNEL); | ||
197 | if (!exynos_connector) | ||
198 | return NULL; | ||
199 | |||
200 | connector = &exynos_connector->drm_connector; | ||
201 | |||
202 | switch (display->type) { | ||
203 | case EXYNOS_DISPLAY_TYPE_HDMI: | ||
204 | type = DRM_MODE_CONNECTOR_HDMIA; | ||
205 | connector->interlace_allowed = true; | ||
206 | connector->polled = DRM_CONNECTOR_POLL_HPD; | ||
207 | break; | ||
208 | case EXYNOS_DISPLAY_TYPE_VIDI: | ||
209 | type = DRM_MODE_CONNECTOR_VIRTUAL; | ||
210 | connector->polled = DRM_CONNECTOR_POLL_HPD; | ||
211 | break; | ||
212 | default: | ||
213 | type = DRM_MODE_CONNECTOR_Unknown; | ||
214 | break; | ||
215 | } | ||
216 | |||
217 | drm_connector_init(dev, connector, &exynos_connector_funcs, type); | ||
218 | drm_connector_helper_add(connector, &exynos_connector_helper_funcs); | ||
219 | |||
220 | err = drm_connector_register(connector); | ||
221 | if (err) | ||
222 | goto err_connector; | ||
223 | |||
224 | exynos_connector->encoder_id = encoder->base.id; | ||
225 | exynos_connector->display = display; | ||
226 | connector->dpms = DRM_MODE_DPMS_OFF; | ||
227 | connector->encoder = encoder; | ||
228 | |||
229 | err = drm_mode_connector_attach_encoder(connector, encoder); | ||
230 | if (err) { | ||
231 | DRM_ERROR("failed to attach a connector to a encoder\n"); | ||
232 | goto err_sysfs; | ||
233 | } | ||
234 | |||
235 | DRM_DEBUG_KMS("connector has been created\n"); | ||
236 | |||
237 | return connector; | ||
238 | |||
239 | err_sysfs: | ||
240 | drm_connector_unregister(connector); | ||
241 | err_connector: | ||
242 | drm_connector_cleanup(connector); | ||
243 | kfree(exynos_connector); | ||
244 | return NULL; | ||
245 | } | ||
diff --git a/drivers/gpu/drm/exynos/exynos_drm_connector.h b/drivers/gpu/drm/exynos/exynos_drm_connector.h deleted file mode 100644 index 4eb20d78379a..000000000000 --- a/drivers/gpu/drm/exynos/exynos_drm_connector.h +++ /dev/null | |||
@@ -1,20 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
3 | * Authors: | ||
4 | * Inki Dae <inki.dae@samsung.com> | ||
5 | * Joonyoung Shim <jy0922.shim@samsung.com> | ||
6 | * Seung-Woo Kim <sw0312.kim@samsung.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms of the GNU General Public License as published by the | ||
10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
11 | * option) any later version. | ||
12 | */ | ||
13 | |||
14 | #ifndef _EXYNOS_DRM_CONNECTOR_H_ | ||
15 | #define _EXYNOS_DRM_CONNECTOR_H_ | ||
16 | |||
17 | struct drm_connector *exynos_drm_connector_create(struct drm_device *dev, | ||
18 | struct drm_encoder *encoder); | ||
19 | |||
20 | #endif | ||
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 925fc69af1a0..c300e22da8ac 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c | |||
@@ -284,14 +284,9 @@ static void fimd_clear_channel(struct fimd_context *ctx) | |||
284 | } | 284 | } |
285 | } | 285 | } |
286 | 286 | ||
287 | static int fimd_ctx_initialize(struct fimd_context *ctx, | 287 | static int fimd_iommu_attach_devices(struct fimd_context *ctx, |
288 | struct drm_device *drm_dev) | 288 | struct drm_device *drm_dev) |
289 | { | 289 | { |
290 | struct exynos_drm_private *priv; | ||
291 | priv = drm_dev->dev_private; | ||
292 | |||
293 | ctx->drm_dev = drm_dev; | ||
294 | ctx->pipe = priv->pipe++; | ||
295 | 290 | ||
296 | /* attach this sub driver to iommu mapping if supported. */ | 291 | /* attach this sub driver to iommu mapping if supported. */ |
297 | if (is_drm_iommu_supported(ctx->drm_dev)) { | 292 | if (is_drm_iommu_supported(ctx->drm_dev)) { |
@@ -313,7 +308,7 @@ static int fimd_ctx_initialize(struct fimd_context *ctx, | |||
313 | return 0; | 308 | return 0; |
314 | } | 309 | } |
315 | 310 | ||
316 | static void fimd_ctx_remove(struct fimd_context *ctx) | 311 | static void fimd_iommu_detach_devices(struct fimd_context *ctx) |
317 | { | 312 | { |
318 | /* detach this sub driver from iommu mapping if supported. */ | 313 | /* detach this sub driver from iommu mapping if supported. */ |
319 | if (is_drm_iommu_supported(ctx->drm_dev)) | 314 | if (is_drm_iommu_supported(ctx->drm_dev)) |
@@ -1056,25 +1051,23 @@ static int fimd_bind(struct device *dev, struct device *master, void *data) | |||
1056 | { | 1051 | { |
1057 | struct fimd_context *ctx = dev_get_drvdata(dev); | 1052 | struct fimd_context *ctx = dev_get_drvdata(dev); |
1058 | struct drm_device *drm_dev = data; | 1053 | struct drm_device *drm_dev = data; |
1054 | struct exynos_drm_private *priv = drm_dev->dev_private; | ||
1059 | int ret; | 1055 | int ret; |
1060 | 1056 | ||
1061 | ret = fimd_ctx_initialize(ctx, drm_dev); | 1057 | ctx->drm_dev = drm_dev; |
1062 | if (ret) { | 1058 | ctx->pipe = priv->pipe++; |
1063 | DRM_ERROR("fimd_ctx_initialize failed.\n"); | ||
1064 | return ret; | ||
1065 | } | ||
1066 | 1059 | ||
1067 | ctx->crtc = exynos_drm_crtc_create(drm_dev, ctx->pipe, | 1060 | ctx->crtc = exynos_drm_crtc_create(drm_dev, ctx->pipe, |
1068 | EXYNOS_DISPLAY_TYPE_LCD, | 1061 | EXYNOS_DISPLAY_TYPE_LCD, |
1069 | &fimd_crtc_ops, ctx); | 1062 | &fimd_crtc_ops, ctx); |
1070 | if (IS_ERR(ctx->crtc)) { | ||
1071 | fimd_ctx_remove(ctx); | ||
1072 | return PTR_ERR(ctx->crtc); | ||
1073 | } | ||
1074 | 1063 | ||
1075 | if (ctx->display) | 1064 | if (ctx->display) |
1076 | exynos_drm_create_enc_conn(drm_dev, ctx->display); | 1065 | exynos_drm_create_enc_conn(drm_dev, ctx->display); |
1077 | 1066 | ||
1067 | ret = fimd_iommu_attach_devices(ctx, drm_dev); | ||
1068 | if (ret) | ||
1069 | return ret; | ||
1070 | |||
1078 | return 0; | 1071 | return 0; |
1079 | 1072 | ||
1080 | } | 1073 | } |
@@ -1086,10 +1079,10 @@ static void fimd_unbind(struct device *dev, struct device *master, | |||
1086 | 1079 | ||
1087 | fimd_dpms(ctx->crtc, DRM_MODE_DPMS_OFF); | 1080 | fimd_dpms(ctx->crtc, DRM_MODE_DPMS_OFF); |
1088 | 1081 | ||
1082 | fimd_iommu_detach_devices(ctx); | ||
1083 | |||
1089 | if (ctx->display) | 1084 | if (ctx->display) |
1090 | exynos_dpi_remove(ctx->display); | 1085 | exynos_dpi_remove(ctx->display); |
1091 | |||
1092 | fimd_ctx_remove(ctx); | ||
1093 | } | 1086 | } |
1094 | 1087 | ||
1095 | static const struct component_ops fimd_component_ops = { | 1088 | static const struct component_ops fimd_component_ops = { |
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index a5616872eee7..8ad5b7294eb4 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c | |||
@@ -175,7 +175,7 @@ static int exynos_disable_plane(struct drm_plane *plane) | |||
175 | struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane); | 175 | struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane); |
176 | struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(plane->crtc); | 176 | struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(plane->crtc); |
177 | 177 | ||
178 | if (exynos_crtc->ops->win_disable) | 178 | if (exynos_crtc && exynos_crtc->ops->win_disable) |
179 | exynos_crtc->ops->win_disable(exynos_crtc, | 179 | exynos_crtc->ops->win_disable(exynos_crtc, |
180 | exynos_plane->zpos); | 180 | exynos_plane->zpos); |
181 | 181 | ||
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 96e811fe24ca..e8b18e542da4 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c | |||
@@ -152,12 +152,12 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |||
152 | seq_puts(m, " (pp"); | 152 | seq_puts(m, " (pp"); |
153 | else | 153 | else |
154 | seq_puts(m, " (g"); | 154 | seq_puts(m, " (g"); |
155 | seq_printf(m, "gtt offset: %08lx, size: %08lx, type: %u)", | 155 | seq_printf(m, "gtt offset: %08llx, size: %08llx, type: %u)", |
156 | vma->node.start, vma->node.size, | 156 | vma->node.start, vma->node.size, |
157 | vma->ggtt_view.type); | 157 | vma->ggtt_view.type); |
158 | } | 158 | } |
159 | if (obj->stolen) | 159 | if (obj->stolen) |
160 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | 160 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
161 | if (obj->pin_mappable || obj->fault_mappable) { | 161 | if (obj->pin_mappable || obj->fault_mappable) { |
162 | char s[3], *t = s; | 162 | char s[3], *t = s; |
163 | if (obj->pin_mappable) | 163 | if (obj->pin_mappable) |
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 8039cec71fc2..cc6ea53d2b81 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c | |||
@@ -622,7 +622,7 @@ static int i915_drm_suspend(struct drm_device *dev) | |||
622 | return 0; | 622 | return 0; |
623 | } | 623 | } |
624 | 624 | ||
625 | static int i915_drm_suspend_late(struct drm_device *drm_dev) | 625 | static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation) |
626 | { | 626 | { |
627 | struct drm_i915_private *dev_priv = drm_dev->dev_private; | 627 | struct drm_i915_private *dev_priv = drm_dev->dev_private; |
628 | int ret; | 628 | int ret; |
@@ -636,7 +636,17 @@ static int i915_drm_suspend_late(struct drm_device *drm_dev) | |||
636 | } | 636 | } |
637 | 637 | ||
638 | pci_disable_device(drm_dev->pdev); | 638 | pci_disable_device(drm_dev->pdev); |
639 | pci_set_power_state(drm_dev->pdev, PCI_D3hot); | 639 | /* |
640 | * During hibernation on some GEN4 platforms the BIOS may try to access | ||
641 | * the device even though it's already in D3 and hang the machine. So | ||
642 | * leave the device in D0 on those platforms and hope the BIOS will | ||
643 | * power down the device properly. Platforms where this was seen: | ||
644 | * Lenovo Thinkpad X301, X61s | ||
645 | */ | ||
646 | if (!(hibernation && | ||
647 | drm_dev->pdev->subsystem_vendor == PCI_VENDOR_ID_LENOVO && | ||
648 | INTEL_INFO(dev_priv)->gen == 4)) | ||
649 | pci_set_power_state(drm_dev->pdev, PCI_D3hot); | ||
640 | 650 | ||
641 | return 0; | 651 | return 0; |
642 | } | 652 | } |
@@ -662,7 +672,7 @@ int i915_suspend_legacy(struct drm_device *dev, pm_message_t state) | |||
662 | if (error) | 672 | if (error) |
663 | return error; | 673 | return error; |
664 | 674 | ||
665 | return i915_drm_suspend_late(dev); | 675 | return i915_drm_suspend_late(dev, false); |
666 | } | 676 | } |
667 | 677 | ||
668 | static int i915_drm_resume(struct drm_device *dev) | 678 | static int i915_drm_resume(struct drm_device *dev) |
@@ -950,7 +960,17 @@ static int i915_pm_suspend_late(struct device *dev) | |||
950 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | 960 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
951 | return 0; | 961 | return 0; |
952 | 962 | ||
953 | return i915_drm_suspend_late(drm_dev); | 963 | return i915_drm_suspend_late(drm_dev, false); |
964 | } | ||
965 | |||
966 | static int i915_pm_poweroff_late(struct device *dev) | ||
967 | { | ||
968 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; | ||
969 | |||
970 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | ||
971 | return 0; | ||
972 | |||
973 | return i915_drm_suspend_late(drm_dev, true); | ||
954 | } | 974 | } |
955 | 975 | ||
956 | static int i915_pm_resume_early(struct device *dev) | 976 | static int i915_pm_resume_early(struct device *dev) |
@@ -1520,7 +1540,7 @@ static const struct dev_pm_ops i915_pm_ops = { | |||
1520 | .thaw_early = i915_pm_resume_early, | 1540 | .thaw_early = i915_pm_resume_early, |
1521 | .thaw = i915_pm_resume, | 1541 | .thaw = i915_pm_resume, |
1522 | .poweroff = i915_pm_suspend, | 1542 | .poweroff = i915_pm_suspend, |
1523 | .poweroff_late = i915_pm_suspend_late, | 1543 | .poweroff_late = i915_pm_poweroff_late, |
1524 | .restore_early = i915_pm_resume_early, | 1544 | .restore_early = i915_pm_resume_early, |
1525 | .restore = i915_pm_resume, | 1545 | .restore = i915_pm_resume, |
1526 | 1546 | ||
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index e5daad5f75fb..27ea6bdebce7 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c | |||
@@ -2737,24 +2737,11 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *ring) | |||
2737 | 2737 | ||
2738 | WARN_ON(i915_verify_lists(ring->dev)); | 2738 | WARN_ON(i915_verify_lists(ring->dev)); |
2739 | 2739 | ||
2740 | /* Move any buffers on the active list that are no longer referenced | 2740 | /* Retire requests first as we use it above for the early return. |
2741 | * by the ringbuffer to the flushing/inactive lists as appropriate, | 2741 | * If we retire requests last, we may use a later seqno and so clear |
2742 | * before we free the context associated with the requests. | 2742 | * the requests lists without clearing the active list, leading to |
2743 | * confusion. | ||
2743 | */ | 2744 | */ |
2744 | while (!list_empty(&ring->active_list)) { | ||
2745 | struct drm_i915_gem_object *obj; | ||
2746 | |||
2747 | obj = list_first_entry(&ring->active_list, | ||
2748 | struct drm_i915_gem_object, | ||
2749 | ring_list); | ||
2750 | |||
2751 | if (!i915_gem_request_completed(obj->last_read_req, true)) | ||
2752 | break; | ||
2753 | |||
2754 | i915_gem_object_move_to_inactive(obj); | ||
2755 | } | ||
2756 | |||
2757 | |||
2758 | while (!list_empty(&ring->request_list)) { | 2745 | while (!list_empty(&ring->request_list)) { |
2759 | struct drm_i915_gem_request *request; | 2746 | struct drm_i915_gem_request *request; |
2760 | struct intel_ringbuffer *ringbuf; | 2747 | struct intel_ringbuffer *ringbuf; |
@@ -2789,6 +2776,23 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *ring) | |||
2789 | i915_gem_free_request(request); | 2776 | i915_gem_free_request(request); |
2790 | } | 2777 | } |
2791 | 2778 | ||
2779 | /* Move any buffers on the active list that are no longer referenced | ||
2780 | * by the ringbuffer to the flushing/inactive lists as appropriate, | ||
2781 | * before we free the context associated with the requests. | ||
2782 | */ | ||
2783 | while (!list_empty(&ring->active_list)) { | ||
2784 | struct drm_i915_gem_object *obj; | ||
2785 | |||
2786 | obj = list_first_entry(&ring->active_list, | ||
2787 | struct drm_i915_gem_object, | ||
2788 | ring_list); | ||
2789 | |||
2790 | if (!i915_gem_request_completed(obj->last_read_req, true)) | ||
2791 | break; | ||
2792 | |||
2793 | i915_gem_object_move_to_inactive(obj); | ||
2794 | } | ||
2795 | |||
2792 | if (unlikely(ring->trace_irq_req && | 2796 | if (unlikely(ring->trace_irq_req && |
2793 | i915_gem_request_completed(ring->trace_irq_req, true))) { | 2797 | i915_gem_request_completed(ring->trace_irq_req, true))) { |
2794 | ring->irq_put(ring); | 2798 | ring->irq_put(ring); |
@@ -2936,9 +2940,9 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |||
2936 | req = obj->last_read_req; | 2940 | req = obj->last_read_req; |
2937 | 2941 | ||
2938 | /* Do this after OLR check to make sure we make forward progress polling | 2942 | /* Do this after OLR check to make sure we make forward progress polling |
2939 | * on this IOCTL with a timeout <=0 (like busy ioctl) | 2943 | * on this IOCTL with a timeout == 0 (like busy ioctl) |
2940 | */ | 2944 | */ |
2941 | if (args->timeout_ns <= 0) { | 2945 | if (args->timeout_ns == 0) { |
2942 | ret = -ETIME; | 2946 | ret = -ETIME; |
2943 | goto out; | 2947 | goto out; |
2944 | } | 2948 | } |
@@ -2948,7 +2952,8 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |||
2948 | i915_gem_request_reference(req); | 2952 | i915_gem_request_reference(req); |
2949 | mutex_unlock(&dev->struct_mutex); | 2953 | mutex_unlock(&dev->struct_mutex); |
2950 | 2954 | ||
2951 | ret = __i915_wait_request(req, reset_counter, true, &args->timeout_ns, | 2955 | ret = __i915_wait_request(req, reset_counter, true, |
2956 | args->timeout_ns > 0 ? &args->timeout_ns : NULL, | ||
2952 | file->driver_priv); | 2957 | file->driver_priv); |
2953 | mutex_lock(&dev->struct_mutex); | 2958 | mutex_lock(&dev->struct_mutex); |
2954 | i915_gem_request_unreference(req); | 2959 | i915_gem_request_unreference(req); |
@@ -4792,6 +4797,9 @@ i915_gem_init_hw(struct drm_device *dev) | |||
4792 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | 4797 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
4793 | return -EIO; | 4798 | return -EIO; |
4794 | 4799 | ||
4800 | /* Double layer security blanket, see i915_gem_init() */ | ||
4801 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | ||
4802 | |||
4795 | if (dev_priv->ellc_size) | 4803 | if (dev_priv->ellc_size) |
4796 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); | 4804 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4797 | 4805 | ||
@@ -4824,7 +4832,7 @@ i915_gem_init_hw(struct drm_device *dev) | |||
4824 | for_each_ring(ring, dev_priv, i) { | 4832 | for_each_ring(ring, dev_priv, i) { |
4825 | ret = ring->init_hw(ring); | 4833 | ret = ring->init_hw(ring); |
4826 | if (ret) | 4834 | if (ret) |
4827 | return ret; | 4835 | goto out; |
4828 | } | 4836 | } |
4829 | 4837 | ||
4830 | for (i = 0; i < NUM_L3_SLICES(dev); i++) | 4838 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
@@ -4841,9 +4849,11 @@ i915_gem_init_hw(struct drm_device *dev) | |||
4841 | DRM_ERROR("Context enable failed %d\n", ret); | 4849 | DRM_ERROR("Context enable failed %d\n", ret); |
4842 | i915_gem_cleanup_ringbuffer(dev); | 4850 | i915_gem_cleanup_ringbuffer(dev); |
4843 | 4851 | ||
4844 | return ret; | 4852 | goto out; |
4845 | } | 4853 | } |
4846 | 4854 | ||
4855 | out: | ||
4856 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | ||
4847 | return ret; | 4857 | return ret; |
4848 | } | 4858 | } |
4849 | 4859 | ||
@@ -4877,6 +4887,14 @@ int i915_gem_init(struct drm_device *dev) | |||
4877 | dev_priv->gt.stop_ring = intel_logical_ring_stop; | 4887 | dev_priv->gt.stop_ring = intel_logical_ring_stop; |
4878 | } | 4888 | } |
4879 | 4889 | ||
4890 | /* This is just a security blanket to placate dragons. | ||
4891 | * On some systems, we very sporadically observe that the first TLBs | ||
4892 | * used by the CS may be stale, despite us poking the TLB reset. If | ||
4893 | * we hold the forcewake during initialisation these problems | ||
4894 | * just magically go away. | ||
4895 | */ | ||
4896 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | ||
4897 | |||
4880 | ret = i915_gem_init_userptr(dev); | 4898 | ret = i915_gem_init_userptr(dev); |
4881 | if (ret) | 4899 | if (ret) |
4882 | goto out_unlock; | 4900 | goto out_unlock; |
@@ -4903,6 +4921,7 @@ int i915_gem_init(struct drm_device *dev) | |||
4903 | } | 4921 | } |
4904 | 4922 | ||
4905 | out_unlock: | 4923 | out_unlock: |
4924 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | ||
4906 | mutex_unlock(&dev->struct_mutex); | 4925 | mutex_unlock(&dev->struct_mutex); |
4907 | 4926 | ||
4908 | return ret; | 4927 | return ret; |
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 746f77fb57a3..dccdc8aad2e2 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c | |||
@@ -1145,7 +1145,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |||
1145 | 1145 | ||
1146 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); | 1146 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
1147 | 1147 | ||
1148 | DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n", | 1148 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
1149 | ppgtt->node.size >> 20, | 1149 | ppgtt->node.size >> 20, |
1150 | ppgtt->node.start / PAGE_SIZE); | 1150 | ppgtt->node.start / PAGE_SIZE); |
1151 | 1151 | ||
@@ -1713,8 +1713,8 @@ void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |||
1713 | 1713 | ||
1714 | static void i915_gtt_color_adjust(struct drm_mm_node *node, | 1714 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1715 | unsigned long color, | 1715 | unsigned long color, |
1716 | unsigned long *start, | 1716 | u64 *start, |
1717 | unsigned long *end) | 1717 | u64 *end) |
1718 | { | 1718 | { |
1719 | if (node->color != color) | 1719 | if (node->color != color) |
1720 | *start += 4096; | 1720 | *start += 4096; |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e730789b53b7..f75173c20f47 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -37,6 +37,7 @@ | |||
37 | #include <drm/i915_drm.h> | 37 | #include <drm/i915_drm.h> |
38 | #include "i915_drv.h" | 38 | #include "i915_drv.h" |
39 | #include "i915_trace.h" | 39 | #include "i915_trace.h" |
40 | #include <drm/drm_atomic.h> | ||
40 | #include <drm/drm_atomic_helper.h> | 41 | #include <drm/drm_atomic_helper.h> |
41 | #include <drm/drm_dp_helper.h> | 42 | #include <drm/drm_dp_helper.h> |
42 | #include <drm/drm_crtc_helper.h> | 43 | #include <drm/drm_crtc_helper.h> |
@@ -2416,6 +2417,14 @@ out_unref_obj: | |||
2416 | return false; | 2417 | return false; |
2417 | } | 2418 | } |
2418 | 2419 | ||
2420 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ | ||
2421 | static void | ||
2422 | update_state_fb(struct drm_plane *plane) | ||
2423 | { | ||
2424 | if (plane->fb != plane->state->fb) | ||
2425 | drm_atomic_set_fb_for_plane(plane->state, plane->fb); | ||
2426 | } | ||
2427 | |||
2419 | static void | 2428 | static void |
2420 | intel_find_plane_obj(struct intel_crtc *intel_crtc, | 2429 | intel_find_plane_obj(struct intel_crtc *intel_crtc, |
2421 | struct intel_initial_plane_config *plane_config) | 2430 | struct intel_initial_plane_config *plane_config) |
@@ -2429,8 +2438,15 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc, | |||
2429 | if (!intel_crtc->base.primary->fb) | 2438 | if (!intel_crtc->base.primary->fb) |
2430 | return; | 2439 | return; |
2431 | 2440 | ||
2432 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) | 2441 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) { |
2442 | struct drm_plane *primary = intel_crtc->base.primary; | ||
2443 | |||
2444 | primary->state->crtc = &intel_crtc->base; | ||
2445 | primary->crtc = &intel_crtc->base; | ||
2446 | update_state_fb(primary); | ||
2447 | |||
2433 | return; | 2448 | return; |
2449 | } | ||
2434 | 2450 | ||
2435 | kfree(intel_crtc->base.primary->fb); | 2451 | kfree(intel_crtc->base.primary->fb); |
2436 | intel_crtc->base.primary->fb = NULL; | 2452 | intel_crtc->base.primary->fb = NULL; |
@@ -2453,15 +2469,21 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc, | |||
2453 | continue; | 2469 | continue; |
2454 | 2470 | ||
2455 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { | 2471 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
2472 | struct drm_plane *primary = intel_crtc->base.primary; | ||
2473 | |||
2456 | if (obj->tiling_mode != I915_TILING_NONE) | 2474 | if (obj->tiling_mode != I915_TILING_NONE) |
2457 | dev_priv->preserve_bios_swizzle = true; | 2475 | dev_priv->preserve_bios_swizzle = true; |
2458 | 2476 | ||
2459 | drm_framebuffer_reference(c->primary->fb); | 2477 | drm_framebuffer_reference(c->primary->fb); |
2460 | intel_crtc->base.primary->fb = c->primary->fb; | 2478 | primary->fb = c->primary->fb; |
2479 | primary->state->crtc = &intel_crtc->base; | ||
2480 | primary->crtc = &intel_crtc->base; | ||
2461 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | 2481 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); |
2462 | break; | 2482 | break; |
2463 | } | 2483 | } |
2464 | } | 2484 | } |
2485 | |||
2486 | update_state_fb(intel_crtc->base.primary); | ||
2465 | } | 2487 | } |
2466 | 2488 | ||
2467 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, | 2489 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
@@ -6602,6 +6624,10 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |||
6602 | struct drm_framebuffer *fb; | 6624 | struct drm_framebuffer *fb; |
6603 | struct intel_framebuffer *intel_fb; | 6625 | struct intel_framebuffer *intel_fb; |
6604 | 6626 | ||
6627 | val = I915_READ(DSPCNTR(plane)); | ||
6628 | if (!(val & DISPLAY_PLANE_ENABLE)) | ||
6629 | return; | ||
6630 | |||
6605 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | 6631 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
6606 | if (!intel_fb) { | 6632 | if (!intel_fb) { |
6607 | DRM_DEBUG_KMS("failed to alloc fb\n"); | 6633 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
@@ -6610,8 +6636,6 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |||
6610 | 6636 | ||
6611 | fb = &intel_fb->base; | 6637 | fb = &intel_fb->base; |
6612 | 6638 | ||
6613 | val = I915_READ(DSPCNTR(plane)); | ||
6614 | |||
6615 | if (INTEL_INFO(dev)->gen >= 4) | 6639 | if (INTEL_INFO(dev)->gen >= 4) |
6616 | if (val & DISPPLANE_TILED) | 6640 | if (val & DISPPLANE_TILED) |
6617 | plane_config->tiling = I915_TILING_X; | 6641 | plane_config->tiling = I915_TILING_X; |
@@ -7643,6 +7667,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, | |||
7643 | fb = &intel_fb->base; | 7667 | fb = &intel_fb->base; |
7644 | 7668 | ||
7645 | val = I915_READ(PLANE_CTL(pipe, 0)); | 7669 | val = I915_READ(PLANE_CTL(pipe, 0)); |
7670 | if (!(val & PLANE_CTL_ENABLE)) | ||
7671 | goto error; | ||
7672 | |||
7646 | if (val & PLANE_CTL_TILED_MASK) | 7673 | if (val & PLANE_CTL_TILED_MASK) |
7647 | plane_config->tiling = I915_TILING_X; | 7674 | plane_config->tiling = I915_TILING_X; |
7648 | 7675 | ||
@@ -7730,6 +7757,10 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |||
7730 | struct drm_framebuffer *fb; | 7757 | struct drm_framebuffer *fb; |
7731 | struct intel_framebuffer *intel_fb; | 7758 | struct intel_framebuffer *intel_fb; |
7732 | 7759 | ||
7760 | val = I915_READ(DSPCNTR(pipe)); | ||
7761 | if (!(val & DISPLAY_PLANE_ENABLE)) | ||
7762 | return; | ||
7763 | |||
7733 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | 7764 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
7734 | if (!intel_fb) { | 7765 | if (!intel_fb) { |
7735 | DRM_DEBUG_KMS("failed to alloc fb\n"); | 7766 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
@@ -7738,8 +7769,6 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |||
7738 | 7769 | ||
7739 | fb = &intel_fb->base; | 7770 | fb = &intel_fb->base; |
7740 | 7771 | ||
7741 | val = I915_READ(DSPCNTR(pipe)); | ||
7742 | |||
7743 | if (INTEL_INFO(dev)->gen >= 4) | 7772 | if (INTEL_INFO(dev)->gen >= 4) |
7744 | if (val & DISPPLANE_TILED) | 7773 | if (val & DISPPLANE_TILED) |
7745 | plane_config->tiling = I915_TILING_X; | 7774 | plane_config->tiling = I915_TILING_X; |
@@ -9716,7 +9745,7 @@ void intel_check_page_flip(struct drm_device *dev, int pipe) | |||
9716 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | 9745 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
9717 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | 9746 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9718 | 9747 | ||
9719 | WARN_ON(!in_irq()); | 9748 | WARN_ON(!in_interrupt()); |
9720 | 9749 | ||
9721 | if (crtc == NULL) | 9750 | if (crtc == NULL) |
9722 | return; | 9751 | return; |
@@ -9816,6 +9845,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, | |||
9816 | drm_gem_object_reference(&obj->base); | 9845 | drm_gem_object_reference(&obj->base); |
9817 | 9846 | ||
9818 | crtc->primary->fb = fb; | 9847 | crtc->primary->fb = fb; |
9848 | update_state_fb(crtc->primary); | ||
9819 | 9849 | ||
9820 | work->pending_flip_obj = obj; | 9850 | work->pending_flip_obj = obj; |
9821 | 9851 | ||
@@ -9884,6 +9914,7 @@ cleanup_unpin: | |||
9884 | cleanup_pending: | 9914 | cleanup_pending: |
9885 | atomic_dec(&intel_crtc->unpin_work_count); | 9915 | atomic_dec(&intel_crtc->unpin_work_count); |
9886 | crtc->primary->fb = old_fb; | 9916 | crtc->primary->fb = old_fb; |
9917 | update_state_fb(crtc->primary); | ||
9887 | drm_gem_object_unreference(&work->old_fb_obj->base); | 9918 | drm_gem_object_unreference(&work->old_fb_obj->base); |
9888 | drm_gem_object_unreference(&obj->base); | 9919 | drm_gem_object_unreference(&obj->base); |
9889 | mutex_unlock(&dev->struct_mutex); | 9920 | mutex_unlock(&dev->struct_mutex); |
@@ -13718,6 +13749,7 @@ void intel_modeset_gem_init(struct drm_device *dev) | |||
13718 | to_intel_crtc(c)->pipe); | 13749 | to_intel_crtc(c)->pipe); |
13719 | drm_framebuffer_unreference(c->primary->fb); | 13750 | drm_framebuffer_unreference(c->primary->fb); |
13720 | c->primary->fb = NULL; | 13751 | c->primary->fb = NULL; |
13752 | update_state_fb(c->primary); | ||
13721 | } | 13753 | } |
13722 | } | 13754 | } |
13723 | mutex_unlock(&dev->struct_mutex); | 13755 | mutex_unlock(&dev->struct_mutex); |
diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c index 04e248dd2259..54daa66c6970 100644 --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c | |||
@@ -282,16 +282,6 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, | |||
282 | return ret; | 282 | return ret; |
283 | } | 283 | } |
284 | 284 | ||
285 | static bool | ||
286 | __cpu_fifo_underrun_reporting_enabled(struct drm_i915_private *dev_priv, | ||
287 | enum pipe pipe) | ||
288 | { | ||
289 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | ||
290 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | ||
291 | |||
292 | return !intel_crtc->cpu_fifo_underrun_disabled; | ||
293 | } | ||
294 | |||
295 | /** | 285 | /** |
296 | * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state | 286 | * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state |
297 | * @dev_priv: i915 device instance | 287 | * @dev_priv: i915 device instance |
@@ -352,9 +342,15 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, | |||
352 | void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, | 342 | void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
353 | enum pipe pipe) | 343 | enum pipe pipe) |
354 | { | 344 | { |
345 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | ||
346 | |||
347 | /* We may be called too early in init, thanks BIOS! */ | ||
348 | if (crtc == NULL) | ||
349 | return; | ||
350 | |||
355 | /* GMCH can't disable fifo underruns, filter them. */ | 351 | /* GMCH can't disable fifo underruns, filter them. */ |
356 | if (HAS_GMCH_DISPLAY(dev_priv->dev) && | 352 | if (HAS_GMCH_DISPLAY(dev_priv->dev) && |
357 | !__cpu_fifo_underrun_reporting_enabled(dev_priv, pipe)) | 353 | to_intel_crtc(crtc)->cpu_fifo_underrun_disabled) |
358 | return; | 354 | return; |
359 | 355 | ||
360 | if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) | 356 | if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) |
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index c47a3baa53d5..4e8fb891d4ea 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c | |||
@@ -1048,8 +1048,14 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev) | |||
1048 | 1048 | ||
1049 | /* We need to init first for ECOBUS access and then | 1049 | /* We need to init first for ECOBUS access and then |
1050 | * determine later if we want to reinit, in case of MT access is | 1050 | * determine later if we want to reinit, in case of MT access is |
1051 | * not working | 1051 | * not working. In this stage we don't know which flavour this |
1052 | * ivb is, so it is better to reset also the gen6 fw registers | ||
1053 | * before the ecobus check. | ||
1052 | */ | 1054 | */ |
1055 | |||
1056 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); | ||
1057 | __raw_posting_read(dev_priv, ECOBUS); | ||
1058 | |||
1053 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, | 1059 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1054 | FORCEWAKE_MT, FORCEWAKE_MT_ACK); | 1060 | FORCEWAKE_MT, FORCEWAKE_MT_ACK); |
1055 | 1061 | ||
diff --git a/drivers/gpu/drm/imx/dw_hdmi-imx.c b/drivers/gpu/drm/imx/dw_hdmi-imx.c index 121d30ca2d44..87fe8ed92ebe 100644 --- a/drivers/gpu/drm/imx/dw_hdmi-imx.c +++ b/drivers/gpu/drm/imx/dw_hdmi-imx.c | |||
@@ -70,7 +70,9 @@ static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = { | |||
70 | 118800000, { 0x091c, 0x091c, 0x06dc }, | 70 | 118800000, { 0x091c, 0x091c, 0x06dc }, |
71 | }, { | 71 | }, { |
72 | 216000000, { 0x06dc, 0x0b5c, 0x091c }, | 72 | 216000000, { 0x06dc, 0x0b5c, 0x091c }, |
73 | } | 73 | }, { |
74 | ~0UL, { 0x0000, 0x0000, 0x0000 }, | ||
75 | }, | ||
74 | }; | 76 | }; |
75 | 77 | ||
76 | static const struct dw_hdmi_sym_term imx_sym_term[] = { | 78 | static const struct dw_hdmi_sym_term imx_sym_term[] = { |
@@ -136,11 +138,34 @@ static struct drm_encoder_funcs dw_hdmi_imx_encoder_funcs = { | |||
136 | .destroy = drm_encoder_cleanup, | 138 | .destroy = drm_encoder_cleanup, |
137 | }; | 139 | }; |
138 | 140 | ||
141 | static enum drm_mode_status imx6q_hdmi_mode_valid(struct drm_connector *con, | ||
142 | struct drm_display_mode *mode) | ||
143 | { | ||
144 | if (mode->clock < 13500) | ||
145 | return MODE_CLOCK_LOW; | ||
146 | if (mode->clock > 266000) | ||
147 | return MODE_CLOCK_HIGH; | ||
148 | |||
149 | return MODE_OK; | ||
150 | } | ||
151 | |||
152 | static enum drm_mode_status imx6dl_hdmi_mode_valid(struct drm_connector *con, | ||
153 | struct drm_display_mode *mode) | ||
154 | { | ||
155 | if (mode->clock < 13500) | ||
156 | return MODE_CLOCK_LOW; | ||
157 | if (mode->clock > 270000) | ||
158 | return MODE_CLOCK_HIGH; | ||
159 | |||
160 | return MODE_OK; | ||
161 | } | ||
162 | |||
139 | static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = { | 163 | static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = { |
140 | .mpll_cfg = imx_mpll_cfg, | 164 | .mpll_cfg = imx_mpll_cfg, |
141 | .cur_ctr = imx_cur_ctr, | 165 | .cur_ctr = imx_cur_ctr, |
142 | .sym_term = imx_sym_term, | 166 | .sym_term = imx_sym_term, |
143 | .dev_type = IMX6Q_HDMI, | 167 | .dev_type = IMX6Q_HDMI, |
168 | .mode_valid = imx6q_hdmi_mode_valid, | ||
144 | }; | 169 | }; |
145 | 170 | ||
146 | static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = { | 171 | static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = { |
@@ -148,6 +173,7 @@ static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = { | |||
148 | .cur_ctr = imx_cur_ctr, | 173 | .cur_ctr = imx_cur_ctr, |
149 | .sym_term = imx_sym_term, | 174 | .sym_term = imx_sym_term, |
150 | .dev_type = IMX6DL_HDMI, | 175 | .dev_type = IMX6DL_HDMI, |
176 | .mode_valid = imx6dl_hdmi_mode_valid, | ||
151 | }; | 177 | }; |
152 | 178 | ||
153 | static const struct of_device_id dw_hdmi_imx_dt_ids[] = { | 179 | static const struct of_device_id dw_hdmi_imx_dt_ids[] = { |
diff --git a/drivers/gpu/drm/imx/imx-ldb.c b/drivers/gpu/drm/imx/imx-ldb.c index 1b86aac0b341..2d6dc94e1e64 100644 --- a/drivers/gpu/drm/imx/imx-ldb.c +++ b/drivers/gpu/drm/imx/imx-ldb.c | |||
@@ -163,22 +163,7 @@ static void imx_ldb_encoder_prepare(struct drm_encoder *encoder) | |||
163 | { | 163 | { |
164 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | 164 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); |
165 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | 165 | struct imx_ldb *ldb = imx_ldb_ch->ldb; |
166 | struct drm_display_mode *mode = &encoder->crtc->hwmode; | ||
167 | u32 pixel_fmt; | 166 | u32 pixel_fmt; |
168 | unsigned long serial_clk; | ||
169 | unsigned long di_clk = mode->clock * 1000; | ||
170 | int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder); | ||
171 | |||
172 | if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) { | ||
173 | /* dual channel LVDS mode */ | ||
174 | serial_clk = 3500UL * mode->clock; | ||
175 | imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk); | ||
176 | imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk); | ||
177 | } else { | ||
178 | serial_clk = 7000UL * mode->clock; | ||
179 | imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk, | ||
180 | di_clk); | ||
181 | } | ||
182 | 167 | ||
183 | switch (imx_ldb_ch->chno) { | 168 | switch (imx_ldb_ch->chno) { |
184 | case 0: | 169 | case 0: |
@@ -247,6 +232,9 @@ static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder, | |||
247 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | 232 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); |
248 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | 233 | struct imx_ldb *ldb = imx_ldb_ch->ldb; |
249 | int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; | 234 | int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; |
235 | unsigned long serial_clk; | ||
236 | unsigned long di_clk = mode->clock * 1000; | ||
237 | int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder); | ||
250 | 238 | ||
251 | if (mode->clock > 170000) { | 239 | if (mode->clock > 170000) { |
252 | dev_warn(ldb->dev, | 240 | dev_warn(ldb->dev, |
@@ -257,6 +245,16 @@ static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder, | |||
257 | "%s: mode exceeds 85 MHz pixel clock\n", __func__); | 245 | "%s: mode exceeds 85 MHz pixel clock\n", __func__); |
258 | } | 246 | } |
259 | 247 | ||
248 | if (dual) { | ||
249 | serial_clk = 3500UL * mode->clock; | ||
250 | imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk); | ||
251 | imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk); | ||
252 | } else { | ||
253 | serial_clk = 7000UL * mode->clock; | ||
254 | imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk, | ||
255 | di_clk); | ||
256 | } | ||
257 | |||
260 | /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */ | 258 | /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */ |
261 | if (imx_ldb_ch == &ldb->channel[0]) { | 259 | if (imx_ldb_ch == &ldb->channel[0]) { |
262 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | 260 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
diff --git a/drivers/gpu/drm/imx/parallel-display.c b/drivers/gpu/drm/imx/parallel-display.c index 5e83e007080f..900dda6a8e71 100644 --- a/drivers/gpu/drm/imx/parallel-display.c +++ b/drivers/gpu/drm/imx/parallel-display.c | |||
@@ -236,8 +236,11 @@ static int imx_pd_bind(struct device *dev, struct device *master, void *data) | |||
236 | } | 236 | } |
237 | 237 | ||
238 | panel_node = of_parse_phandle(np, "fsl,panel", 0); | 238 | panel_node = of_parse_phandle(np, "fsl,panel", 0); |
239 | if (panel_node) | 239 | if (panel_node) { |
240 | imxpd->panel = of_drm_find_panel(panel_node); | 240 | imxpd->panel = of_drm_find_panel(panel_node); |
241 | if (!imxpd->panel) | ||
242 | return -EPROBE_DEFER; | ||
243 | } | ||
241 | 244 | ||
242 | imxpd->dev = dev; | 245 | imxpd->dev = dev; |
243 | 246 | ||
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_irq.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_irq.c index 8edd531cb621..7369ee7f0c55 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_irq.c +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_irq.c | |||
@@ -32,7 +32,10 @@ static void mdp4_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus) | |||
32 | void mdp4_irq_preinstall(struct msm_kms *kms) | 32 | void mdp4_irq_preinstall(struct msm_kms *kms) |
33 | { | 33 | { |
34 | struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); | 34 | struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); |
35 | mdp4_enable(mdp4_kms); | ||
35 | mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, 0xffffffff); | 36 | mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, 0xffffffff); |
37 | mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000); | ||
38 | mdp4_disable(mdp4_kms); | ||
36 | } | 39 | } |
37 | 40 | ||
38 | int mdp4_irq_postinstall(struct msm_kms *kms) | 41 | int mdp4_irq_postinstall(struct msm_kms *kms) |
@@ -53,7 +56,9 @@ int mdp4_irq_postinstall(struct msm_kms *kms) | |||
53 | void mdp4_irq_uninstall(struct msm_kms *kms) | 56 | void mdp4_irq_uninstall(struct msm_kms *kms) |
54 | { | 57 | { |
55 | struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); | 58 | struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); |
59 | mdp4_enable(mdp4_kms); | ||
56 | mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000); | 60 | mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000); |
61 | mdp4_disable(mdp4_kms); | ||
57 | } | 62 | } |
58 | 63 | ||
59 | irqreturn_t mdp4_irq(struct msm_kms *kms) | 64 | irqreturn_t mdp4_irq(struct msm_kms *kms) |
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h index 09b4a25eb553..c276624290af 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | |||
@@ -8,17 +8,9 @@ http://github.com/freedreno/envytools/ | |||
8 | git clone https://github.com/freedreno/envytools.git | 8 | git clone https://github.com/freedreno/envytools.git |
9 | 9 | ||
10 | The rules-ng-ng source files this header was generated from are: | 10 | The rules-ng-ng source files this header was generated from are: |
11 | - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) | 11 | - /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml ( 27229 bytes, from 2015-02-10 17:00:41) |
12 | - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) | 12 | - /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2014-06-02 18:31:15) |
13 | - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00) | 13 | - /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2015-01-23 16:20:19) |
14 | - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00) | ||
15 | - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11) | ||
16 | - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) | ||
17 | - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) | ||
18 | - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) | ||
19 | - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) | ||
20 | - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57) | ||
21 | - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00) | ||
22 | 14 | ||
23 | Copyright (C) 2013-2015 by the following authors: | 15 | Copyright (C) 2013-2015 by the following authors: |
24 | - Rob Clark <robdclark@gmail.com> (robclark) | 16 | - Rob Clark <robdclark@gmail.com> (robclark) |
@@ -910,6 +902,7 @@ static inline uint32_t __offset_LM(uint32_t idx) | |||
910 | case 2: return (mdp5_cfg->lm.base[2]); | 902 | case 2: return (mdp5_cfg->lm.base[2]); |
911 | case 3: return (mdp5_cfg->lm.base[3]); | 903 | case 3: return (mdp5_cfg->lm.base[3]); |
912 | case 4: return (mdp5_cfg->lm.base[4]); | 904 | case 4: return (mdp5_cfg->lm.base[4]); |
905 | case 5: return (mdp5_cfg->lm.base[5]); | ||
913 | default: return INVALID_IDX(idx); | 906 | default: return INVALID_IDX(idx); |
914 | } | 907 | } |
915 | } | 908 | } |
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c index 46fac545dc2b..2f2863cf8b45 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | |||
@@ -62,8 +62,8 @@ struct mdp5_crtc { | |||
62 | 62 | ||
63 | /* current cursor being scanned out: */ | 63 | /* current cursor being scanned out: */ |
64 | struct drm_gem_object *scanout_bo; | 64 | struct drm_gem_object *scanout_bo; |
65 | uint32_t width; | 65 | uint32_t width, height; |
66 | uint32_t height; | 66 | uint32_t x, y; |
67 | } cursor; | 67 | } cursor; |
68 | }; | 68 | }; |
69 | #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base) | 69 | #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base) |
@@ -103,8 +103,8 @@ static void crtc_flush_all(struct drm_crtc *crtc) | |||
103 | struct drm_plane *plane; | 103 | struct drm_plane *plane; |
104 | uint32_t flush_mask = 0; | 104 | uint32_t flush_mask = 0; |
105 | 105 | ||
106 | /* we could have already released CTL in the disable path: */ | 106 | /* this should not happen: */ |
107 | if (!mdp5_crtc->ctl) | 107 | if (WARN_ON(!mdp5_crtc->ctl)) |
108 | return; | 108 | return; |
109 | 109 | ||
110 | drm_atomic_crtc_for_each_plane(plane, crtc) { | 110 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
@@ -143,6 +143,11 @@ static void complete_flip(struct drm_crtc *crtc, struct drm_file *file) | |||
143 | drm_atomic_crtc_for_each_plane(plane, crtc) { | 143 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
144 | mdp5_plane_complete_flip(plane); | 144 | mdp5_plane_complete_flip(plane); |
145 | } | 145 | } |
146 | |||
147 | if (mdp5_crtc->ctl && !crtc->state->enable) { | ||
148 | mdp5_ctl_release(mdp5_crtc->ctl); | ||
149 | mdp5_crtc->ctl = NULL; | ||
150 | } | ||
146 | } | 151 | } |
147 | 152 | ||
148 | static void unref_cursor_worker(struct drm_flip_work *work, void *val) | 153 | static void unref_cursor_worker(struct drm_flip_work *work, void *val) |
@@ -386,14 +391,17 @@ static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc) | |||
386 | mdp5_crtc->event = crtc->state->event; | 391 | mdp5_crtc->event = crtc->state->event; |
387 | spin_unlock_irqrestore(&dev->event_lock, flags); | 392 | spin_unlock_irqrestore(&dev->event_lock, flags); |
388 | 393 | ||
394 | /* | ||
395 | * If no CTL has been allocated in mdp5_crtc_atomic_check(), | ||
396 | * it means we are trying to flush a CRTC whose state is disabled: | ||
397 | * nothing else needs to be done. | ||
398 | */ | ||
399 | if (unlikely(!mdp5_crtc->ctl)) | ||
400 | return; | ||
401 | |||
389 | blend_setup(crtc); | 402 | blend_setup(crtc); |
390 | crtc_flush_all(crtc); | 403 | crtc_flush_all(crtc); |
391 | request_pending(crtc, PENDING_FLIP); | 404 | request_pending(crtc, PENDING_FLIP); |
392 | |||
393 | if (mdp5_crtc->ctl && !crtc->state->enable) { | ||
394 | mdp5_ctl_release(mdp5_crtc->ctl); | ||
395 | mdp5_crtc->ctl = NULL; | ||
396 | } | ||
397 | } | 405 | } |
398 | 406 | ||
399 | static int mdp5_crtc_set_property(struct drm_crtc *crtc, | 407 | static int mdp5_crtc_set_property(struct drm_crtc *crtc, |
@@ -403,6 +411,32 @@ static int mdp5_crtc_set_property(struct drm_crtc *crtc, | |||
403 | return -EINVAL; | 411 | return -EINVAL; |
404 | } | 412 | } |
405 | 413 | ||
414 | static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h) | ||
415 | { | ||
416 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | ||
417 | uint32_t xres = crtc->mode.hdisplay; | ||
418 | uint32_t yres = crtc->mode.vdisplay; | ||
419 | |||
420 | /* | ||
421 | * Cursor Region Of Interest (ROI) is a plane read from cursor | ||
422 | * buffer to render. The ROI region is determined by the visibility of | ||
423 | * the cursor point. In the default Cursor image the cursor point will | ||
424 | * be at the top left of the cursor image, unless it is specified | ||
425 | * otherwise using hotspot feature. | ||
426 | * | ||
427 | * If the cursor point reaches the right (xres - x < cursor.width) or | ||
428 | * bottom (yres - y < cursor.height) boundary of the screen, then ROI | ||
429 | * width and ROI height need to be evaluated to crop the cursor image | ||
430 | * accordingly. | ||
431 | * (xres-x) will be new cursor width when x > (xres - cursor.width) | ||
432 | * (yres-y) will be new cursor height when y > (yres - cursor.height) | ||
433 | */ | ||
434 | *roi_w = min(mdp5_crtc->cursor.width, xres - | ||
435 | mdp5_crtc->cursor.x); | ||
436 | *roi_h = min(mdp5_crtc->cursor.height, yres - | ||
437 | mdp5_crtc->cursor.y); | ||
438 | } | ||
439 | |||
406 | static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, | 440 | static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, |
407 | struct drm_file *file, uint32_t handle, | 441 | struct drm_file *file, uint32_t handle, |
408 | uint32_t width, uint32_t height) | 442 | uint32_t width, uint32_t height) |
@@ -416,6 +450,7 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, | |||
416 | unsigned int depth; | 450 | unsigned int depth; |
417 | enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL; | 451 | enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL; |
418 | uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); | 452 | uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); |
453 | uint32_t roi_w, roi_h; | ||
419 | unsigned long flags; | 454 | unsigned long flags; |
420 | 455 | ||
421 | if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) { | 456 | if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) { |
@@ -446,6 +481,12 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, | |||
446 | spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); | 481 | spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); |
447 | old_bo = mdp5_crtc->cursor.scanout_bo; | 482 | old_bo = mdp5_crtc->cursor.scanout_bo; |
448 | 483 | ||
484 | mdp5_crtc->cursor.scanout_bo = cursor_bo; | ||
485 | mdp5_crtc->cursor.width = width; | ||
486 | mdp5_crtc->cursor.height = height; | ||
487 | |||
488 | get_roi(crtc, &roi_w, &roi_h); | ||
489 | |||
449 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride); | 490 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride); |
450 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm), | 491 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm), |
451 | MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888)); | 492 | MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888)); |
@@ -453,19 +494,14 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, | |||
453 | MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) | | 494 | MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) | |
454 | MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width)); | 495 | MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width)); |
455 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm), | 496 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm), |
456 | MDP5_LM_CURSOR_SIZE_ROI_H(height) | | 497 | MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) | |
457 | MDP5_LM_CURSOR_SIZE_ROI_W(width)); | 498 | MDP5_LM_CURSOR_SIZE_ROI_W(roi_w)); |
458 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm), cursor_addr); | 499 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm), cursor_addr); |
459 | 500 | ||
460 | |||
461 | blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN; | 501 | blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN; |
462 | blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_TRANSP_EN; | ||
463 | blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha); | 502 | blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha); |
464 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg); | 503 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg); |
465 | 504 | ||
466 | mdp5_crtc->cursor.scanout_bo = cursor_bo; | ||
467 | mdp5_crtc->cursor.width = width; | ||
468 | mdp5_crtc->cursor.height = height; | ||
469 | spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags); | 505 | spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags); |
470 | 506 | ||
471 | ret = mdp5_ctl_set_cursor(mdp5_crtc->ctl, true); | 507 | ret = mdp5_ctl_set_cursor(mdp5_crtc->ctl, true); |
@@ -489,31 +525,18 @@ static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |||
489 | struct mdp5_kms *mdp5_kms = get_kms(crtc); | 525 | struct mdp5_kms *mdp5_kms = get_kms(crtc); |
490 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | 526 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); |
491 | uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); | 527 | uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); |
492 | uint32_t xres = crtc->mode.hdisplay; | ||
493 | uint32_t yres = crtc->mode.vdisplay; | ||
494 | uint32_t roi_w; | 528 | uint32_t roi_w; |
495 | uint32_t roi_h; | 529 | uint32_t roi_h; |
496 | unsigned long flags; | 530 | unsigned long flags; |
497 | 531 | ||
498 | x = (x > 0) ? x : 0; | 532 | /* In case the CRTC is disabled, just drop the cursor update */ |
499 | y = (y > 0) ? y : 0; | 533 | if (unlikely(!crtc->state->enable)) |
534 | return 0; | ||
500 | 535 | ||
501 | /* | 536 | mdp5_crtc->cursor.x = x = max(x, 0); |
502 | * Cursor Region Of Interest (ROI) is a plane read from cursor | 537 | mdp5_crtc->cursor.y = y = max(y, 0); |
503 | * buffer to render. The ROI region is determined by the visiblity of | 538 | |
504 | * the cursor point. In the default Cursor image the cursor point will | 539 | get_roi(crtc, &roi_w, &roi_h); |
505 | * be at the top left of the cursor image, unless it is specified | ||
506 | * otherwise using hotspot feature. | ||
507 | * | ||
508 | * If the cursor point reaches the right (xres - x < cursor.width) or | ||
509 | * bottom (yres - y < cursor.height) boundary of the screen, then ROI | ||
510 | * width and ROI height need to be evaluated to crop the cursor image | ||
511 | * accordingly. | ||
512 | * (xres-x) will be new cursor width when x > (xres - cursor.width) | ||
513 | * (yres-y) will be new cursor height when y > (yres - cursor.height) | ||
514 | */ | ||
515 | roi_w = min(mdp5_crtc->cursor.width, xres - x); | ||
516 | roi_h = min(mdp5_crtc->cursor.height, yres - y); | ||
517 | 540 | ||
518 | spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); | 541 | spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); |
519 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(mdp5_crtc->lm), | 542 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(mdp5_crtc->lm), |
@@ -544,8 +567,8 @@ static const struct drm_crtc_funcs mdp5_crtc_funcs = { | |||
544 | static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = { | 567 | static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = { |
545 | .mode_fixup = mdp5_crtc_mode_fixup, | 568 | .mode_fixup = mdp5_crtc_mode_fixup, |
546 | .mode_set_nofb = mdp5_crtc_mode_set_nofb, | 569 | .mode_set_nofb = mdp5_crtc_mode_set_nofb, |
547 | .prepare = mdp5_crtc_disable, | 570 | .disable = mdp5_crtc_disable, |
548 | .commit = mdp5_crtc_enable, | 571 | .enable = mdp5_crtc_enable, |
549 | .atomic_check = mdp5_crtc_atomic_check, | 572 | .atomic_check = mdp5_crtc_atomic_check, |
550 | .atomic_begin = mdp5_crtc_atomic_begin, | 573 | .atomic_begin = mdp5_crtc_atomic_begin, |
551 | .atomic_flush = mdp5_crtc_atomic_flush, | 574 | .atomic_flush = mdp5_crtc_atomic_flush, |
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c index d6a14bb99988..af0e02fa4f48 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | |||
@@ -267,14 +267,14 @@ static void mdp5_encoder_enable(struct drm_encoder *encoder) | |||
267 | mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intf), 1); | 267 | mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intf), 1); |
268 | spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags); | 268 | spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags); |
269 | 269 | ||
270 | mdp5_encoder->enabled = false; | 270 | mdp5_encoder->enabled = true; |
271 | } | 271 | } |
272 | 272 | ||
273 | static const struct drm_encoder_helper_funcs mdp5_encoder_helper_funcs = { | 273 | static const struct drm_encoder_helper_funcs mdp5_encoder_helper_funcs = { |
274 | .mode_fixup = mdp5_encoder_mode_fixup, | 274 | .mode_fixup = mdp5_encoder_mode_fixup, |
275 | .mode_set = mdp5_encoder_mode_set, | 275 | .mode_set = mdp5_encoder_mode_set, |
276 | .prepare = mdp5_encoder_disable, | 276 | .disable = mdp5_encoder_disable, |
277 | .commit = mdp5_encoder_enable, | 277 | .enable = mdp5_encoder_enable, |
278 | }; | 278 | }; |
279 | 279 | ||
280 | /* initialize encoder */ | 280 | /* initialize encoder */ |
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c index 70ac81edd40f..a9407105b9b7 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c | |||
@@ -34,7 +34,10 @@ static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus) | |||
34 | void mdp5_irq_preinstall(struct msm_kms *kms) | 34 | void mdp5_irq_preinstall(struct msm_kms *kms) |
35 | { | 35 | { |
36 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | 36 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); |
37 | mdp5_enable(mdp5_kms); | ||
37 | mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff); | 38 | mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff); |
39 | mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000); | ||
40 | mdp5_disable(mdp5_kms); | ||
38 | } | 41 | } |
39 | 42 | ||
40 | int mdp5_irq_postinstall(struct msm_kms *kms) | 43 | int mdp5_irq_postinstall(struct msm_kms *kms) |
@@ -57,7 +60,9 @@ int mdp5_irq_postinstall(struct msm_kms *kms) | |||
57 | void mdp5_irq_uninstall(struct msm_kms *kms) | 60 | void mdp5_irq_uninstall(struct msm_kms *kms) |
58 | { | 61 | { |
59 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | 62 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); |
63 | mdp5_enable(mdp5_kms); | ||
60 | mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000); | 64 | mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000); |
65 | mdp5_disable(mdp5_kms); | ||
61 | } | 66 | } |
62 | 67 | ||
63 | static void mdp5_irq_mdp(struct mdp_kms *mdp_kms) | 68 | static void mdp5_irq_mdp(struct mdp_kms *mdp_kms) |
diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c index 871aa2108dc6..18fd643b6e69 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c | |||
@@ -219,8 +219,10 @@ int msm_atomic_commit(struct drm_device *dev, | |||
219 | * mark our set of crtc's as busy: | 219 | * mark our set of crtc's as busy: |
220 | */ | 220 | */ |
221 | ret = start_atomic(dev->dev_private, c->crtc_mask); | 221 | ret = start_atomic(dev->dev_private, c->crtc_mask); |
222 | if (ret) | 222 | if (ret) { |
223 | kfree(c); | ||
223 | return ret; | 224 | return ret; |
225 | } | ||
224 | 226 | ||
225 | /* | 227 | /* |
226 | * This is the point of no return - everything below never fails except | 228 | * This is the point of no return - everything below never fails except |
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index 79924e4b1b49..6751553abe4a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c | |||
@@ -418,7 +418,7 @@ nouveau_fbcon_create(struct drm_fb_helper *helper, | |||
418 | nouveau_fbcon_zfill(dev, fbcon); | 418 | nouveau_fbcon_zfill(dev, fbcon); |
419 | 419 | ||
420 | /* To allow resizeing without swapping buffers */ | 420 | /* To allow resizeing without swapping buffers */ |
421 | NV_INFO(drm, "allocated %dx%d fb: 0x%lx, bo %p\n", | 421 | NV_INFO(drm, "allocated %dx%d fb: 0x%llx, bo %p\n", |
422 | nouveau_fb->base.width, nouveau_fb->base.height, | 422 | nouveau_fb->base.width, nouveau_fb->base.height, |
423 | nvbo->bo.offset, nvbo); | 423 | nvbo->bo.offset, nvbo); |
424 | 424 | ||
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 29bd539af183..6efa8f38ff54 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | |||
@@ -340,11 +340,13 @@ nvkm_devobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, | |||
340 | 340 | ||
341 | /* switch mmio to cpu's native endianness */ | 341 | /* switch mmio to cpu's native endianness */ |
342 | #ifndef __BIG_ENDIAN | 342 | #ifndef __BIG_ENDIAN |
343 | if (ioread32_native(map + 0x000004) != 0x00000000) | 343 | if (ioread32_native(map + 0x000004) != 0x00000000) { |
344 | #else | 344 | #else |
345 | if (ioread32_native(map + 0x000004) == 0x00000000) | 345 | if (ioread32_native(map + 0x000004) == 0x00000000) { |
346 | #endif | 346 | #endif |
347 | iowrite32_native(0x01000001, map + 0x000004); | 347 | iowrite32_native(0x01000001, map + 0x000004); |
348 | ioread32_native(map); | ||
349 | } | ||
348 | 350 | ||
349 | /* read boot0 and strapping information */ | 351 | /* read boot0 and strapping information */ |
350 | boot0 = ioread32_native(map + 0x000000); | 352 | boot0 = ioread32_native(map + 0x000000); |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index 539561ed3281..108d048da764 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | |||
@@ -142,6 +142,49 @@ gm100_identify(struct nvkm_device *device) | |||
142 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | 142 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; |
143 | #endif | 143 | #endif |
144 | break; | 144 | break; |
145 | case 0x126: | ||
146 | device->cname = "GM206"; | ||
147 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; | ||
148 | device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; | ||
149 | device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass; | ||
150 | device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass; | ||
151 | #if 0 | ||
152 | /* looks to be some non-trivial changes */ | ||
153 | device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; | ||
154 | /* priv ring says no to 0x10eb14 writes */ | ||
155 | device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; | ||
156 | #endif | ||
157 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | ||
158 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gm204_devinit_oclass; | ||
159 | device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; | ||
160 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; | ||
161 | device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; | ||
162 | device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass; | ||
163 | device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; | ||
164 | device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; | ||
165 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; | ||
166 | device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; | ||
167 | device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; | ||
168 | device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; | ||
169 | #if 0 | ||
170 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | ||
171 | #endif | ||
172 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; | ||
173 | #if 0 | ||
174 | device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; | ||
175 | device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; | ||
176 | device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; | ||
177 | #endif | ||
178 | device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass; | ||
179 | #if 0 | ||
180 | device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass; | ||
181 | device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass; | ||
182 | device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass; | ||
183 | device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; | ||
184 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; | ||
185 | device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; | ||
186 | #endif | ||
187 | break; | ||
145 | default: | 188 | default: |
146 | nv_fatal(device, "unknown Maxwell chipset\n"); | 189 | nv_fatal(device, "unknown Maxwell chipset\n"); |
147 | return -EINVAL; | 190 | return -EINVAL; |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c index b038b6eb51db..043e4296084c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c | |||
@@ -502,72 +502,57 @@ nv04_fifo_intr(struct nvkm_subdev *subdev) | |||
502 | { | 502 | { |
503 | struct nvkm_device *device = nv_device(subdev); | 503 | struct nvkm_device *device = nv_device(subdev); |
504 | struct nv04_fifo_priv *priv = (void *)subdev; | 504 | struct nv04_fifo_priv *priv = (void *)subdev; |
505 | uint32_t status, reassign; | 505 | u32 mask = nv_rd32(priv, NV03_PFIFO_INTR_EN_0); |
506 | int cnt = 0; | 506 | u32 stat = nv_rd32(priv, NV03_PFIFO_INTR_0) & mask; |
507 | u32 reassign, chid, get, sem; | ||
507 | 508 | ||
508 | reassign = nv_rd32(priv, NV03_PFIFO_CACHES) & 1; | 509 | reassign = nv_rd32(priv, NV03_PFIFO_CACHES) & 1; |
509 | while ((status = nv_rd32(priv, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) { | 510 | nv_wr32(priv, NV03_PFIFO_CACHES, 0); |
510 | uint32_t chid, get; | ||
511 | |||
512 | nv_wr32(priv, NV03_PFIFO_CACHES, 0); | ||
513 | |||
514 | chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max; | ||
515 | get = nv_rd32(priv, NV03_PFIFO_CACHE1_GET); | ||
516 | 511 | ||
517 | if (status & NV_PFIFO_INTR_CACHE_ERROR) { | 512 | chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max; |
518 | nv04_fifo_cache_error(device, priv, chid, get); | 513 | get = nv_rd32(priv, NV03_PFIFO_CACHE1_GET); |
519 | status &= ~NV_PFIFO_INTR_CACHE_ERROR; | ||
520 | } | ||
521 | 514 | ||
522 | if (status & NV_PFIFO_INTR_DMA_PUSHER) { | 515 | if (stat & NV_PFIFO_INTR_CACHE_ERROR) { |
523 | nv04_fifo_dma_pusher(device, priv, chid); | 516 | nv04_fifo_cache_error(device, priv, chid, get); |
524 | status &= ~NV_PFIFO_INTR_DMA_PUSHER; | 517 | stat &= ~NV_PFIFO_INTR_CACHE_ERROR; |
525 | } | 518 | } |
526 | 519 | ||
527 | if (status & NV_PFIFO_INTR_SEMAPHORE) { | 520 | if (stat & NV_PFIFO_INTR_DMA_PUSHER) { |
528 | uint32_t sem; | 521 | nv04_fifo_dma_pusher(device, priv, chid); |
522 | stat &= ~NV_PFIFO_INTR_DMA_PUSHER; | ||
523 | } | ||
529 | 524 | ||
530 | status &= ~NV_PFIFO_INTR_SEMAPHORE; | 525 | if (stat & NV_PFIFO_INTR_SEMAPHORE) { |
531 | nv_wr32(priv, NV03_PFIFO_INTR_0, | 526 | stat &= ~NV_PFIFO_INTR_SEMAPHORE; |
532 | NV_PFIFO_INTR_SEMAPHORE); | 527 | nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_SEMAPHORE); |
533 | 528 | ||
534 | sem = nv_rd32(priv, NV10_PFIFO_CACHE1_SEMAPHORE); | 529 | sem = nv_rd32(priv, NV10_PFIFO_CACHE1_SEMAPHORE); |
535 | nv_wr32(priv, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1); | 530 | nv_wr32(priv, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1); |
536 | 531 | ||
537 | nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4); | 532 | nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4); |
538 | nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); | 533 | nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); |
539 | } | 534 | } |
540 | 535 | ||
541 | if (device->card_type == NV_50) { | 536 | if (device->card_type == NV_50) { |
542 | if (status & 0x00000010) { | 537 | if (stat & 0x00000010) { |
543 | status &= ~0x00000010; | 538 | stat &= ~0x00000010; |
544 | nv_wr32(priv, 0x002100, 0x00000010); | 539 | nv_wr32(priv, 0x002100, 0x00000010); |
545 | } | ||
546 | |||
547 | if (status & 0x40000000) { | ||
548 | nv_wr32(priv, 0x002100, 0x40000000); | ||
549 | nvkm_fifo_uevent(&priv->base); | ||
550 | status &= ~0x40000000; | ||
551 | } | ||
552 | } | 540 | } |
553 | 541 | ||
554 | if (status) { | 542 | if (stat & 0x40000000) { |
555 | nv_warn(priv, "unknown intr 0x%08x, ch %d\n", | 543 | nv_wr32(priv, 0x002100, 0x40000000); |
556 | status, chid); | 544 | nvkm_fifo_uevent(&priv->base); |
557 | nv_wr32(priv, NV03_PFIFO_INTR_0, status); | 545 | stat &= ~0x40000000; |
558 | status = 0; | ||
559 | } | 546 | } |
560 | |||
561 | nv_wr32(priv, NV03_PFIFO_CACHES, reassign); | ||
562 | } | 547 | } |
563 | 548 | ||
564 | if (status) { | 549 | if (stat) { |
565 | nv_error(priv, "still angry after %d spins, halt\n", cnt); | 550 | nv_warn(priv, "unknown intr 0x%08x\n", stat); |
566 | nv_wr32(priv, 0x002140, 0); | 551 | nv_mask(priv, NV03_PFIFO_INTR_EN_0, stat, 0x00000000); |
567 | nv_wr32(priv, 0x000140, 0); | 552 | nv_wr32(priv, NV03_PFIFO_INTR_0, stat); |
568 | } | 553 | } |
569 | 554 | ||
570 | nv_wr32(priv, 0x000100, 0x00000100); | 555 | nv_wr32(priv, NV03_PFIFO_CACHES, reassign); |
571 | } | 556 | } |
572 | 557 | ||
573 | static int | 558 | static int |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c index 2e7ec389eea7..57e2c5b13123 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c | |||
@@ -1032,9 +1032,9 @@ gf100_grctx_generate_bundle(struct gf100_grctx *info) | |||
1032 | const int s = 8; | 1032 | const int s = 8; |
1033 | const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); | 1033 | const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); |
1034 | mmio_refn(info, 0x408004, 0x00000000, s, b); | 1034 | mmio_refn(info, 0x408004, 0x00000000, s, b); |
1035 | mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b); | 1035 | mmio_wr32(info, 0x408008, 0x80000000 | (impl->bundle_size >> s)); |
1036 | mmio_refn(info, 0x418808, 0x00000000, s, b); | 1036 | mmio_refn(info, 0x418808, 0x00000000, s, b); |
1037 | mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b); | 1037 | mmio_wr32(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s)); |
1038 | } | 1038 | } |
1039 | 1039 | ||
1040 | void | 1040 | void |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c index b52300d8861a..5e9454ba158f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c | |||
@@ -851,9 +851,9 @@ gk104_grctx_generate_bundle(struct gf100_grctx *info) | |||
851 | const int s = 8; | 851 | const int s = 8; |
852 | const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); | 852 | const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); |
853 | mmio_refn(info, 0x408004, 0x00000000, s, b); | 853 | mmio_refn(info, 0x408004, 0x00000000, s, b); |
854 | mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b); | 854 | mmio_wr32(info, 0x408008, 0x80000000 | (impl->bundle_size >> s)); |
855 | mmio_refn(info, 0x418808, 0x00000000, s, b); | 855 | mmio_refn(info, 0x418808, 0x00000000, s, b); |
856 | mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b); | 856 | mmio_wr32(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s)); |
857 | mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit); | 857 | mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit); |
858 | } | 858 | } |
859 | 859 | ||
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c index 956f4dce960c..b2fae6e389e2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c | |||
@@ -871,9 +871,9 @@ gm107_grctx_generate_bundle(struct gf100_grctx *info) | |||
871 | const int s = 8; | 871 | const int s = 8; |
872 | const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); | 872 | const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); |
873 | mmio_refn(info, 0x408004, 0x00000000, s, b); | 873 | mmio_refn(info, 0x408004, 0x00000000, s, b); |
874 | mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b); | 874 | mmio_wr32(info, 0x408008, 0x80000000 | (impl->bundle_size >> s)); |
875 | mmio_refn(info, 0x418e24, 0x00000000, s, b); | 875 | mmio_refn(info, 0x418e24, 0x00000000, s, b); |
876 | mmio_refn(info, 0x418e28, 0x80000000 | (impl->bundle_size >> s), 0, b); | 876 | mmio_wr32(info, 0x418e28, 0x80000000 | (impl->bundle_size >> s)); |
877 | mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit); | 877 | mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit); |
878 | } | 878 | } |
879 | 879 | ||
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.c index d1a89b2bd5c1..c4e1f085ee10 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.c | |||
@@ -74,7 +74,11 @@ dcb_i2c_parse(struct nvkm_bios *bios, u8 idx, struct dcb_i2c_entry *info) | |||
74 | u16 ent = dcb_i2c_entry(bios, idx, &ver, &len); | 74 | u16 ent = dcb_i2c_entry(bios, idx, &ver, &len); |
75 | if (ent) { | 75 | if (ent) { |
76 | if (ver >= 0x41) { | 76 | if (ver >= 0x41) { |
77 | if (!(nv_ro32(bios, ent) & 0x80000000)) | 77 | u32 ent_value = nv_ro32(bios, ent); |
78 | u8 i2c_port = (ent_value >> 27) & 0x1f; | ||
79 | u8 dpaux_port = (ent_value >> 22) & 0x1f; | ||
80 | /* value 0x1f means unused according to DCB 4.x spec */ | ||
81 | if (i2c_port == 0x1f && dpaux_port == 0x1f) | ||
78 | info->type = DCB_I2C_UNUSED; | 82 | info->type = DCB_I2C_UNUSED; |
79 | else | 83 | else |
80 | info->type = DCB_I2C_PMGR; | 84 | info->type = DCB_I2C_PMGR; |
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index ed644a4f6f57..86807ee91bd1 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c | |||
@@ -1405,6 +1405,9 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, | |||
1405 | (x << 16) | y); | 1405 | (x << 16) | y); |
1406 | viewport_w = crtc->mode.hdisplay; | 1406 | viewport_w = crtc->mode.hdisplay; |
1407 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; | 1407 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; |
1408 | if ((rdev->family >= CHIP_BONAIRE) && | ||
1409 | (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)) | ||
1410 | viewport_h *= 2; | ||
1408 | WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, | 1411 | WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
1409 | (viewport_w << 16) | viewport_h); | 1412 | (viewport_w << 16) | viewport_h); |
1410 | 1413 | ||
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c index 7fe7b749e182..c39c1d0d9d4e 100644 --- a/drivers/gpu/drm/radeon/atombios_encoders.c +++ b/drivers/gpu/drm/radeon/atombios_encoders.c | |||
@@ -1626,7 +1626,6 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) | |||
1626 | struct radeon_connector *radeon_connector = NULL; | 1626 | struct radeon_connector *radeon_connector = NULL; |
1627 | struct radeon_connector_atom_dig *radeon_dig_connector = NULL; | 1627 | struct radeon_connector_atom_dig *radeon_dig_connector = NULL; |
1628 | bool travis_quirk = false; | 1628 | bool travis_quirk = false; |
1629 | int encoder_mode; | ||
1630 | 1629 | ||
1631 | if (connector) { | 1630 | if (connector) { |
1632 | radeon_connector = to_radeon_connector(connector); | 1631 | radeon_connector = to_radeon_connector(connector); |
@@ -1722,13 +1721,6 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) | |||
1722 | } | 1721 | } |
1723 | break; | 1722 | break; |
1724 | } | 1723 | } |
1725 | |||
1726 | encoder_mode = atombios_get_encoder_mode(encoder); | ||
1727 | if (connector && (radeon_audio != 0) && | ||
1728 | ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || | ||
1729 | (ENCODER_MODE_IS_DP(encoder_mode) && | ||
1730 | drm_detect_monitor_audio(radeon_connector_edid(connector))))) | ||
1731 | radeon_audio_dpms(encoder, mode); | ||
1732 | } | 1724 | } |
1733 | 1725 | ||
1734 | static void | 1726 | static void |
@@ -1737,10 +1729,19 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) | |||
1737 | struct drm_device *dev = encoder->dev; | 1729 | struct drm_device *dev = encoder->dev; |
1738 | struct radeon_device *rdev = dev->dev_private; | 1730 | struct radeon_device *rdev = dev->dev_private; |
1739 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 1731 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1732 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | ||
1733 | int encoder_mode = atombios_get_encoder_mode(encoder); | ||
1740 | 1734 | ||
1741 | DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", | 1735 | DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
1742 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, | 1736 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
1743 | radeon_encoder->active_device); | 1737 | radeon_encoder->active_device); |
1738 | |||
1739 | if (connector && (radeon_audio != 0) && | ||
1740 | ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || | ||
1741 | (ENCODER_MODE_IS_DP(encoder_mode) && | ||
1742 | drm_detect_monitor_audio(radeon_connector_edid(connector))))) | ||
1743 | radeon_audio_dpms(encoder, mode); | ||
1744 | |||
1744 | switch (radeon_encoder->encoder_id) { | 1745 | switch (radeon_encoder->encoder_id) { |
1745 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | 1746 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
1746 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | 1747 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
@@ -2170,12 +2171,6 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, | |||
2170 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: | 2171 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
2171 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | 2172 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2172 | /* handled in dpms */ | 2173 | /* handled in dpms */ |
2173 | encoder_mode = atombios_get_encoder_mode(encoder); | ||
2174 | if (connector && (radeon_audio != 0) && | ||
2175 | ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || | ||
2176 | (ENCODER_MODE_IS_DP(encoder_mode) && | ||
2177 | drm_detect_monitor_audio(radeon_connector_edid(connector))))) | ||
2178 | radeon_audio_mode_set(encoder, adjusted_mode); | ||
2179 | break; | 2174 | break; |
2180 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | 2175 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
2181 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | 2176 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
@@ -2197,6 +2192,13 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, | |||
2197 | } | 2192 | } |
2198 | 2193 | ||
2199 | atombios_apply_encoder_quirks(encoder, adjusted_mode); | 2194 | atombios_apply_encoder_quirks(encoder, adjusted_mode); |
2195 | |||
2196 | encoder_mode = atombios_get_encoder_mode(encoder); | ||
2197 | if (connector && (radeon_audio != 0) && | ||
2198 | ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || | ||
2199 | (ENCODER_MODE_IS_DP(encoder_mode) && | ||
2200 | drm_detect_monitor_audio(radeon_connector_edid(connector))))) | ||
2201 | radeon_audio_mode_set(encoder, adjusted_mode); | ||
2200 | } | 2202 | } |
2201 | 2203 | ||
2202 | static bool | 2204 | static bool |
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 0c993da9c8fb..3e670d344a20 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c | |||
@@ -7555,6 +7555,9 @@ int cik_irq_set(struct radeon_device *rdev) | |||
7555 | WREG32(DC_HPD5_INT_CONTROL, hpd5); | 7555 | WREG32(DC_HPD5_INT_CONTROL, hpd5); |
7556 | WREG32(DC_HPD6_INT_CONTROL, hpd6); | 7556 | WREG32(DC_HPD6_INT_CONTROL, hpd6); |
7557 | 7557 | ||
7558 | /* posting read */ | ||
7559 | RREG32(SRBM_STATUS); | ||
7560 | |||
7558 | return 0; | 7561 | return 0; |
7559 | } | 7562 | } |
7560 | 7563 | ||
diff --git a/drivers/gpu/drm/radeon/dce6_afmt.c b/drivers/gpu/drm/radeon/dce6_afmt.c index 192c80389151..3adc2afe32aa 100644 --- a/drivers/gpu/drm/radeon/dce6_afmt.c +++ b/drivers/gpu/drm/radeon/dce6_afmt.c | |||
@@ -26,6 +26,9 @@ | |||
26 | #include "radeon_audio.h" | 26 | #include "radeon_audio.h" |
27 | #include "sid.h" | 27 | #include "sid.h" |
28 | 28 | ||
29 | #define DCE8_DCCG_AUDIO_DTO1_PHASE 0x05b8 | ||
30 | #define DCE8_DCCG_AUDIO_DTO1_MODULE 0x05bc | ||
31 | |||
29 | u32 dce6_endpoint_rreg(struct radeon_device *rdev, | 32 | u32 dce6_endpoint_rreg(struct radeon_device *rdev, |
30 | u32 block_offset, u32 reg) | 33 | u32 block_offset, u32 reg) |
31 | { | 34 | { |
@@ -252,72 +255,67 @@ void dce6_audio_enable(struct radeon_device *rdev, | |||
252 | void dce6_hdmi_audio_set_dto(struct radeon_device *rdev, | 255 | void dce6_hdmi_audio_set_dto(struct radeon_device *rdev, |
253 | struct radeon_crtc *crtc, unsigned int clock) | 256 | struct radeon_crtc *crtc, unsigned int clock) |
254 | { | 257 | { |
255 | /* Two dtos; generally use dto0 for HDMI */ | 258 | /* Two dtos; generally use dto0 for HDMI */ |
256 | u32 value = 0; | 259 | u32 value = 0; |
257 | 260 | ||
258 | if (crtc) | 261 | if (crtc) |
259 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); | 262 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); |
260 | 263 | ||
261 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); | 264 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); |
262 | 265 | ||
263 | /* Express [24MHz / target pixel clock] as an exact rational | 266 | /* Express [24MHz / target pixel clock] as an exact rational |
264 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE | 267 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
265 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator | 268 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
266 | */ | 269 | */ |
267 | WREG32(DCCG_AUDIO_DTO0_PHASE, 24000); | 270 | WREG32(DCCG_AUDIO_DTO0_PHASE, 24000); |
268 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock); | 271 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock); |
269 | } | 272 | } |
270 | 273 | ||
271 | void dce6_dp_audio_set_dto(struct radeon_device *rdev, | 274 | void dce6_dp_audio_set_dto(struct radeon_device *rdev, |
272 | struct radeon_crtc *crtc, unsigned int clock) | 275 | struct radeon_crtc *crtc, unsigned int clock) |
273 | { | 276 | { |
274 | /* Two dtos; generally use dto1 for DP */ | 277 | /* Two dtos; generally use dto1 for DP */ |
275 | u32 value = 0; | 278 | u32 value = 0; |
276 | value |= DCCG_AUDIO_DTO_SEL; | 279 | value |= DCCG_AUDIO_DTO_SEL; |
277 | 280 | ||
278 | if (crtc) | 281 | if (crtc) |
279 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); | 282 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); |
280 | 283 | ||
281 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); | 284 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); |
282 | 285 | ||
283 | /* Express [24MHz / target pixel clock] as an exact rational | 286 | /* Express [24MHz / target pixel clock] as an exact rational |
284 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE | 287 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
285 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator | 288 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
286 | */ | 289 | */ |
287 | WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); | 290 | if (ASIC_IS_DCE8(rdev)) { |
288 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock); | 291 | WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000); |
292 | WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock); | ||
293 | } else { | ||
294 | WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); | ||
295 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock); | ||
296 | } | ||
289 | } | 297 | } |
290 | 298 | ||
291 | void dce6_enable_dp_audio_packets(struct drm_encoder *encoder, bool enable) | 299 | void dce6_dp_enable(struct drm_encoder *encoder, bool enable) |
292 | { | 300 | { |
293 | struct drm_device *dev = encoder->dev; | 301 | struct drm_device *dev = encoder->dev; |
294 | struct radeon_device *rdev = dev->dev_private; | 302 | struct radeon_device *rdev = dev->dev_private; |
295 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 303 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
296 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | 304 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
297 | uint32_t offset; | ||
298 | 305 | ||
299 | if (!dig || !dig->afmt) | 306 | if (!dig || !dig->afmt) |
300 | return; | 307 | return; |
301 | 308 | ||
302 | offset = dig->afmt->offset; | ||
303 | |||
304 | if (enable) { | 309 | if (enable) { |
305 | if (dig->afmt->enabled) | 310 | WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset, |
306 | return; | 311 | EVERGREEN_DP_SEC_TIMESTAMP_MODE(1)); |
307 | 312 | WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, | |
308 | WREG32(EVERGREEN_DP_SEC_TIMESTAMP + offset, EVERGREEN_DP_SEC_TIMESTAMP_MODE(1)); | 313 | EVERGREEN_DP_SEC_ASP_ENABLE | /* Audio packet transmission */ |
309 | WREG32(EVERGREEN_DP_SEC_CNTL + offset, | 314 | EVERGREEN_DP_SEC_ATP_ENABLE | /* Audio timestamp packet transmission */ |
310 | EVERGREEN_DP_SEC_ASP_ENABLE | /* Audio packet transmission */ | 315 | EVERGREEN_DP_SEC_AIP_ENABLE | /* Audio infoframe packet transmission */ |
311 | EVERGREEN_DP_SEC_ATP_ENABLE | /* Audio timestamp packet transmission */ | 316 | EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */ |
312 | EVERGREEN_DP_SEC_AIP_ENABLE | /* Audio infoframe packet transmission */ | ||
313 | EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */ | ||
314 | radeon_audio_enable(rdev, dig->afmt->pin, true); | ||
315 | } else { | 317 | } else { |
316 | if (!dig->afmt->enabled) | 318 | WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0); |
317 | return; | ||
318 | |||
319 | WREG32(EVERGREEN_DP_SEC_CNTL + offset, 0); | ||
320 | radeon_audio_enable(rdev, dig->afmt->pin, false); | ||
321 | } | 319 | } |
322 | 320 | ||
323 | dig->afmt->enabled = enable; | 321 | dig->afmt->enabled = enable; |
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 4c0e24b3bb90..973df064c14f 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -4593,6 +4593,9 @@ int evergreen_irq_set(struct radeon_device *rdev) | |||
4593 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5); | 4593 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5); |
4594 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6); | 4594 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6); |
4595 | 4595 | ||
4596 | /* posting read */ | ||
4597 | RREG32(SRBM_STATUS); | ||
4598 | |||
4596 | return 0; | 4599 | return 0; |
4597 | } | 4600 | } |
4598 | 4601 | ||
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c index 1d9aebc79595..c18d4ecbd95d 100644 --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c | |||
@@ -272,7 +272,7 @@ void dce4_hdmi_audio_set_dto(struct radeon_device *rdev, | |||
272 | } | 272 | } |
273 | 273 | ||
274 | void dce4_dp_audio_set_dto(struct radeon_device *rdev, | 274 | void dce4_dp_audio_set_dto(struct radeon_device *rdev, |
275 | struct radeon_crtc *crtc, unsigned int clock) | 275 | struct radeon_crtc *crtc, unsigned int clock) |
276 | { | 276 | { |
277 | u32 value; | 277 | u32 value; |
278 | 278 | ||
@@ -294,7 +294,7 @@ void dce4_dp_audio_set_dto(struct radeon_device *rdev, | |||
294 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator | 294 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
295 | */ | 295 | */ |
296 | WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); | 296 | WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); |
297 | WREG32(DCCG_AUDIO_DTO1_MODULE, rdev->clock.max_pixel_clock * 10); | 297 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock); |
298 | } | 298 | } |
299 | 299 | ||
300 | void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset) | 300 | void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset) |
@@ -350,20 +350,9 @@ void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset) | |||
350 | struct drm_device *dev = encoder->dev; | 350 | struct drm_device *dev = encoder->dev; |
351 | struct radeon_device *rdev = dev->dev_private; | 351 | struct radeon_device *rdev = dev->dev_private; |
352 | 352 | ||
353 | WREG32(HDMI_INFOFRAME_CONTROL0 + offset, | ||
354 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ | ||
355 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ | ||
356 | |||
357 | WREG32(AFMT_INFOFRAME_CONTROL0 + offset, | 353 | WREG32(AFMT_INFOFRAME_CONTROL0 + offset, |
358 | AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ | 354 | AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ |
359 | 355 | ||
360 | WREG32(HDMI_INFOFRAME_CONTROL1 + offset, | ||
361 | HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ | ||
362 | |||
363 | WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, | ||
364 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ | ||
365 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ | ||
366 | |||
367 | WREG32(AFMT_60958_0 + offset, | 356 | WREG32(AFMT_60958_0 + offset, |
368 | AFMT_60958_CS_CHANNEL_NUMBER_L(1)); | 357 | AFMT_60958_CS_CHANNEL_NUMBER_L(1)); |
369 | 358 | ||
@@ -408,15 +397,19 @@ void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) | |||
408 | if (!dig || !dig->afmt) | 397 | if (!dig || !dig->afmt) |
409 | return; | 398 | return; |
410 | 399 | ||
411 | /* Silent, r600_hdmi_enable will raise WARN for us */ | 400 | if (enable) { |
412 | if (enable && dig->afmt->enabled) | 401 | WREG32(HDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, |
413 | return; | 402 | HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ |
414 | if (!enable && !dig->afmt->enabled) | 403 | |
415 | return; | 404 | WREG32(HDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
405 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ | ||
406 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ | ||
416 | 407 | ||
417 | if (!enable && dig->afmt->pin) { | 408 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, |
418 | radeon_audio_enable(rdev, dig->afmt->pin, 0); | 409 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
419 | dig->afmt->pin = NULL; | 410 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ |
411 | } else { | ||
412 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0); | ||
420 | } | 413 | } |
421 | 414 | ||
422 | dig->afmt->enabled = enable; | 415 | dig->afmt->enabled = enable; |
@@ -425,33 +418,28 @@ void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) | |||
425 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); | 418 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); |
426 | } | 419 | } |
427 | 420 | ||
428 | void evergreen_enable_dp_audio_packets(struct drm_encoder *encoder, bool enable) | 421 | void evergreen_dp_enable(struct drm_encoder *encoder, bool enable) |
429 | { | 422 | { |
430 | struct drm_device *dev = encoder->dev; | 423 | struct drm_device *dev = encoder->dev; |
431 | struct radeon_device *rdev = dev->dev_private; | 424 | struct radeon_device *rdev = dev->dev_private; |
432 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 425 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
433 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | 426 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
434 | uint32_t offset; | ||
435 | 427 | ||
436 | if (!dig || !dig->afmt) | 428 | if (!dig || !dig->afmt) |
437 | return; | 429 | return; |
438 | 430 | ||
439 | offset = dig->afmt->offset; | ||
440 | |||
441 | if (enable) { | 431 | if (enable) { |
442 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | 432 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
443 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | 433 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
444 | struct radeon_connector_atom_dig *dig_connector; | 434 | struct radeon_connector_atom_dig *dig_connector; |
445 | uint32_t val; | 435 | uint32_t val; |
446 | 436 | ||
447 | if (dig->afmt->enabled) | 437 | WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset, |
448 | return; | 438 | EVERGREEN_DP_SEC_TIMESTAMP_MODE(1)); |
449 | |||
450 | WREG32(EVERGREEN_DP_SEC_TIMESTAMP + offset, EVERGREEN_DP_SEC_TIMESTAMP_MODE(1)); | ||
451 | 439 | ||
452 | if (radeon_connector->con_priv) { | 440 | if (radeon_connector->con_priv) { |
453 | dig_connector = radeon_connector->con_priv; | 441 | dig_connector = radeon_connector->con_priv; |
454 | val = RREG32(EVERGREEN_DP_SEC_AUD_N + offset); | 442 | val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset); |
455 | val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf); | 443 | val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf); |
456 | 444 | ||
457 | if (dig_connector->dp_clock == 162000) | 445 | if (dig_connector->dp_clock == 162000) |
@@ -459,21 +447,16 @@ void evergreen_enable_dp_audio_packets(struct drm_encoder *encoder, bool enable) | |||
459 | else | 447 | else |
460 | val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5); | 448 | val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5); |
461 | 449 | ||
462 | WREG32(EVERGREEN_DP_SEC_AUD_N + offset, val); | 450 | WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val); |
463 | } | 451 | } |
464 | 452 | ||
465 | WREG32(EVERGREEN_DP_SEC_CNTL + offset, | 453 | WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, |
466 | EVERGREEN_DP_SEC_ASP_ENABLE | /* Audio packet transmission */ | 454 | EVERGREEN_DP_SEC_ASP_ENABLE | /* Audio packet transmission */ |
467 | EVERGREEN_DP_SEC_ATP_ENABLE | /* Audio timestamp packet transmission */ | 455 | EVERGREEN_DP_SEC_ATP_ENABLE | /* Audio timestamp packet transmission */ |
468 | EVERGREEN_DP_SEC_AIP_ENABLE | /* Audio infoframe packet transmission */ | 456 | EVERGREEN_DP_SEC_AIP_ENABLE | /* Audio infoframe packet transmission */ |
469 | EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */ | 457 | EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */ |
470 | radeon_audio_enable(rdev, dig->afmt->pin, 0xf); | ||
471 | } else { | 458 | } else { |
472 | if (!dig->afmt->enabled) | 459 | WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0); |
473 | return; | ||
474 | |||
475 | WREG32(EVERGREEN_DP_SEC_CNTL + offset, 0); | ||
476 | radeon_audio_enable(rdev, dig->afmt->pin, 0); | ||
477 | } | 460 | } |
478 | 461 | ||
479 | dig->afmt->enabled = enable; | 462 | dig->afmt->enabled = enable; |
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 279801ca5110..04f2514f7564 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
@@ -728,6 +728,10 @@ int r100_irq_set(struct radeon_device *rdev) | |||
728 | tmp |= RADEON_FP2_DETECT_MASK; | 728 | tmp |= RADEON_FP2_DETECT_MASK; |
729 | } | 729 | } |
730 | WREG32(RADEON_GEN_INT_CNTL, tmp); | 730 | WREG32(RADEON_GEN_INT_CNTL, tmp); |
731 | |||
732 | /* read back to post the write */ | ||
733 | RREG32(RADEON_GEN_INT_CNTL); | ||
734 | |||
731 | return 0; | 735 | return 0; |
732 | } | 736 | } |
733 | 737 | ||
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 07a71a2488c9..2fcad344492f 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -3784,6 +3784,9 @@ int r600_irq_set(struct radeon_device *rdev) | |||
3784 | WREG32(RV770_CG_THERMAL_INT, thermal_int); | 3784 | WREG32(RV770_CG_THERMAL_INT, thermal_int); |
3785 | } | 3785 | } |
3786 | 3786 | ||
3787 | /* posting read */ | ||
3788 | RREG32(R_000E50_SRBM_STATUS); | ||
3789 | |||
3787 | return 0; | 3790 | return 0; |
3788 | } | 3791 | } |
3789 | 3792 | ||
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c index 62c91ed669ce..dd6606b8e23c 100644 --- a/drivers/gpu/drm/radeon/r600_hdmi.c +++ b/drivers/gpu/drm/radeon/r600_hdmi.c | |||
@@ -476,17 +476,6 @@ void r600_hdmi_enable(struct drm_encoder *encoder, bool enable) | |||
476 | if (!dig || !dig->afmt) | 476 | if (!dig || !dig->afmt) |
477 | return; | 477 | return; |
478 | 478 | ||
479 | /* Silent, r600_hdmi_enable will raise WARN for us */ | ||
480 | if (enable && dig->afmt->enabled) | ||
481 | return; | ||
482 | if (!enable && !dig->afmt->enabled) | ||
483 | return; | ||
484 | |||
485 | if (!enable && dig->afmt->pin) { | ||
486 | radeon_audio_enable(rdev, dig->afmt->pin, 0); | ||
487 | dig->afmt->pin = NULL; | ||
488 | } | ||
489 | |||
490 | /* Older chipsets require setting HDMI and routing manually */ | 479 | /* Older chipsets require setting HDMI and routing manually */ |
491 | if (!ASIC_IS_DCE3(rdev)) { | 480 | if (!ASIC_IS_DCE3(rdev)) { |
492 | if (enable) | 481 | if (enable) |
diff --git a/drivers/gpu/drm/radeon/radeon_audio.c b/drivers/gpu/drm/radeon/radeon_audio.c index a3ceef6d9632..b21ef69a34ac 100644 --- a/drivers/gpu/drm/radeon/radeon_audio.c +++ b/drivers/gpu/drm/radeon/radeon_audio.c | |||
@@ -101,8 +101,8 @@ static void radeon_audio_dp_mode_set(struct drm_encoder *encoder, | |||
101 | struct drm_display_mode *mode); | 101 | struct drm_display_mode *mode); |
102 | void r600_hdmi_enable(struct drm_encoder *encoder, bool enable); | 102 | void r600_hdmi_enable(struct drm_encoder *encoder, bool enable); |
103 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable); | 103 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable); |
104 | void evergreen_enable_dp_audio_packets(struct drm_encoder *encoder, bool enable); | 104 | void evergreen_dp_enable(struct drm_encoder *encoder, bool enable); |
105 | void dce6_enable_dp_audio_packets(struct drm_encoder *encoder, bool enable); | 105 | void dce6_dp_enable(struct drm_encoder *encoder, bool enable); |
106 | 106 | ||
107 | static const u32 pin_offsets[7] = | 107 | static const u32 pin_offsets[7] = |
108 | { | 108 | { |
@@ -210,7 +210,7 @@ static struct radeon_audio_funcs dce4_dp_funcs = { | |||
210 | .set_avi_packet = evergreen_set_avi_packet, | 210 | .set_avi_packet = evergreen_set_avi_packet, |
211 | .set_audio_packet = dce4_set_audio_packet, | 211 | .set_audio_packet = dce4_set_audio_packet, |
212 | .mode_set = radeon_audio_dp_mode_set, | 212 | .mode_set = radeon_audio_dp_mode_set, |
213 | .dpms = evergreen_enable_dp_audio_packets, | 213 | .dpms = evergreen_dp_enable, |
214 | }; | 214 | }; |
215 | 215 | ||
216 | static struct radeon_audio_funcs dce6_hdmi_funcs = { | 216 | static struct radeon_audio_funcs dce6_hdmi_funcs = { |
@@ -240,7 +240,7 @@ static struct radeon_audio_funcs dce6_dp_funcs = { | |||
240 | .set_avi_packet = evergreen_set_avi_packet, | 240 | .set_avi_packet = evergreen_set_avi_packet, |
241 | .set_audio_packet = dce4_set_audio_packet, | 241 | .set_audio_packet = dce4_set_audio_packet, |
242 | .mode_set = radeon_audio_dp_mode_set, | 242 | .mode_set = radeon_audio_dp_mode_set, |
243 | .dpms = dce6_enable_dp_audio_packets, | 243 | .dpms = dce6_dp_enable, |
244 | }; | 244 | }; |
245 | 245 | ||
246 | static void radeon_audio_interface_init(struct radeon_device *rdev) | 246 | static void radeon_audio_interface_init(struct radeon_device *rdev) |
@@ -452,7 +452,7 @@ void radeon_audio_enable(struct radeon_device *rdev, | |||
452 | } | 452 | } |
453 | 453 | ||
454 | void radeon_audio_detect(struct drm_connector *connector, | 454 | void radeon_audio_detect(struct drm_connector *connector, |
455 | enum drm_connector_status status) | 455 | enum drm_connector_status status) |
456 | { | 456 | { |
457 | struct radeon_device *rdev; | 457 | struct radeon_device *rdev; |
458 | struct radeon_encoder *radeon_encoder; | 458 | struct radeon_encoder *radeon_encoder; |
@@ -483,14 +483,11 @@ void radeon_audio_detect(struct drm_connector *connector, | |||
483 | else | 483 | else |
484 | radeon_encoder->audio = rdev->audio.hdmi_funcs; | 484 | radeon_encoder->audio = rdev->audio.hdmi_funcs; |
485 | 485 | ||
486 | radeon_audio_write_speaker_allocation(connector->encoder); | 486 | dig->afmt->pin = radeon_audio_get_pin(connector->encoder); |
487 | radeon_audio_write_sad_regs(connector->encoder); | ||
488 | if (connector->encoder->crtc) | ||
489 | radeon_audio_write_latency_fields(connector->encoder, | ||
490 | &connector->encoder->crtc->mode); | ||
491 | radeon_audio_enable(rdev, dig->afmt->pin, 0xf); | 487 | radeon_audio_enable(rdev, dig->afmt->pin, 0xf); |
492 | } else { | 488 | } else { |
493 | radeon_audio_enable(rdev, dig->afmt->pin, 0); | 489 | radeon_audio_enable(rdev, dig->afmt->pin, 0); |
490 | dig->afmt->pin = NULL; | ||
494 | } | 491 | } |
495 | } | 492 | } |
496 | 493 | ||
@@ -694,23 +691,22 @@ static void radeon_audio_set_mute(struct drm_encoder *encoder, bool mute) | |||
694 | * update the info frames with the data from the current display mode | 691 | * update the info frames with the data from the current display mode |
695 | */ | 692 | */ |
696 | static void radeon_audio_hdmi_mode_set(struct drm_encoder *encoder, | 693 | static void radeon_audio_hdmi_mode_set(struct drm_encoder *encoder, |
697 | struct drm_display_mode *mode) | 694 | struct drm_display_mode *mode) |
698 | { | 695 | { |
699 | struct radeon_device *rdev = encoder->dev->dev_private; | ||
700 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 696 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
701 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | 697 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
702 | 698 | ||
703 | if (!dig || !dig->afmt) | 699 | if (!dig || !dig->afmt) |
704 | return; | 700 | return; |
705 | 701 | ||
706 | /* disable audio prior to setting up hw */ | 702 | radeon_audio_set_mute(encoder, true); |
707 | dig->afmt->pin = radeon_audio_get_pin(encoder); | ||
708 | radeon_audio_enable(rdev, dig->afmt->pin, 0); | ||
709 | 703 | ||
704 | radeon_audio_write_speaker_allocation(encoder); | ||
705 | radeon_audio_write_sad_regs(encoder); | ||
706 | radeon_audio_write_latency_fields(encoder, mode); | ||
710 | radeon_audio_set_dto(encoder, mode->clock); | 707 | radeon_audio_set_dto(encoder, mode->clock); |
711 | radeon_audio_set_vbi_packet(encoder); | 708 | radeon_audio_set_vbi_packet(encoder); |
712 | radeon_hdmi_set_color_depth(encoder); | 709 | radeon_hdmi_set_color_depth(encoder); |
713 | radeon_audio_set_mute(encoder, false); | ||
714 | radeon_audio_update_acr(encoder, mode->clock); | 710 | radeon_audio_update_acr(encoder, mode->clock); |
715 | radeon_audio_set_audio_packet(encoder); | 711 | radeon_audio_set_audio_packet(encoder); |
716 | radeon_audio_select_pin(encoder); | 712 | radeon_audio_select_pin(encoder); |
@@ -718,8 +714,7 @@ static void radeon_audio_hdmi_mode_set(struct drm_encoder *encoder, | |||
718 | if (radeon_audio_set_avi_packet(encoder, mode) < 0) | 714 | if (radeon_audio_set_avi_packet(encoder, mode) < 0) |
719 | return; | 715 | return; |
720 | 716 | ||
721 | /* enable audio after to setting up hw */ | 717 | radeon_audio_set_mute(encoder, false); |
722 | radeon_audio_enable(rdev, dig->afmt->pin, 0xf); | ||
723 | } | 718 | } |
724 | 719 | ||
725 | static void radeon_audio_dp_mode_set(struct drm_encoder *encoder, | 720 | static void radeon_audio_dp_mode_set(struct drm_encoder *encoder, |
@@ -729,23 +724,26 @@ static void radeon_audio_dp_mode_set(struct drm_encoder *encoder, | |||
729 | struct radeon_device *rdev = dev->dev_private; | 724 | struct radeon_device *rdev = dev->dev_private; |
730 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 725 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
731 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | 726 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
727 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | ||
728 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | ||
729 | struct radeon_connector_atom_dig *dig_connector = | ||
730 | radeon_connector->con_priv; | ||
732 | 731 | ||
733 | if (!dig || !dig->afmt) | 732 | if (!dig || !dig->afmt) |
734 | return; | 733 | return; |
735 | 734 | ||
736 | /* disable audio prior to setting up hw */ | 735 | radeon_audio_write_speaker_allocation(encoder); |
737 | dig->afmt->pin = radeon_audio_get_pin(encoder); | 736 | radeon_audio_write_sad_regs(encoder); |
738 | radeon_audio_enable(rdev, dig->afmt->pin, 0); | 737 | radeon_audio_write_latency_fields(encoder, mode); |
739 | 738 | if (rdev->clock.dp_extclk || ASIC_IS_DCE5(rdev)) | |
740 | radeon_audio_set_dto(encoder, rdev->clock.default_dispclk * 10); | 739 | radeon_audio_set_dto(encoder, rdev->clock.default_dispclk * 10); |
740 | else | ||
741 | radeon_audio_set_dto(encoder, dig_connector->dp_clock); | ||
741 | radeon_audio_set_audio_packet(encoder); | 742 | radeon_audio_set_audio_packet(encoder); |
742 | radeon_audio_select_pin(encoder); | 743 | radeon_audio_select_pin(encoder); |
743 | 744 | ||
744 | if (radeon_audio_set_avi_packet(encoder, mode) < 0) | 745 | if (radeon_audio_set_avi_packet(encoder, mode) < 0) |
745 | return; | 746 | return; |
746 | |||
747 | /* enable audio after to setting up hw */ | ||
748 | radeon_audio_enable(rdev, dig->afmt->pin, 0xf); | ||
749 | } | 747 | } |
750 | 748 | ||
751 | void radeon_audio_mode_set(struct drm_encoder *encoder, | 749 | void radeon_audio_mode_set(struct drm_encoder *encoder, |
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index a579ed379f20..4d0f96cc3da4 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c | |||
@@ -256,11 +256,13 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) | |||
256 | u32 ring = RADEON_CS_RING_GFX; | 256 | u32 ring = RADEON_CS_RING_GFX; |
257 | s32 priority = 0; | 257 | s32 priority = 0; |
258 | 258 | ||
259 | INIT_LIST_HEAD(&p->validated); | ||
260 | |||
259 | if (!cs->num_chunks) { | 261 | if (!cs->num_chunks) { |
260 | return 0; | 262 | return 0; |
261 | } | 263 | } |
264 | |||
262 | /* get chunks */ | 265 | /* get chunks */ |
263 | INIT_LIST_HEAD(&p->validated); | ||
264 | p->idx = 0; | 266 | p->idx = 0; |
265 | p->ib.sa_bo = NULL; | 267 | p->ib.sa_bo = NULL; |
266 | p->const_ib.sa_bo = NULL; | 268 | p->const_ib.sa_bo = NULL; |
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c index d13d1b5a859f..df09ca7c4889 100644 --- a/drivers/gpu/drm/radeon/radeon_fence.c +++ b/drivers/gpu/drm/radeon/radeon_fence.c | |||
@@ -1030,37 +1030,59 @@ static inline bool radeon_test_signaled(struct radeon_fence *fence) | |||
1030 | return test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags); | 1030 | return test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags); |
1031 | } | 1031 | } |
1032 | 1032 | ||
1033 | struct radeon_wait_cb { | ||
1034 | struct fence_cb base; | ||
1035 | struct task_struct *task; | ||
1036 | }; | ||
1037 | |||
1038 | static void | ||
1039 | radeon_fence_wait_cb(struct fence *fence, struct fence_cb *cb) | ||
1040 | { | ||
1041 | struct radeon_wait_cb *wait = | ||
1042 | container_of(cb, struct radeon_wait_cb, base); | ||
1043 | |||
1044 | wake_up_process(wait->task); | ||
1045 | } | ||
1046 | |||
1033 | static signed long radeon_fence_default_wait(struct fence *f, bool intr, | 1047 | static signed long radeon_fence_default_wait(struct fence *f, bool intr, |
1034 | signed long t) | 1048 | signed long t) |
1035 | { | 1049 | { |
1036 | struct radeon_fence *fence = to_radeon_fence(f); | 1050 | struct radeon_fence *fence = to_radeon_fence(f); |
1037 | struct radeon_device *rdev = fence->rdev; | 1051 | struct radeon_device *rdev = fence->rdev; |
1038 | bool signaled; | 1052 | struct radeon_wait_cb cb; |
1039 | 1053 | ||
1040 | fence_enable_sw_signaling(&fence->base); | 1054 | cb.task = current; |
1041 | 1055 | ||
1042 | /* | 1056 | if (fence_add_callback(f, &cb.base, radeon_fence_wait_cb)) |
1043 | * This function has to return -EDEADLK, but cannot hold | 1057 | return t; |
1044 | * exclusive_lock during the wait because some callers | 1058 | |
1045 | * may already hold it. This means checking needs_reset without | 1059 | while (t > 0) { |
1046 | * lock, and not fiddling with any gpu internals. | 1060 | if (intr) |
1047 | * | 1061 | set_current_state(TASK_INTERRUPTIBLE); |
1048 | * The callback installed with fence_enable_sw_signaling will | 1062 | else |
1049 | * run before our wait_event_*timeout call, so we will see | 1063 | set_current_state(TASK_UNINTERRUPTIBLE); |
1050 | * both the signaled fence and the changes to needs_reset. | 1064 | |
1051 | */ | 1065 | /* |
1066 | * radeon_test_signaled must be called after | ||
1067 | * set_current_state to prevent a race with wake_up_process | ||
1068 | */ | ||
1069 | if (radeon_test_signaled(fence)) | ||
1070 | break; | ||
1071 | |||
1072 | if (rdev->needs_reset) { | ||
1073 | t = -EDEADLK; | ||
1074 | break; | ||
1075 | } | ||
1076 | |||
1077 | t = schedule_timeout(t); | ||
1078 | |||
1079 | if (t > 0 && intr && signal_pending(current)) | ||
1080 | t = -ERESTARTSYS; | ||
1081 | } | ||
1082 | |||
1083 | __set_current_state(TASK_RUNNING); | ||
1084 | fence_remove_callback(f, &cb.base); | ||
1052 | 1085 | ||
1053 | if (intr) | ||
1054 | t = wait_event_interruptible_timeout(rdev->fence_queue, | ||
1055 | ((signaled = radeon_test_signaled(fence)) || | ||
1056 | rdev->needs_reset), t); | ||
1057 | else | ||
1058 | t = wait_event_timeout(rdev->fence_queue, | ||
1059 | ((signaled = radeon_test_signaled(fence)) || | ||
1060 | rdev->needs_reset), t); | ||
1061 | |||
1062 | if (t > 0 && !signaled) | ||
1063 | return -EDEADLK; | ||
1064 | return t; | 1086 | return t; |
1065 | } | 1087 | } |
1066 | 1088 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_kfd.c b/drivers/gpu/drm/radeon/radeon_kfd.c index 061eaa9c19c7..122eb5693ba1 100644 --- a/drivers/gpu/drm/radeon/radeon_kfd.c +++ b/drivers/gpu/drm/radeon/radeon_kfd.c | |||
@@ -153,7 +153,7 @@ void radeon_kfd_device_init(struct radeon_device *rdev) | |||
153 | .compute_vmid_bitmap = 0xFF00, | 153 | .compute_vmid_bitmap = 0xFF00, |
154 | 154 | ||
155 | .first_compute_pipe = 1, | 155 | .first_compute_pipe = 1, |
156 | .compute_pipe_count = 8 - 1, | 156 | .compute_pipe_count = 4 - 1, |
157 | }; | 157 | }; |
158 | 158 | ||
159 | radeon_doorbell_get_kfd_info(rdev, | 159 | radeon_doorbell_get_kfd_info(rdev, |
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index 43e09942823e..318165d4855c 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c | |||
@@ -173,17 +173,6 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) | |||
173 | else | 173 | else |
174 | rbo->placements[i].lpfn = 0; | 174 | rbo->placements[i].lpfn = 0; |
175 | } | 175 | } |
176 | |||
177 | /* | ||
178 | * Use two-ended allocation depending on the buffer size to | ||
179 | * improve fragmentation quality. | ||
180 | * 512kb was measured as the most optimal number. | ||
181 | */ | ||
182 | if (rbo->tbo.mem.size > 512 * 1024) { | ||
183 | for (i = 0; i < c; i++) { | ||
184 | rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN; | ||
185 | } | ||
186 | } | ||
187 | } | 176 | } |
188 | 177 | ||
189 | int radeon_bo_create(struct radeon_device *rdev, | 178 | int radeon_bo_create(struct radeon_device *rdev, |
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index d81182ad53ec..97a904835759 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c | |||
@@ -694,6 +694,10 @@ int rs600_irq_set(struct radeon_device *rdev) | |||
694 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); | 694 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
695 | if (ASIC_IS_DCE2(rdev)) | 695 | if (ASIC_IS_DCE2(rdev)) |
696 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); | 696 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
697 | |||
698 | /* posting read */ | ||
699 | RREG32(R_000040_GEN_INT_CNTL); | ||
700 | |||
697 | return 0; | 701 | return 0; |
698 | } | 702 | } |
699 | 703 | ||
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index bcf516a8a2f1..a7fb2735d4a9 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c | |||
@@ -6203,6 +6203,9 @@ int si_irq_set(struct radeon_device *rdev) | |||
6203 | 6203 | ||
6204 | WREG32(CG_THERMAL_INT, thermal_int); | 6204 | WREG32(CG_THERMAL_INT, thermal_int); |
6205 | 6205 | ||
6206 | /* posting read */ | ||
6207 | RREG32(SRBM_STATUS); | ||
6208 | |||
6206 | return 0; | 6209 | return 0; |
6207 | } | 6210 | } |
6208 | 6211 | ||
@@ -7127,8 +7130,7 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) | |||
7127 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); | 7130 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); |
7128 | 7131 | ||
7129 | if (!vclk || !dclk) { | 7132 | if (!vclk || !dclk) { |
7130 | /* keep the Bypass mode, put PLL to sleep */ | 7133 | /* keep the Bypass mode */ |
7131 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); | ||
7132 | return 0; | 7134 | return 0; |
7133 | } | 7135 | } |
7134 | 7136 | ||
@@ -7144,8 +7146,7 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) | |||
7144 | /* set VCO_MODE to 1 */ | 7146 | /* set VCO_MODE to 1 */ |
7145 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); | 7147 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); |
7146 | 7148 | ||
7147 | /* toggle UPLL_SLEEP to 1 then back to 0 */ | 7149 | /* disable sleep mode */ |
7148 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); | ||
7149 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); | 7150 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); |
7150 | 7151 | ||
7151 | /* deassert UPLL_RESET */ | 7152 | /* deassert UPLL_RESET */ |
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h index c27118cab16a..99a9835c9f61 100644 --- a/drivers/gpu/drm/radeon/sid.h +++ b/drivers/gpu/drm/radeon/sid.h | |||
@@ -912,8 +912,8 @@ | |||
912 | 912 | ||
913 | #define DCCG_AUDIO_DTO0_PHASE 0x05b0 | 913 | #define DCCG_AUDIO_DTO0_PHASE 0x05b0 |
914 | #define DCCG_AUDIO_DTO0_MODULE 0x05b4 | 914 | #define DCCG_AUDIO_DTO0_MODULE 0x05b4 |
915 | #define DCCG_AUDIO_DTO1_PHASE 0x05b8 | 915 | #define DCCG_AUDIO_DTO1_PHASE 0x05c0 |
916 | #define DCCG_AUDIO_DTO1_MODULE 0x05bc | 916 | #define DCCG_AUDIO_DTO1_MODULE 0x05c4 |
917 | 917 | ||
918 | #define AFMT_AUDIO_SRC_CONTROL 0x713c | 918 | #define AFMT_AUDIO_SRC_CONTROL 0x713c |
919 | #define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0) | 919 | #define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0) |
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index d395b0bef73b..8d9b7de25613 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c | |||
@@ -74,7 +74,7 @@ static void ttm_mem_type_debug(struct ttm_bo_device *bdev, int mem_type) | |||
74 | pr_err(" has_type: %d\n", man->has_type); | 74 | pr_err(" has_type: %d\n", man->has_type); |
75 | pr_err(" use_type: %d\n", man->use_type); | 75 | pr_err(" use_type: %d\n", man->use_type); |
76 | pr_err(" flags: 0x%08X\n", man->flags); | 76 | pr_err(" flags: 0x%08X\n", man->flags); |
77 | pr_err(" gpu_offset: 0x%08lX\n", man->gpu_offset); | 77 | pr_err(" gpu_offset: 0x%08llX\n", man->gpu_offset); |
78 | pr_err(" size: %llu\n", man->size); | 78 | pr_err(" size: %llu\n", man->size); |
79 | pr_err(" available_caching: 0x%08X\n", man->available_caching); | 79 | pr_err(" available_caching: 0x%08X\n", man->available_caching); |
80 | pr_err(" default_caching: 0x%08X\n", man->default_caching); | 80 | pr_err(" default_caching: 0x%08X\n", man->default_caching); |
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c index 6c6b655defcf..e13b9cbc304e 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | |||
@@ -725,32 +725,6 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) | |||
725 | goto out_err1; | 725 | goto out_err1; |
726 | } | 726 | } |
727 | 727 | ||
728 | ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, | ||
729 | (dev_priv->vram_size >> PAGE_SHIFT)); | ||
730 | if (unlikely(ret != 0)) { | ||
731 | DRM_ERROR("Failed initializing memory manager for VRAM.\n"); | ||
732 | goto out_err2; | ||
733 | } | ||
734 | |||
735 | dev_priv->has_gmr = true; | ||
736 | if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || | ||
737 | refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, | ||
738 | VMW_PL_GMR) != 0) { | ||
739 | DRM_INFO("No GMR memory available. " | ||
740 | "Graphics memory resources are very limited.\n"); | ||
741 | dev_priv->has_gmr = false; | ||
742 | } | ||
743 | |||
744 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { | ||
745 | dev_priv->has_mob = true; | ||
746 | if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, | ||
747 | VMW_PL_MOB) != 0) { | ||
748 | DRM_INFO("No MOB memory available. " | ||
749 | "3D will be disabled.\n"); | ||
750 | dev_priv->has_mob = false; | ||
751 | } | ||
752 | } | ||
753 | |||
754 | dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start, | 728 | dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start, |
755 | dev_priv->mmio_size); | 729 | dev_priv->mmio_size); |
756 | 730 | ||
@@ -813,6 +787,33 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) | |||
813 | goto out_no_fman; | 787 | goto out_no_fman; |
814 | } | 788 | } |
815 | 789 | ||
790 | |||
791 | ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, | ||
792 | (dev_priv->vram_size >> PAGE_SHIFT)); | ||
793 | if (unlikely(ret != 0)) { | ||
794 | DRM_ERROR("Failed initializing memory manager for VRAM.\n"); | ||
795 | goto out_no_vram; | ||
796 | } | ||
797 | |||
798 | dev_priv->has_gmr = true; | ||
799 | if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || | ||
800 | refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, | ||
801 | VMW_PL_GMR) != 0) { | ||
802 | DRM_INFO("No GMR memory available. " | ||
803 | "Graphics memory resources are very limited.\n"); | ||
804 | dev_priv->has_gmr = false; | ||
805 | } | ||
806 | |||
807 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { | ||
808 | dev_priv->has_mob = true; | ||
809 | if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, | ||
810 | VMW_PL_MOB) != 0) { | ||
811 | DRM_INFO("No MOB memory available. " | ||
812 | "3D will be disabled.\n"); | ||
813 | dev_priv->has_mob = false; | ||
814 | } | ||
815 | } | ||
816 | |||
816 | vmw_kms_save_vga(dev_priv); | 817 | vmw_kms_save_vga(dev_priv); |
817 | 818 | ||
818 | /* Start kms and overlay systems, needs fifo. */ | 819 | /* Start kms and overlay systems, needs fifo. */ |
@@ -838,6 +839,12 @@ out_no_fifo: | |||
838 | vmw_kms_close(dev_priv); | 839 | vmw_kms_close(dev_priv); |
839 | out_no_kms: | 840 | out_no_kms: |
840 | vmw_kms_restore_vga(dev_priv); | 841 | vmw_kms_restore_vga(dev_priv); |
842 | if (dev_priv->has_mob) | ||
843 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); | ||
844 | if (dev_priv->has_gmr) | ||
845 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | ||
846 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); | ||
847 | out_no_vram: | ||
841 | vmw_fence_manager_takedown(dev_priv->fman); | 848 | vmw_fence_manager_takedown(dev_priv->fman); |
842 | out_no_fman: | 849 | out_no_fman: |
843 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) | 850 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
@@ -853,12 +860,6 @@ out_err4: | |||
853 | iounmap(dev_priv->mmio_virt); | 860 | iounmap(dev_priv->mmio_virt); |
854 | out_err3: | 861 | out_err3: |
855 | arch_phys_wc_del(dev_priv->mmio_mtrr); | 862 | arch_phys_wc_del(dev_priv->mmio_mtrr); |
856 | if (dev_priv->has_mob) | ||
857 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); | ||
858 | if (dev_priv->has_gmr) | ||
859 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | ||
860 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); | ||
861 | out_err2: | ||
862 | (void)ttm_bo_device_release(&dev_priv->bdev); | 863 | (void)ttm_bo_device_release(&dev_priv->bdev); |
863 | out_err1: | 864 | out_err1: |
864 | vmw_ttm_global_release(dev_priv); | 865 | vmw_ttm_global_release(dev_priv); |
@@ -887,6 +888,13 @@ static int vmw_driver_unload(struct drm_device *dev) | |||
887 | } | 888 | } |
888 | vmw_kms_close(dev_priv); | 889 | vmw_kms_close(dev_priv); |
889 | vmw_overlay_close(dev_priv); | 890 | vmw_overlay_close(dev_priv); |
891 | |||
892 | if (dev_priv->has_mob) | ||
893 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); | ||
894 | if (dev_priv->has_gmr) | ||
895 | (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | ||
896 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); | ||
897 | |||
890 | vmw_fence_manager_takedown(dev_priv->fman); | 898 | vmw_fence_manager_takedown(dev_priv->fman); |
891 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) | 899 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
892 | drm_irq_uninstall(dev_priv->dev); | 900 | drm_irq_uninstall(dev_priv->dev); |
@@ -898,11 +906,6 @@ static int vmw_driver_unload(struct drm_device *dev) | |||
898 | ttm_object_device_release(&dev_priv->tdev); | 906 | ttm_object_device_release(&dev_priv->tdev); |
899 | iounmap(dev_priv->mmio_virt); | 907 | iounmap(dev_priv->mmio_virt); |
900 | arch_phys_wc_del(dev_priv->mmio_mtrr); | 908 | arch_phys_wc_del(dev_priv->mmio_mtrr); |
901 | if (dev_priv->has_mob) | ||
902 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); | ||
903 | if (dev_priv->has_gmr) | ||
904 | (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | ||
905 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); | ||
906 | (void)ttm_bo_device_release(&dev_priv->bdev); | 909 | (void)ttm_bo_device_release(&dev_priv->bdev); |
907 | vmw_ttm_global_release(dev_priv); | 910 | vmw_ttm_global_release(dev_priv); |
908 | 911 | ||
@@ -1235,6 +1238,7 @@ static void vmw_remove(struct pci_dev *pdev) | |||
1235 | { | 1238 | { |
1236 | struct drm_device *dev = pci_get_drvdata(pdev); | 1239 | struct drm_device *dev = pci_get_drvdata(pdev); |
1237 | 1240 | ||
1241 | pci_disable_device(pdev); | ||
1238 | drm_put_dev(dev); | 1242 | drm_put_dev(dev); |
1239 | } | 1243 | } |
1240 | 1244 | ||
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c index 33176d05db35..654c8daeb5ab 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | |||
@@ -890,7 +890,8 @@ static int vmw_translate_mob_ptr(struct vmw_private *dev_priv, | |||
890 | ret = vmw_user_dmabuf_lookup(sw_context->fp->tfile, handle, &vmw_bo); | 890 | ret = vmw_user_dmabuf_lookup(sw_context->fp->tfile, handle, &vmw_bo); |
891 | if (unlikely(ret != 0)) { | 891 | if (unlikely(ret != 0)) { |
892 | DRM_ERROR("Could not find or use MOB buffer.\n"); | 892 | DRM_ERROR("Could not find or use MOB buffer.\n"); |
893 | return -EINVAL; | 893 | ret = -EINVAL; |
894 | goto out_no_reloc; | ||
894 | } | 895 | } |
895 | bo = &vmw_bo->base; | 896 | bo = &vmw_bo->base; |
896 | 897 | ||
@@ -914,7 +915,7 @@ static int vmw_translate_mob_ptr(struct vmw_private *dev_priv, | |||
914 | 915 | ||
915 | out_no_reloc: | 916 | out_no_reloc: |
916 | vmw_dmabuf_unreference(&vmw_bo); | 917 | vmw_dmabuf_unreference(&vmw_bo); |
917 | vmw_bo_p = NULL; | 918 | *vmw_bo_p = NULL; |
918 | return ret; | 919 | return ret; |
919 | } | 920 | } |
920 | 921 | ||
@@ -951,7 +952,8 @@ static int vmw_translate_guest_ptr(struct vmw_private *dev_priv, | |||
951 | ret = vmw_user_dmabuf_lookup(sw_context->fp->tfile, handle, &vmw_bo); | 952 | ret = vmw_user_dmabuf_lookup(sw_context->fp->tfile, handle, &vmw_bo); |
952 | if (unlikely(ret != 0)) { | 953 | if (unlikely(ret != 0)) { |
953 | DRM_ERROR("Could not find or use GMR region.\n"); | 954 | DRM_ERROR("Could not find or use GMR region.\n"); |
954 | return -EINVAL; | 955 | ret = -EINVAL; |
956 | goto out_no_reloc; | ||
955 | } | 957 | } |
956 | bo = &vmw_bo->base; | 958 | bo = &vmw_bo->base; |
957 | 959 | ||
@@ -974,7 +976,7 @@ static int vmw_translate_guest_ptr(struct vmw_private *dev_priv, | |||
974 | 976 | ||
975 | out_no_reloc: | 977 | out_no_reloc: |
976 | vmw_dmabuf_unreference(&vmw_bo); | 978 | vmw_dmabuf_unreference(&vmw_bo); |
977 | vmw_bo_p = NULL; | 979 | *vmw_bo_p = NULL; |
978 | return ret; | 980 | return ret; |
979 | } | 981 | } |
980 | 982 | ||
@@ -2780,13 +2782,11 @@ int vmw_execbuf_ioctl(struct drm_device *dev, void *data, | |||
2780 | NULL, arg->command_size, arg->throttle_us, | 2782 | NULL, arg->command_size, arg->throttle_us, |
2781 | (void __user *)(unsigned long)arg->fence_rep, | 2783 | (void __user *)(unsigned long)arg->fence_rep, |
2782 | NULL); | 2784 | NULL); |
2783 | 2785 | ttm_read_unlock(&dev_priv->reservation_sem); | |
2784 | if (unlikely(ret != 0)) | 2786 | if (unlikely(ret != 0)) |
2785 | goto out_unlock; | 2787 | return ret; |
2786 | 2788 | ||
2787 | vmw_kms_cursor_post_execbuf(dev_priv); | 2789 | vmw_kms_cursor_post_execbuf(dev_priv); |
2788 | 2790 | ||
2789 | out_unlock: | 2791 | return 0; |
2790 | ttm_read_unlock(&dev_priv->reservation_sem); | ||
2791 | return ret; | ||
2792 | } | 2792 | } |
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c index 8725b79e7847..07cda8cbbddb 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | |||
@@ -2033,23 +2033,17 @@ int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data, | |||
2033 | int i; | 2033 | int i; |
2034 | struct drm_mode_config *mode_config = &dev->mode_config; | 2034 | struct drm_mode_config *mode_config = &dev->mode_config; |
2035 | 2035 | ||
2036 | ret = ttm_read_lock(&dev_priv->reservation_sem, true); | ||
2037 | if (unlikely(ret != 0)) | ||
2038 | return ret; | ||
2039 | |||
2040 | if (!arg->num_outputs) { | 2036 | if (!arg->num_outputs) { |
2041 | struct drm_vmw_rect def_rect = {0, 0, 800, 600}; | 2037 | struct drm_vmw_rect def_rect = {0, 0, 800, 600}; |
2042 | vmw_du_update_layout(dev_priv, 1, &def_rect); | 2038 | vmw_du_update_layout(dev_priv, 1, &def_rect); |
2043 | goto out_unlock; | 2039 | return 0; |
2044 | } | 2040 | } |
2045 | 2041 | ||
2046 | rects_size = arg->num_outputs * sizeof(struct drm_vmw_rect); | 2042 | rects_size = arg->num_outputs * sizeof(struct drm_vmw_rect); |
2047 | rects = kcalloc(arg->num_outputs, sizeof(struct drm_vmw_rect), | 2043 | rects = kcalloc(arg->num_outputs, sizeof(struct drm_vmw_rect), |
2048 | GFP_KERNEL); | 2044 | GFP_KERNEL); |
2049 | if (unlikely(!rects)) { | 2045 | if (unlikely(!rects)) |
2050 | ret = -ENOMEM; | 2046 | return -ENOMEM; |
2051 | goto out_unlock; | ||
2052 | } | ||
2053 | 2047 | ||
2054 | user_rects = (void __user *)(unsigned long)arg->rects; | 2048 | user_rects = (void __user *)(unsigned long)arg->rects; |
2055 | ret = copy_from_user(rects, user_rects, rects_size); | 2049 | ret = copy_from_user(rects, user_rects, rects_size); |
@@ -2074,7 +2068,5 @@ int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data, | |||
2074 | 2068 | ||
2075 | out_free: | 2069 | out_free: |
2076 | kfree(rects); | 2070 | kfree(rects); |
2077 | out_unlock: | ||
2078 | ttm_read_unlock(&dev_priv->reservation_sem); | ||
2079 | return ret; | 2071 | return ret; |
2080 | } | 2072 | } |