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path: root/drivers/gpu/drm/radeon/si_dpm.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/si_dpm.c')
-rw-r--r--drivers/gpu/drm/radeon/si_dpm.c53
1 files changed, 43 insertions, 10 deletions
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index 89bdf20344ae..c49934527a87 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -2999,6 +2999,49 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2999 int i; 2999 int i;
3000 struct si_dpm_quirk *p = si_dpm_quirk_list; 3000 struct si_dpm_quirk *p = si_dpm_quirk_list;
3001 3001
3002 /* limit all SI kickers */
3003 if (rdev->family == CHIP_PITCAIRN) {
3004 if ((rdev->pdev->revision == 0x81) ||
3005 (rdev->pdev->device == 0x6810) ||
3006 (rdev->pdev->device == 0x6811) ||
3007 (rdev->pdev->device == 0x6816) ||
3008 (rdev->pdev->device == 0x6817) ||
3009 (rdev->pdev->device == 0x6806))
3010 max_mclk = 120000;
3011 } else if (rdev->family == CHIP_VERDE) {
3012 if ((rdev->pdev->revision == 0x81) ||
3013 (rdev->pdev->revision == 0x83) ||
3014 (rdev->pdev->revision == 0x87) ||
3015 (rdev->pdev->device == 0x6820) ||
3016 (rdev->pdev->device == 0x6821) ||
3017 (rdev->pdev->device == 0x6822) ||
3018 (rdev->pdev->device == 0x6823) ||
3019 (rdev->pdev->device == 0x682A) ||
3020 (rdev->pdev->device == 0x682B)) {
3021 max_sclk = 75000;
3022 max_mclk = 80000;
3023 }
3024 } else if (rdev->family == CHIP_OLAND) {
3025 if ((rdev->pdev->revision == 0xC7) ||
3026 (rdev->pdev->revision == 0x80) ||
3027 (rdev->pdev->revision == 0x81) ||
3028 (rdev->pdev->revision == 0x83) ||
3029 (rdev->pdev->device == 0x6604) ||
3030 (rdev->pdev->device == 0x6605)) {
3031 max_sclk = 75000;
3032 max_mclk = 80000;
3033 }
3034 } else if (rdev->family == CHIP_HAINAN) {
3035 if ((rdev->pdev->revision == 0x81) ||
3036 (rdev->pdev->revision == 0x83) ||
3037 (rdev->pdev->revision == 0xC3) ||
3038 (rdev->pdev->device == 0x6664) ||
3039 (rdev->pdev->device == 0x6665) ||
3040 (rdev->pdev->device == 0x6667)) {
3041 max_sclk = 75000;
3042 max_mclk = 80000;
3043 }
3044 }
3002 /* Apply dpm quirks */ 3045 /* Apply dpm quirks */
3003 while (p && p->chip_device != 0) { 3046 while (p && p->chip_device != 0) {
3004 if (rdev->pdev->vendor == p->chip_vendor && 3047 if (rdev->pdev->vendor == p->chip_vendor &&
@@ -3011,16 +3054,6 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
3011 } 3054 }
3012 ++p; 3055 ++p;
3013 } 3056 }
3014 /* limit mclk on all R7 370 parts for stability */
3015 if (rdev->pdev->device == 0x6811 &&
3016 rdev->pdev->revision == 0x81)
3017 max_mclk = 120000;
3018 /* limit sclk/mclk on Jet parts for stability */
3019 if (rdev->pdev->device == 0x6665 &&
3020 rdev->pdev->revision == 0xc3) {
3021 max_sclk = 75000;
3022 max_mclk = 80000;
3023 }
3024 3057
3025 if (rps->vce_active) { 3058 if (rps->vce_active) {
3026 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 3059 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;