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path: root/drivers/gpu/drm/radeon/si.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
-rw-r--r--drivers/gpu/drm/radeon/si.c336
1 files changed, 192 insertions, 144 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 26388b5dd6ed..07037e32dea3 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -6466,23 +6466,27 @@ restart_ih:
6466 case 1: /* D1 vblank/vline */ 6466 case 1: /* D1 vblank/vline */
6467 switch (src_data) { 6467 switch (src_data) {
6468 case 0: /* D1 vblank */ 6468 case 0: /* D1 vblank */
6469 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { 6469 if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT))
6470 if (rdev->irq.crtc_vblank_int[0]) { 6470 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6471 drm_handle_vblank(rdev->ddev, 0); 6471
6472 rdev->pm.vblank_sync = true; 6472 if (rdev->irq.crtc_vblank_int[0]) {
6473 wake_up(&rdev->irq.vblank_queue); 6473 drm_handle_vblank(rdev->ddev, 0);
6474 } 6474 rdev->pm.vblank_sync = true;
6475 if (atomic_read(&rdev->irq.pflip[0])) 6475 wake_up(&rdev->irq.vblank_queue);
6476 radeon_crtc_handle_vblank(rdev, 0);
6477 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
6478 DRM_DEBUG("IH: D1 vblank\n");
6479 } 6476 }
6477 if (atomic_read(&rdev->irq.pflip[0]))
6478 radeon_crtc_handle_vblank(rdev, 0);
6479 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
6480 DRM_DEBUG("IH: D1 vblank\n");
6481
6480 break; 6482 break;
6481 case 1: /* D1 vline */ 6483 case 1: /* D1 vline */
6482 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) { 6484 if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT))
6483 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; 6485 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6484 DRM_DEBUG("IH: D1 vline\n"); 6486
6485 } 6487 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
6488 DRM_DEBUG("IH: D1 vline\n");
6489
6486 break; 6490 break;
6487 default: 6491 default:
6488 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 6492 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@@ -6492,23 +6496,27 @@ restart_ih:
6492 case 2: /* D2 vblank/vline */ 6496 case 2: /* D2 vblank/vline */
6493 switch (src_data) { 6497 switch (src_data) {
6494 case 0: /* D2 vblank */ 6498 case 0: /* D2 vblank */
6495 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { 6499 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT))
6496 if (rdev->irq.crtc_vblank_int[1]) { 6500 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6497 drm_handle_vblank(rdev->ddev, 1); 6501
6498 rdev->pm.vblank_sync = true; 6502 if (rdev->irq.crtc_vblank_int[1]) {
6499 wake_up(&rdev->irq.vblank_queue); 6503 drm_handle_vblank(rdev->ddev, 1);
6500 } 6504 rdev->pm.vblank_sync = true;
6501 if (atomic_read(&rdev->irq.pflip[1])) 6505 wake_up(&rdev->irq.vblank_queue);
6502 radeon_crtc_handle_vblank(rdev, 1);
6503 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
6504 DRM_DEBUG("IH: D2 vblank\n");
6505 } 6506 }
6507 if (atomic_read(&rdev->irq.pflip[1]))
6508 radeon_crtc_handle_vblank(rdev, 1);
6509 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
6510 DRM_DEBUG("IH: D2 vblank\n");
6511
6506 break; 6512 break;
6507 case 1: /* D2 vline */ 6513 case 1: /* D2 vline */
6508 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) { 6514 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT))
6509 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; 6515 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6510 DRM_DEBUG("IH: D2 vline\n"); 6516
6511 } 6517 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
6518 DRM_DEBUG("IH: D2 vline\n");
6519
6512 break; 6520 break;
6513 default: 6521 default:
6514 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 6522 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@@ -6518,23 +6526,27 @@ restart_ih:
6518 case 3: /* D3 vblank/vline */ 6526 case 3: /* D3 vblank/vline */
6519 switch (src_data) { 6527 switch (src_data) {
6520 case 0: /* D3 vblank */ 6528 case 0: /* D3 vblank */
6521 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { 6529 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT))
6522 if (rdev->irq.crtc_vblank_int[2]) { 6530 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6523 drm_handle_vblank(rdev->ddev, 2); 6531
6524 rdev->pm.vblank_sync = true; 6532 if (rdev->irq.crtc_vblank_int[2]) {
6525 wake_up(&rdev->irq.vblank_queue); 6533 drm_handle_vblank(rdev->ddev, 2);
6526 } 6534 rdev->pm.vblank_sync = true;
6527 if (atomic_read(&rdev->irq.pflip[2])) 6535 wake_up(&rdev->irq.vblank_queue);
6528 radeon_crtc_handle_vblank(rdev, 2);
6529 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
6530 DRM_DEBUG("IH: D3 vblank\n");
6531 } 6536 }
6537 if (atomic_read(&rdev->irq.pflip[2]))
6538 radeon_crtc_handle_vblank(rdev, 2);
6539 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
6540 DRM_DEBUG("IH: D3 vblank\n");
6541
6532 break; 6542 break;
6533 case 1: /* D3 vline */ 6543 case 1: /* D3 vline */
6534 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { 6544 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT))
6535 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; 6545 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6536 DRM_DEBUG("IH: D3 vline\n"); 6546
6537 } 6547 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
6548 DRM_DEBUG("IH: D3 vline\n");
6549
6538 break; 6550 break;
6539 default: 6551 default:
6540 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 6552 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@@ -6544,23 +6556,27 @@ restart_ih:
6544 case 4: /* D4 vblank/vline */ 6556 case 4: /* D4 vblank/vline */
6545 switch (src_data) { 6557 switch (src_data) {
6546 case 0: /* D4 vblank */ 6558 case 0: /* D4 vblank */
6547 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { 6559 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT))
6548 if (rdev->irq.crtc_vblank_int[3]) { 6560 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6549 drm_handle_vblank(rdev->ddev, 3); 6561
6550 rdev->pm.vblank_sync = true; 6562 if (rdev->irq.crtc_vblank_int[3]) {
6551 wake_up(&rdev->irq.vblank_queue); 6563 drm_handle_vblank(rdev->ddev, 3);
6552 } 6564 rdev->pm.vblank_sync = true;
6553 if (atomic_read(&rdev->irq.pflip[3])) 6565 wake_up(&rdev->irq.vblank_queue);
6554 radeon_crtc_handle_vblank(rdev, 3);
6555 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
6556 DRM_DEBUG("IH: D4 vblank\n");
6557 } 6566 }
6567 if (atomic_read(&rdev->irq.pflip[3]))
6568 radeon_crtc_handle_vblank(rdev, 3);
6569 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
6570 DRM_DEBUG("IH: D4 vblank\n");
6571
6558 break; 6572 break;
6559 case 1: /* D4 vline */ 6573 case 1: /* D4 vline */
6560 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { 6574 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT))
6561 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; 6575 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6562 DRM_DEBUG("IH: D4 vline\n"); 6576
6563 } 6577 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
6578 DRM_DEBUG("IH: D4 vline\n");
6579
6564 break; 6580 break;
6565 default: 6581 default:
6566 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 6582 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@@ -6570,23 +6586,27 @@ restart_ih:
6570 case 5: /* D5 vblank/vline */ 6586 case 5: /* D5 vblank/vline */
6571 switch (src_data) { 6587 switch (src_data) {
6572 case 0: /* D5 vblank */ 6588 case 0: /* D5 vblank */
6573 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { 6589 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT))
6574 if (rdev->irq.crtc_vblank_int[4]) { 6590 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6575 drm_handle_vblank(rdev->ddev, 4); 6591
6576 rdev->pm.vblank_sync = true; 6592 if (rdev->irq.crtc_vblank_int[4]) {
6577 wake_up(&rdev->irq.vblank_queue); 6593 drm_handle_vblank(rdev->ddev, 4);
6578 } 6594 rdev->pm.vblank_sync = true;
6579 if (atomic_read(&rdev->irq.pflip[4])) 6595 wake_up(&rdev->irq.vblank_queue);
6580 radeon_crtc_handle_vblank(rdev, 4);
6581 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
6582 DRM_DEBUG("IH: D5 vblank\n");
6583 } 6596 }
6597 if (atomic_read(&rdev->irq.pflip[4]))
6598 radeon_crtc_handle_vblank(rdev, 4);
6599 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
6600 DRM_DEBUG("IH: D5 vblank\n");
6601
6584 break; 6602 break;
6585 case 1: /* D5 vline */ 6603 case 1: /* D5 vline */
6586 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { 6604 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT))
6587 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; 6605 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6588 DRM_DEBUG("IH: D5 vline\n"); 6606
6589 } 6607 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
6608 DRM_DEBUG("IH: D5 vline\n");
6609
6590 break; 6610 break;
6591 default: 6611 default:
6592 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 6612 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@@ -6596,23 +6616,27 @@ restart_ih:
6596 case 6: /* D6 vblank/vline */ 6616 case 6: /* D6 vblank/vline */
6597 switch (src_data) { 6617 switch (src_data) {
6598 case 0: /* D6 vblank */ 6618 case 0: /* D6 vblank */
6599 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { 6619 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT))
6600 if (rdev->irq.crtc_vblank_int[5]) { 6620 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6601 drm_handle_vblank(rdev->ddev, 5); 6621
6602 rdev->pm.vblank_sync = true; 6622 if (rdev->irq.crtc_vblank_int[5]) {
6603 wake_up(&rdev->irq.vblank_queue); 6623 drm_handle_vblank(rdev->ddev, 5);
6604 } 6624 rdev->pm.vblank_sync = true;
6605 if (atomic_read(&rdev->irq.pflip[5])) 6625 wake_up(&rdev->irq.vblank_queue);
6606 radeon_crtc_handle_vblank(rdev, 5);
6607 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
6608 DRM_DEBUG("IH: D6 vblank\n");
6609 } 6626 }
6627 if (atomic_read(&rdev->irq.pflip[5]))
6628 radeon_crtc_handle_vblank(rdev, 5);
6629 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
6630 DRM_DEBUG("IH: D6 vblank\n");
6631
6610 break; 6632 break;
6611 case 1: /* D6 vline */ 6633 case 1: /* D6 vline */
6612 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { 6634 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT))
6613 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; 6635 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6614 DRM_DEBUG("IH: D6 vline\n"); 6636
6615 } 6637 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
6638 DRM_DEBUG("IH: D6 vline\n");
6639
6616 break; 6640 break;
6617 default: 6641 default:
6618 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 6642 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@@ -6632,88 +6656,112 @@ restart_ih:
6632 case 42: /* HPD hotplug */ 6656 case 42: /* HPD hotplug */
6633 switch (src_data) { 6657 switch (src_data) {
6634 case 0: 6658 case 0:
6635 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 6659 if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT))
6636 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; 6660 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6637 queue_hotplug = true; 6661
6638 DRM_DEBUG("IH: HPD1\n"); 6662 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
6639 } 6663 queue_hotplug = true;
6664 DRM_DEBUG("IH: HPD1\n");
6665
6640 break; 6666 break;
6641 case 1: 6667 case 1:
6642 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { 6668 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT))
6643 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; 6669 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6644 queue_hotplug = true; 6670
6645 DRM_DEBUG("IH: HPD2\n"); 6671 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
6646 } 6672 queue_hotplug = true;
6673 DRM_DEBUG("IH: HPD2\n");
6674
6647 break; 6675 break;
6648 case 2: 6676 case 2:
6649 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { 6677 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT))
6650 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; 6678 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6651 queue_hotplug = true; 6679
6652 DRM_DEBUG("IH: HPD3\n"); 6680 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
6653 } 6681 queue_hotplug = true;
6682 DRM_DEBUG("IH: HPD3\n");
6683
6654 break; 6684 break;
6655 case 3: 6685 case 3:
6656 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { 6686 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT))
6657 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; 6687 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6658 queue_hotplug = true; 6688
6659 DRM_DEBUG("IH: HPD4\n"); 6689 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
6660 } 6690 queue_hotplug = true;
6691 DRM_DEBUG("IH: HPD4\n");
6692
6661 break; 6693 break;
6662 case 4: 6694 case 4:
6663 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { 6695 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT))
6664 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; 6696 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6665 queue_hotplug = true; 6697
6666 DRM_DEBUG("IH: HPD5\n"); 6698 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
6667 } 6699 queue_hotplug = true;
6700 DRM_DEBUG("IH: HPD5\n");
6701
6668 break; 6702 break;
6669 case 5: 6703 case 5:
6670 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { 6704 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT))
6671 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; 6705 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6672 queue_hotplug = true; 6706
6673 DRM_DEBUG("IH: HPD6\n"); 6707 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
6674 } 6708 queue_hotplug = true;
6709 DRM_DEBUG("IH: HPD6\n");
6710
6675 break; 6711 break;
6676 case 6: 6712 case 6:
6677 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT) { 6713 if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT))
6678 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT; 6714 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6679 queue_dp = true; 6715
6680 DRM_DEBUG("IH: HPD_RX 1\n"); 6716 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT;
6681 } 6717 queue_dp = true;
6718 DRM_DEBUG("IH: HPD_RX 1\n");
6719
6682 break; 6720 break;
6683 case 7: 6721 case 7:
6684 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT) { 6722 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT))
6685 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT; 6723 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6686 queue_dp = true; 6724
6687 DRM_DEBUG("IH: HPD_RX 2\n"); 6725 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT;
6688 } 6726 queue_dp = true;
6727 DRM_DEBUG("IH: HPD_RX 2\n");
6728
6689 break; 6729 break;
6690 case 8: 6730 case 8:
6691 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) { 6731 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT))
6692 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT; 6732 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6693 queue_dp = true; 6733
6694 DRM_DEBUG("IH: HPD_RX 3\n"); 6734 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT;
6695 } 6735 queue_dp = true;
6736 DRM_DEBUG("IH: HPD_RX 3\n");
6737
6696 break; 6738 break;
6697 case 9: 6739 case 9:
6698 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) { 6740 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT))
6699 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT; 6741 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6700 queue_dp = true; 6742
6701 DRM_DEBUG("IH: HPD_RX 4\n"); 6743 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT;
6702 } 6744 queue_dp = true;
6745 DRM_DEBUG("IH: HPD_RX 4\n");
6746
6703 break; 6747 break;
6704 case 10: 6748 case 10:
6705 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) { 6749 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT))
6706 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT; 6750 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6707 queue_dp = true; 6751
6708 DRM_DEBUG("IH: HPD_RX 5\n"); 6752 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT;
6709 } 6753 queue_dp = true;
6754 DRM_DEBUG("IH: HPD_RX 5\n");
6755
6710 break; 6756 break;
6711 case 11: 6757 case 11:
6712 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) { 6758 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT))
6713 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT; 6759 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6714 queue_dp = true; 6760
6715 DRM_DEBUG("IH: HPD_RX 6\n"); 6761 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT;
6716 } 6762 queue_dp = true;
6763 DRM_DEBUG("IH: HPD_RX 6\n");
6764
6717 break; 6765 break;
6718 default: 6766 default:
6719 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 6767 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-06 23:17:35 -0500