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-rw-r--r--drivers/gpu/drm/mediatek/Kconfig9
-rw-r--r--drivers/gpu/drm/mediatek/Makefile7
-rw-r--r--drivers/gpu/drm/mediatek/mtk_cec.c265
-rw-r--r--drivers/gpu/drm/mediatek/mtk_cec.h26
-rw-r--r--drivers/gpu/drm/mediatek/mtk_dpi.c5
-rw-r--r--drivers/gpu/drm/mediatek/mtk_drm_drv.c13
-rw-r--r--drivers/gpu/drm/mediatek/mtk_drm_plane.c1
-rw-r--r--drivers/gpu/drm/mediatek/mtk_dsi.c13
-rw-r--r--drivers/gpu/drm/mediatek/mtk_hdmi.c1828
-rw-r--r--drivers/gpu/drm/mediatek/mtk_hdmi.h23
-rw-r--r--drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c358
-rw-r--r--drivers/gpu/drm/mediatek/mtk_hdmi_regs.h238
-rw-r--r--drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c515
13 files changed, 3272 insertions, 29 deletions
diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
index eeefc971801a..23ac8041c562 100644
--- a/drivers/gpu/drm/mediatek/Kconfig
+++ b/drivers/gpu/drm/mediatek/Kconfig
@@ -6,7 +6,6 @@ config DRM_MEDIATEK
6 select DRM_KMS_HELPER 6 select DRM_KMS_HELPER
7 select DRM_MIPI_DSI 7 select DRM_MIPI_DSI
8 select DRM_PANEL 8 select DRM_PANEL
9 select IOMMU_DMA
10 select MEMORY 9 select MEMORY
11 select MTK_SMI 10 select MTK_SMI
12 help 11 help
@@ -14,3 +13,11 @@ config DRM_MEDIATEK
14 The module will be called mediatek-drm 13 The module will be called mediatek-drm
15 This driver provides kernel mode setting and 14 This driver provides kernel mode setting and
16 buffer management to userspace. 15 buffer management to userspace.
16
17config DRM_MEDIATEK_HDMI
18 tristate "DRM HDMI Support for Mediatek SoCs"
19 depends on DRM_MEDIATEK
20 select SND_SOC_HDMI_CODEC if SND_SOC
21 select GENERIC_PHY
22 help
23 DRM/KMS HDMI driver for Mediatek SoCs
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 5fcf58e87786..bf2e5be1ab30 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -12,3 +12,10 @@ mediatek-drm-y := mtk_disp_ovl.o \
12 mtk_dpi.o 12 mtk_dpi.o
13 13
14obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o 14obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
15
16mediatek-drm-hdmi-objs := mtk_cec.o \
17 mtk_hdmi.o \
18 mtk_hdmi_ddc.o \
19 mtk_mt8173_hdmi_phy.o
20
21obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c b/drivers/gpu/drm/mediatek/mtk_cec.c
new file mode 100644
index 000000000000..7a3eb8c17ef9
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_cec.c
@@ -0,0 +1,265 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Jie Qiu <jie.qiu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/io.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19
20#include "mtk_cec.h"
21
22#define TR_CONFIG 0x00
23#define CLEAR_CEC_IRQ BIT(15)
24
25#define CEC_CKGEN 0x04
26#define CEC_32K_PDN BIT(19)
27#define PDN BIT(16)
28
29#define RX_EVENT 0x54
30#define HDMI_PORD BIT(25)
31#define HDMI_HTPLG BIT(24)
32#define HDMI_PORD_INT_EN BIT(9)
33#define HDMI_HTPLG_INT_EN BIT(8)
34
35#define RX_GEN_WD 0x58
36#define HDMI_PORD_INT_32K_STATUS BIT(26)
37#define RX_RISC_INT_32K_STATUS BIT(25)
38#define HDMI_HTPLG_INT_32K_STATUS BIT(24)
39#define HDMI_PORD_INT_32K_CLR BIT(18)
40#define RX_INT_32K_CLR BIT(17)
41#define HDMI_HTPLG_INT_32K_CLR BIT(16)
42#define HDMI_PORD_INT_32K_STA_MASK BIT(10)
43#define RX_RISC_INT_32K_STA_MASK BIT(9)
44#define HDMI_HTPLG_INT_32K_STA_MASK BIT(8)
45#define HDMI_PORD_INT_32K_EN BIT(2)
46#define RX_INT_32K_EN BIT(1)
47#define HDMI_HTPLG_INT_32K_EN BIT(0)
48
49#define NORMAL_INT_CTRL 0x5C
50#define HDMI_HTPLG_INT_STA BIT(0)
51#define HDMI_PORD_INT_STA BIT(1)
52#define HDMI_HTPLG_INT_CLR BIT(16)
53#define HDMI_PORD_INT_CLR BIT(17)
54#define HDMI_FULL_INT_CLR BIT(20)
55
56struct mtk_cec {
57 void __iomem *regs;
58 struct clk *clk;
59 int irq;
60 bool hpd;
61 void (*hpd_event)(bool hpd, struct device *dev);
62 struct device *hdmi_dev;
63 spinlock_t lock;
64};
65
66static void mtk_cec_clear_bits(struct mtk_cec *cec, unsigned int offset,
67 unsigned int bits)
68{
69 void __iomem *reg = cec->regs + offset;
70 u32 tmp;
71
72 tmp = readl(reg);
73 tmp &= ~bits;
74 writel(tmp, reg);
75}
76
77static void mtk_cec_set_bits(struct mtk_cec *cec, unsigned int offset,
78 unsigned int bits)
79{
80 void __iomem *reg = cec->regs + offset;
81 u32 tmp;
82
83 tmp = readl(reg);
84 tmp |= bits;
85 writel(tmp, reg);
86}
87
88static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset,
89 unsigned int val, unsigned int mask)
90{
91 u32 tmp = readl(cec->regs + offset) & ~mask;
92
93 tmp |= val & mask;
94 writel(val, cec->regs + offset);
95}
96
97void mtk_cec_set_hpd_event(struct device *dev,
98 void (*hpd_event)(bool hpd, struct device *dev),
99 struct device *hdmi_dev)
100{
101 struct mtk_cec *cec = dev_get_drvdata(dev);
102 unsigned long flags;
103
104 spin_lock_irqsave(&cec->lock, flags);
105 cec->hdmi_dev = hdmi_dev;
106 cec->hpd_event = hpd_event;
107 spin_unlock_irqrestore(&cec->lock, flags);
108}
109
110bool mtk_cec_hpd_high(struct device *dev)
111{
112 struct mtk_cec *cec = dev_get_drvdata(dev);
113 unsigned int status;
114
115 status = readl(cec->regs + RX_EVENT);
116
117 return (status & (HDMI_PORD | HDMI_HTPLG)) == (HDMI_PORD | HDMI_HTPLG);
118}
119
120static void mtk_cec_htplg_irq_init(struct mtk_cec *cec)
121{
122 mtk_cec_mask(cec, CEC_CKGEN, 0 | CEC_32K_PDN, PDN | CEC_32K_PDN);
123 mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
124 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
125 mtk_cec_mask(cec, RX_GEN_WD, 0, HDMI_PORD_INT_32K_CLR | RX_INT_32K_CLR |
126 HDMI_HTPLG_INT_32K_CLR | HDMI_PORD_INT_32K_EN |
127 RX_INT_32K_EN | HDMI_HTPLG_INT_32K_EN);
128}
129
130static void mtk_cec_htplg_irq_enable(struct mtk_cec *cec)
131{
132 mtk_cec_set_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
133}
134
135static void mtk_cec_htplg_irq_disable(struct mtk_cec *cec)
136{
137 mtk_cec_clear_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
138}
139
140static void mtk_cec_clear_htplg_irq(struct mtk_cec *cec)
141{
142 mtk_cec_set_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
143 mtk_cec_set_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
144 HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
145 mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
146 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
147 usleep_range(5, 10);
148 mtk_cec_clear_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
149 HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
150 mtk_cec_clear_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
151 mtk_cec_clear_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
152 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
153}
154
155static void mtk_cec_hpd_event(struct mtk_cec *cec, bool hpd)
156{
157 void (*hpd_event)(bool hpd, struct device *dev);
158 struct device *hdmi_dev;
159 unsigned long flags;
160
161 spin_lock_irqsave(&cec->lock, flags);
162 hpd_event = cec->hpd_event;
163 hdmi_dev = cec->hdmi_dev;
164 spin_unlock_irqrestore(&cec->lock, flags);
165
166 if (hpd_event)
167 hpd_event(hpd, hdmi_dev);
168}
169
170static irqreturn_t mtk_cec_htplg_isr_thread(int irq, void *arg)
171{
172 struct device *dev = arg;
173 struct mtk_cec *cec = dev_get_drvdata(dev);
174 bool hpd;
175
176 mtk_cec_clear_htplg_irq(cec);
177 hpd = mtk_cec_hpd_high(dev);
178
179 if (cec->hpd != hpd) {
180 dev_dbg(dev, "hotplug event! cur hpd = %d, hpd = %d\n",
181 cec->hpd, hpd);
182 cec->hpd = hpd;
183 mtk_cec_hpd_event(cec, hpd);
184 }
185 return IRQ_HANDLED;
186}
187
188static int mtk_cec_probe(struct platform_device *pdev)
189{
190 struct device *dev = &pdev->dev;
191 struct mtk_cec *cec;
192 struct resource *res;
193 int ret;
194
195 cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);
196 if (!cec)
197 return -ENOMEM;
198
199 platform_set_drvdata(pdev, cec);
200 spin_lock_init(&cec->lock);
201
202 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
203 cec->regs = devm_ioremap_resource(dev, res);
204 if (IS_ERR(cec->regs)) {
205 ret = PTR_ERR(cec->regs);
206 dev_err(dev, "Failed to ioremap cec: %d\n", ret);
207 return ret;
208 }
209
210 cec->clk = devm_clk_get(dev, NULL);
211 if (IS_ERR(cec->clk)) {
212 ret = PTR_ERR(cec->clk);
213 dev_err(dev, "Failed to get cec clock: %d\n", ret);
214 return ret;
215 }
216
217 cec->irq = platform_get_irq(pdev, 0);
218 if (cec->irq < 0) {
219 dev_err(dev, "Failed to get cec irq: %d\n", cec->irq);
220 return cec->irq;
221 }
222
223 ret = devm_request_threaded_irq(dev, cec->irq, NULL,
224 mtk_cec_htplg_isr_thread,
225 IRQF_SHARED | IRQF_TRIGGER_LOW |
226 IRQF_ONESHOT, "hdmi hpd", dev);
227 if (ret) {
228 dev_err(dev, "Failed to register cec irq: %d\n", ret);
229 return ret;
230 }
231
232 ret = clk_prepare_enable(cec->clk);
233 if (ret) {
234 dev_err(dev, "Failed to enable cec clock: %d\n", ret);
235 return ret;
236 }
237
238 mtk_cec_htplg_irq_init(cec);
239 mtk_cec_htplg_irq_enable(cec);
240
241 return 0;
242}
243
244static int mtk_cec_remove(struct platform_device *pdev)
245{
246 struct mtk_cec *cec = platform_get_drvdata(pdev);
247
248 mtk_cec_htplg_irq_disable(cec);
249 clk_disable_unprepare(cec->clk);
250 return 0;
251}
252
253static const struct of_device_id mtk_cec_of_ids[] = {
254 { .compatible = "mediatek,mt8173-cec", },
255 {}
256};
257
258struct platform_driver mtk_cec_driver = {
259 .probe = mtk_cec_probe,
260 .remove = mtk_cec_remove,
261 .driver = {
262 .name = "mediatek-cec",
263 .of_match_table = mtk_cec_of_ids,
264 },
265};
diff --git a/drivers/gpu/drm/mediatek/mtk_cec.h b/drivers/gpu/drm/mediatek/mtk_cec.h
new file mode 100644
index 000000000000..10057b7eabec
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_cec.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Jie Qiu <jie.qiu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#ifndef _MTK_CEC_H
15#define _MTK_CEC_H
16
17#include <linux/types.h>
18
19struct device;
20
21void mtk_cec_set_hpd_event(struct device *dev,
22 void (*hotplug_event)(bool hpd, struct device *dev),
23 struct device *hdmi_dev);
24bool mtk_cec_hpd_high(struct device *dev);
25
26#endif /* _MTK_CEC_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index d05ca7901315..0186e500d2a5 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -432,11 +432,6 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
432 unsigned long pll_rate; 432 unsigned long pll_rate;
433 unsigned int factor; 433 unsigned int factor;
434 434
435 if (!dpi) {
436 dev_err(dpi->dev, "invalid argument\n");
437 return -EINVAL;
438 }
439
440 pix_rate = 1000UL * mode->clock; 435 pix_rate = 1000UL * mode->clock;
441 if (mode->clock <= 74000) 436 if (mode->clock <= 74000)
442 factor = 8 * 3; 437 factor = 8 * 3;
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b1223d54d0ab..eebb7d881c2b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -91,7 +91,7 @@ static int mtk_atomic_commit(struct drm_device *drm,
91 mutex_lock(&private->commit.lock); 91 mutex_lock(&private->commit.lock);
92 flush_work(&private->commit.work); 92 flush_work(&private->commit.work);
93 93
94 drm_atomic_helper_swap_state(drm, state); 94 drm_atomic_helper_swap_state(state, true);
95 95
96 if (async) 96 if (async)
97 mtk_atomic_schedule(private, state); 97 mtk_atomic_schedule(private, state);
@@ -243,7 +243,7 @@ static struct drm_driver mtk_drm_driver = {
243 .enable_vblank = mtk_drm_crtc_enable_vblank, 243 .enable_vblank = mtk_drm_crtc_enable_vblank,
244 .disable_vblank = mtk_drm_crtc_disable_vblank, 244 .disable_vblank = mtk_drm_crtc_disable_vblank,
245 245
246 .gem_free_object = mtk_drm_gem_free_object, 246 .gem_free_object_unlocked = mtk_drm_gem_free_object,
247 .gem_vm_ops = &drm_gem_cma_vm_ops, 247 .gem_vm_ops = &drm_gem_cma_vm_ops,
248 .dumb_create = mtk_drm_gem_dumb_create, 248 .dumb_create = mtk_drm_gem_dumb_create,
249 .dumb_map_offset = mtk_drm_gem_dumb_map_offset, 249 .dumb_map_offset = mtk_drm_gem_dumb_map_offset,
@@ -280,8 +280,6 @@ static int mtk_drm_bind(struct device *dev)
280 if (!drm) 280 if (!drm)
281 return -ENOMEM; 281 return -ENOMEM;
282 282
283 drm_dev_set_unique(drm, dev_name(dev));
284
285 drm->dev_private = private; 283 drm->dev_private = private;
286 private->drm = drm; 284 private->drm = drm;
287 285
@@ -293,14 +291,8 @@ static int mtk_drm_bind(struct device *dev)
293 if (ret < 0) 291 if (ret < 0)
294 goto err_deinit; 292 goto err_deinit;
295 293
296 ret = drm_connector_register_all(drm);
297 if (ret < 0)
298 goto err_unregister;
299
300 return 0; 294 return 0;
301 295
302err_unregister:
303 drm_dev_unregister(drm);
304err_deinit: 296err_deinit:
305 mtk_drm_kms_deinit(drm); 297 mtk_drm_kms_deinit(drm);
306err_free: 298err_free:
@@ -455,7 +447,6 @@ static int mtk_drm_remove(struct platform_device *pdev)
455 struct drm_device *drm = private->drm; 447 struct drm_device *drm = private->drm;
456 int i; 448 int i;
457 449
458 drm_connector_unregister_all(drm);
459 drm_dev_unregister(drm); 450 drm_dev_unregister(drm);
460 mtk_drm_kms_deinit(drm); 451 mtk_drm_kms_deinit(drm);
461 drm_dev_unref(drm); 452 drm_dev_unref(drm);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
index 51bc8988fc26..3995765a90dc 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
@@ -170,6 +170,7 @@ static int mtk_plane_atomic_check(struct drm_plane *plane,
170 170
171 return drm_plane_helper_check_update(plane, state->crtc, fb, 171 return drm_plane_helper_check_update(plane, state->crtc, fb,
172 &src, &dest, &clip, 172 &src, &dest, &clip,
173 state->rotation,
173 DRM_PLANE_HELPER_NO_SCALING, 174 DRM_PLANE_HELPER_NO_SCALING,
174 DRM_PLANE_HELPER_NO_SCALING, 175 DRM_PLANE_HELPER_NO_SCALING,
175 true, true, &visible); 176 true, true, &visible);
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 2d808e59fefd..28b2044ed9f2 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -575,14 +575,6 @@ static int mtk_dsi_connector_get_modes(struct drm_connector *connector)
575 return drm_panel_get_modes(dsi->panel); 575 return drm_panel_get_modes(dsi->panel);
576} 576}
577 577
578static struct drm_encoder *mtk_dsi_connector_best_encoder(
579 struct drm_connector *connector)
580{
581 struct mtk_dsi *dsi = connector_to_dsi(connector);
582
583 return &dsi->encoder;
584}
585
586static const struct drm_encoder_helper_funcs mtk_dsi_encoder_helper_funcs = { 578static const struct drm_encoder_helper_funcs mtk_dsi_encoder_helper_funcs = {
587 .mode_fixup = mtk_dsi_encoder_mode_fixup, 579 .mode_fixup = mtk_dsi_encoder_mode_fixup,
588 .mode_set = mtk_dsi_encoder_mode_set, 580 .mode_set = mtk_dsi_encoder_mode_set,
@@ -603,7 +595,6 @@ static const struct drm_connector_funcs mtk_dsi_connector_funcs = {
603static const struct drm_connector_helper_funcs 595static const struct drm_connector_helper_funcs
604 mtk_dsi_connector_helper_funcs = { 596 mtk_dsi_connector_helper_funcs = {
605 .get_modes = mtk_dsi_connector_get_modes, 597 .get_modes = mtk_dsi_connector_get_modes,
606 .best_encoder = mtk_dsi_connector_best_encoder,
607}; 598};
608 599
609static int mtk_drm_attach_bridge(struct drm_bridge *bridge, 600static int mtk_drm_attach_bridge(struct drm_bridge *bridge,
@@ -695,10 +686,8 @@ static void mtk_dsi_destroy_conn_enc(struct mtk_dsi *dsi)
695{ 686{
696 drm_encoder_cleanup(&dsi->encoder); 687 drm_encoder_cleanup(&dsi->encoder);
697 /* Skip connector cleanup if creation was delegated to the bridge */ 688 /* Skip connector cleanup if creation was delegated to the bridge */
698 if (dsi->conn.dev) { 689 if (dsi->conn.dev)
699 drm_connector_unregister(&dsi->conn);
700 drm_connector_cleanup(&dsi->conn); 690 drm_connector_cleanup(&dsi->conn);
701 }
702} 691}
703 692
704static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp) 693static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
new file mode 100644
index 000000000000..334562d06731
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -0,0 +1,1828 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Jie Qiu <jie.qiu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#include <drm/drmP.h>
15#include <drm/drm_atomic_helper.h>
16#include <drm/drm_crtc.h>
17#include <drm/drm_crtc_helper.h>
18#include <drm/drm_edid.h>
19#include <linux/arm-smccc.h>
20#include <linux/clk.h>
21#include <linux/delay.h>
22#include <linux/hdmi.h>
23#include <linux/i2c.h>
24#include <linux/io.h>
25#include <linux/kernel.h>
26#include <linux/mfd/syscon.h>
27#include <linux/of_platform.h>
28#include <linux/of.h>
29#include <linux/of_gpio.h>
30#include <linux/of_graph.h>
31#include <linux/phy/phy.h>
32#include <linux/platform_device.h>
33#include <linux/regmap.h>
34#include <sound/hdmi-codec.h>
35#include "mtk_cec.h"
36#include "mtk_hdmi.h"
37#include "mtk_hdmi_regs.h"
38
39#define NCTS_BYTES 7
40
41enum mtk_hdmi_clk_id {
42 MTK_HDMI_CLK_HDMI_PIXEL,
43 MTK_HDMI_CLK_HDMI_PLL,
44 MTK_HDMI_CLK_AUD_BCLK,
45 MTK_HDMI_CLK_AUD_SPDIF,
46 MTK_HDMI_CLK_COUNT
47};
48
49enum hdmi_aud_input_type {
50 HDMI_AUD_INPUT_I2S = 0,
51 HDMI_AUD_INPUT_SPDIF,
52};
53
54enum hdmi_aud_i2s_fmt {
55 HDMI_I2S_MODE_RJT_24BIT = 0,
56 HDMI_I2S_MODE_RJT_16BIT,
57 HDMI_I2S_MODE_LJT_24BIT,
58 HDMI_I2S_MODE_LJT_16BIT,
59 HDMI_I2S_MODE_I2S_24BIT,
60 HDMI_I2S_MODE_I2S_16BIT
61};
62
63enum hdmi_aud_mclk {
64 HDMI_AUD_MCLK_128FS,
65 HDMI_AUD_MCLK_192FS,
66 HDMI_AUD_MCLK_256FS,
67 HDMI_AUD_MCLK_384FS,
68 HDMI_AUD_MCLK_512FS,
69 HDMI_AUD_MCLK_768FS,
70 HDMI_AUD_MCLK_1152FS,
71};
72
73enum hdmi_aud_channel_type {
74 HDMI_AUD_CHAN_TYPE_1_0 = 0,
75 HDMI_AUD_CHAN_TYPE_1_1,
76 HDMI_AUD_CHAN_TYPE_2_0,
77 HDMI_AUD_CHAN_TYPE_2_1,
78 HDMI_AUD_CHAN_TYPE_3_0,
79 HDMI_AUD_CHAN_TYPE_3_1,
80 HDMI_AUD_CHAN_TYPE_4_0,
81 HDMI_AUD_CHAN_TYPE_4_1,
82 HDMI_AUD_CHAN_TYPE_5_0,
83 HDMI_AUD_CHAN_TYPE_5_1,
84 HDMI_AUD_CHAN_TYPE_6_0,
85 HDMI_AUD_CHAN_TYPE_6_1,
86 HDMI_AUD_CHAN_TYPE_7_0,
87 HDMI_AUD_CHAN_TYPE_7_1,
88 HDMI_AUD_CHAN_TYPE_3_0_LRS,
89 HDMI_AUD_CHAN_TYPE_3_1_LRS,
90 HDMI_AUD_CHAN_TYPE_4_0_CLRS,
91 HDMI_AUD_CHAN_TYPE_4_1_CLRS,
92 HDMI_AUD_CHAN_TYPE_6_1_CS,
93 HDMI_AUD_CHAN_TYPE_6_1_CH,
94 HDMI_AUD_CHAN_TYPE_6_1_OH,
95 HDMI_AUD_CHAN_TYPE_6_1_CHR,
96 HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
97 HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
98 HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
99 HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
100 HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
101 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
102 HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
103 HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
104 HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
105 HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
106 HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
107 HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
108 HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
109 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
110 HDMI_AUD_CHAN_TYPE_6_0_CS,
111 HDMI_AUD_CHAN_TYPE_6_0_CH,
112 HDMI_AUD_CHAN_TYPE_6_0_OH,
113 HDMI_AUD_CHAN_TYPE_6_0_CHR,
114 HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
115 HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
116 HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
117 HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
118 HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
119 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
120 HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
121 HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
122 HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
123 HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
124 HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
125 HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
126 HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
127 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
128 HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
129 HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
130};
131
132enum hdmi_aud_channel_swap_type {
133 HDMI_AUD_SWAP_LR,
134 HDMI_AUD_SWAP_LFE_CC,
135 HDMI_AUD_SWAP_LSRS,
136 HDMI_AUD_SWAP_RLS_RRS,
137 HDMI_AUD_SWAP_LR_STATUS,
138};
139
140struct hdmi_audio_param {
141 enum hdmi_audio_coding_type aud_codec;
142 enum hdmi_audio_sample_size aud_sampe_size;
143 enum hdmi_aud_input_type aud_input_type;
144 enum hdmi_aud_i2s_fmt aud_i2s_fmt;
145 enum hdmi_aud_mclk aud_mclk;
146 enum hdmi_aud_channel_type aud_input_chan_type;
147 struct hdmi_codec_params codec_params;
148};
149
150struct mtk_hdmi {
151 struct drm_bridge bridge;
152 struct drm_connector conn;
153 struct device *dev;
154 struct phy *phy;
155 struct device *cec_dev;
156 struct i2c_adapter *ddc_adpt;
157 struct clk *clk[MTK_HDMI_CLK_COUNT];
158 struct drm_display_mode mode;
159 bool dvi_mode;
160 u32 min_clock;
161 u32 max_clock;
162 u32 max_hdisplay;
163 u32 max_vdisplay;
164 u32 ibias;
165 u32 ibias_up;
166 struct regmap *sys_regmap;
167 unsigned int sys_offset;
168 void __iomem *regs;
169 enum hdmi_colorspace csp;
170 struct hdmi_audio_param aud_param;
171 bool audio_enable;
172 bool powered;
173 bool enabled;
174};
175
176static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
177{
178 return container_of(b, struct mtk_hdmi, bridge);
179}
180
181static inline struct mtk_hdmi *hdmi_ctx_from_conn(struct drm_connector *c)
182{
183 return container_of(c, struct mtk_hdmi, conn);
184}
185
186static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
187{
188 return readl(hdmi->regs + offset);
189}
190
191static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
192{
193 writel(val, hdmi->regs + offset);
194}
195
196static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
197{
198 void __iomem *reg = hdmi->regs + offset;
199 u32 tmp;
200
201 tmp = readl(reg);
202 tmp &= ~bits;
203 writel(tmp, reg);
204}
205
206static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
207{
208 void __iomem *reg = hdmi->regs + offset;
209 u32 tmp;
210
211 tmp = readl(reg);
212 tmp |= bits;
213 writel(tmp, reg);
214}
215
216static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
217{
218 void __iomem *reg = hdmi->regs + offset;
219 u32 tmp;
220
221 tmp = readl(reg);
222 tmp = (tmp & ~mask) | (val & mask);
223 writel(tmp, reg);
224}
225
226static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
227{
228 mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH,
229 VIDEO_SOURCE_SEL);
230}
231
232static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
233{
234 struct arm_smccc_res res;
235
236 /*
237 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
238 * output. This bit can only be controlled in ARM supervisor mode.
239 * The ARM trusted firmware provides an API for the HDMI driver to set
240 * this control bit to enable HDMI output in supervisor mode.
241 */
242 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 0x80000000,
243 0, 0, 0, 0, 0, &res);
244
245 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
246 HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
247 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
248 HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0);
249}
250
251static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable)
252{
253 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
254 HDMI2P0_EN, enable ? 0 : HDMI2P0_EN);
255}
256
257static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi)
258{
259 mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
260}
261
262static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi)
263{
264 mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
265}
266
267static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
268{
269 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
270 HDMI_RST, HDMI_RST);
271 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
272 HDMI_RST, 0);
273 mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);
274 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
275 ANLG_ON, ANLG_ON);
276}
277
278static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice)
279{
280 mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0,
281 CFG2_NOTICE_EN);
282}
283
284static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask)
285{
286 mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask);
287}
288
289static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable)
290{
291 mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI);
292}
293
294static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer,
295 u8 len)
296{
297 u32 ctrl_reg = GRL_CTRL;
298 int i;
299 u8 *frame_data;
300 enum hdmi_infoframe_type frame_type;
301 u8 frame_ver;
302 u8 frame_len;
303 u8 checksum;
304 int ctrl_frame_en = 0;
305
306 frame_type = *buffer;
307 buffer += 1;
308 frame_ver = *buffer;
309 buffer += 1;
310 frame_len = *buffer;
311 buffer += 1;
312 checksum = *buffer;
313 buffer += 1;
314 frame_data = buffer;
315
316 dev_dbg(hdmi->dev,
317 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n",
318 frame_type, frame_ver, frame_len, checksum);
319
320 switch (frame_type) {
321 case HDMI_INFOFRAME_TYPE_AVI:
322 ctrl_frame_en = CTRL_AVI_EN;
323 ctrl_reg = GRL_CTRL;
324 break;
325 case HDMI_INFOFRAME_TYPE_SPD:
326 ctrl_frame_en = CTRL_SPD_EN;
327 ctrl_reg = GRL_CTRL;
328 break;
329 case HDMI_INFOFRAME_TYPE_AUDIO:
330 ctrl_frame_en = CTRL_AUDIO_EN;
331 ctrl_reg = GRL_CTRL;
332 break;
333 case HDMI_INFOFRAME_TYPE_VENDOR:
334 ctrl_frame_en = VS_EN;
335 ctrl_reg = GRL_ACP_ISRC_CTRL;
336 break;
337 }
338 mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en);
339 mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type);
340 mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver);
341 mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len);
342
343 mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum);
344 for (i = 0; i < frame_len; i++)
345 mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]);
346
347 mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en);
348}
349
350static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable)
351{
352 mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF,
353 AUDIO_PACKET_OFF);
354}
355
356static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi)
357{
358 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
359 HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0);
360 usleep_range(2000, 4000);
361 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
362 HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN);
363}
364
365static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi)
366{
367 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
368 DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN,
369 COLOR_8BIT_MODE);
370}
371
372static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi)
373{
374 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
375 usleep_range(2000, 4000);
376 mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
377}
378
379static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi)
380{
381 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN,
382 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
383 usleep_range(2000, 4000);
384 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET,
385 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
386}
387
388static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on)
389{
390 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT,
391 CTS_CTRL_SOFT);
392}
393
394static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi,
395 bool enable)
396{
397 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0,
398 NCTS_WRI_ANYTIME);
399}
400
401static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi,
402 struct drm_display_mode *mode)
403{
404 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE);
405
406 if (mode->flags & DRM_MODE_FLAG_INTERLACE &&
407 mode->clock == 74250 &&
408 mode->vdisplay == 1080)
409 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
410 else
411 mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
412}
413
414static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi,
415 enum hdmi_aud_channel_swap_type swap)
416{
417 u8 swap_bit;
418
419 switch (swap) {
420 case HDMI_AUD_SWAP_LR:
421 swap_bit = LR_SWAP;
422 break;
423 case HDMI_AUD_SWAP_LFE_CC:
424 swap_bit = LFE_CC_SWAP;
425 break;
426 case HDMI_AUD_SWAP_LSRS:
427 swap_bit = LSRS_SWAP;
428 break;
429 case HDMI_AUD_SWAP_RLS_RRS:
430 swap_bit = RLS_RRS_SWAP;
431 break;
432 case HDMI_AUD_SWAP_LR_STATUS:
433 swap_bit = LR_STATUS_SWAP;
434 break;
435 default:
436 swap_bit = LFE_CC_SWAP;
437 break;
438 }
439 mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff);
440}
441
442static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi,
443 enum hdmi_audio_sample_size bit_num)
444{
445 u32 val;
446
447 switch (bit_num) {
448 case HDMI_AUDIO_SAMPLE_SIZE_16:
449 val = AOUT_16BIT;
450 break;
451 case HDMI_AUDIO_SAMPLE_SIZE_20:
452 val = AOUT_20BIT;
453 break;
454 case HDMI_AUDIO_SAMPLE_SIZE_24:
455 case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
456 val = AOUT_24BIT;
457 break;
458 }
459
460 mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK);
461}
462
463static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
464 enum hdmi_aud_i2s_fmt i2s_fmt)
465{
466 u32 val;
467
468 val = mtk_hdmi_read(hdmi, GRL_CFG0);
469 val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
470
471 switch (i2s_fmt) {
472 case HDMI_I2S_MODE_RJT_24BIT:
473 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT;
474 break;
475 case HDMI_I2S_MODE_RJT_16BIT:
476 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT;
477 break;
478 case HDMI_I2S_MODE_LJT_24BIT:
479 default:
480 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT;
481 break;
482 case HDMI_I2S_MODE_LJT_16BIT:
483 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT;
484 break;
485 case HDMI_I2S_MODE_I2S_24BIT:
486 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT;
487 break;
488 case HDMI_I2S_MODE_I2S_16BIT:
489 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT;
490 break;
491 }
492 mtk_hdmi_write(hdmi, GRL_CFG0, val);
493}
494
495static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst)
496{
497 const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL;
498 u8 val;
499
500 /* Disable high bitrate, set DST packet normal/double */
501 mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);
502
503 if (dst)
504 val = DST_NORMAL_DOUBLE | SACD_DST;
505 else
506 val = 0;
507
508 mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask);
509}
510
511static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi,
512 enum hdmi_aud_channel_type channel_type,
513 u8 channel_count)
514{
515 unsigned int ch_switch;
516 u8 i2s_uv;
517
518 ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) |
519 CH_SWITCH(5, 5) | CH_SWITCH(4, 4) |
520 CH_SWITCH(3, 3) | CH_SWITCH(1, 2) |
521 CH_SWITCH(2, 1) | CH_SWITCH(0, 0);
522
523 if (channel_count == 2) {
524 i2s_uv = I2S_UV_CH_EN(0);
525 } else if (channel_count == 3 || channel_count == 4) {
526 if (channel_count == 4 &&
527 (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS ||
528 channel_type == HDMI_AUD_CHAN_TYPE_4_0))
529 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0);
530 else
531 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2);
532 } else if (channel_count == 6 || channel_count == 5) {
533 if (channel_count == 6 &&
534 channel_type != HDMI_AUD_CHAN_TYPE_5_1 &&
535 channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) {
536 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
537 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
538 } else {
539 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) |
540 I2S_UV_CH_EN(0);
541 }
542 } else if (channel_count == 8 || channel_count == 7) {
543 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
544 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
545 } else {
546 i2s_uv = I2S_UV_CH_EN(0);
547 }
548
549 mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff);
550 mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff);
551 mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff);
552 mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv);
553}
554
555static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
556 enum hdmi_aud_input_type input_type)
557{
558 u32 val;
559
560 val = mtk_hdmi_read(hdmi, GRL_CFG1);
561 if (input_type == HDMI_AUD_INPUT_I2S &&
562 (val & CFG1_SPDIF) == CFG1_SPDIF) {
563 val &= ~CFG1_SPDIF;
564 } else if (input_type == HDMI_AUD_INPUT_SPDIF &&
565 (val & CFG1_SPDIF) == 0) {
566 val |= CFG1_SPDIF;
567 }
568 mtk_hdmi_write(hdmi, GRL_CFG1, val);
569}
570
571static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi,
572 u8 *channel_status)
573{
574 int i;
575
576 for (i = 0; i < 5; i++) {
577 mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]);
578 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]);
579 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]);
580 }
581 for (; i < 24; i++) {
582 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0);
583 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0);
584 }
585}
586
587static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
588{
589 u32 val;
590
591 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
592 if (val & MIX_CTRL_SRC_EN) {
593 val &= ~MIX_CTRL_SRC_EN;
594 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
595 usleep_range(255, 512);
596 val |= MIX_CTRL_SRC_EN;
597 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
598 }
599}
600
601static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
602{
603 u32 val;
604
605 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
606 val &= ~MIX_CTRL_SRC_EN;
607 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
608 mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
609}
610
611static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
612 enum hdmi_aud_mclk mclk)
613{
614 u32 val;
615
616 val = mtk_hdmi_read(hdmi, GRL_CFG5);
617 val &= CFG5_CD_RATIO_MASK;
618
619 switch (mclk) {
620 case HDMI_AUD_MCLK_128FS:
621 val |= CFG5_FS128;
622 break;
623 case HDMI_AUD_MCLK_256FS:
624 val |= CFG5_FS256;
625 break;
626 case HDMI_AUD_MCLK_384FS:
627 val |= CFG5_FS384;
628 break;
629 case HDMI_AUD_MCLK_512FS:
630 val |= CFG5_FS512;
631 break;
632 case HDMI_AUD_MCLK_768FS:
633 val |= CFG5_FS768;
634 break;
635 default:
636 val |= CFG5_FS256;
637 break;
638 }
639 mtk_hdmi_write(hdmi, GRL_CFG5, val);
640}
641
642struct hdmi_acr_n {
643 unsigned int clock;
644 unsigned int n[3];
645};
646
647/* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
648static const struct hdmi_acr_n hdmi_rec_n_table[] = {
649 /* Clock, N: 32kHz 44.1kHz 48kHz */
650 { 25175, { 4576, 7007, 6864 } },
651 { 74176, { 11648, 17836, 11648 } },
652 { 148352, { 11648, 8918, 5824 } },
653 { 296703, { 5824, 4459, 5824 } },
654 { 297000, { 3072, 4704, 5120 } },
655 { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */
656};
657
658/**
659 * hdmi_recommended_n() - Return N value recommended by HDMI specification
660 * @freq: audio sample rate in Hz
661 * @clock: rounded TMDS clock in kHz
662 */
663static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
664{
665 const struct hdmi_acr_n *recommended;
666 unsigned int i;
667
668 for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
669 if (clock == hdmi_rec_n_table[i].clock)
670 break;
671 }
672 recommended = hdmi_rec_n_table + i;
673
674 switch (freq) {
675 case 32000:
676 return recommended->n[0];
677 case 44100:
678 return recommended->n[1];
679 case 48000:
680 return recommended->n[2];
681 case 88200:
682 return recommended->n[1] * 2;
683 case 96000:
684 return recommended->n[2] * 2;
685 case 176400:
686 return recommended->n[1] * 4;
687 case 192000:
688 return recommended->n[2] * 4;
689 default:
690 return (128 * freq) / 1000;
691 }
692}
693
694static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
695{
696 switch (clock) {
697 case 25175:
698 return 25174825; /* 25.2/1.001 MHz */
699 case 74176:
700 return 74175824; /* 74.25/1.001 MHz */
701 case 148352:
702 return 148351648; /* 148.5/1.001 MHz */
703 case 296703:
704 return 296703297; /* 297/1.001 MHz */
705 default:
706 return clock * 1000;
707 }
708}
709
710static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
711 unsigned int tmds_clock, unsigned int n)
712{
713 return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
714 128 * audio_sample_rate);
715}
716
717static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
718 unsigned int cts)
719{
720 unsigned char val[NCTS_BYTES];
721 int i;
722
723 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
724 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
725 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
726 memset(val, 0, sizeof(val));
727
728 val[0] = (cts >> 24) & 0xff;
729 val[1] = (cts >> 16) & 0xff;
730 val[2] = (cts >> 8) & 0xff;
731 val[3] = cts & 0xff;
732
733 val[4] = (n >> 16) & 0xff;
734 val[5] = (n >> 8) & 0xff;
735 val[6] = n & 0xff;
736
737 for (i = 0; i < NCTS_BYTES; i++)
738 mtk_hdmi_write(hdmi, GRL_NCTS, val[i]);
739}
740
741static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
742 unsigned int sample_rate,
743 unsigned int clock)
744{
745 unsigned int n, cts;
746
747 n = hdmi_recommended_n(sample_rate, clock);
748 cts = hdmi_expected_cts(sample_rate, clock, n);
749
750 dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
751 __func__, sample_rate, clock, n, cts);
752
753 mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64,
754 AUDIO_I2S_NCTS_SEL);
755 do_hdmi_hw_aud_set_ncts(hdmi, n, cts);
756}
757
758static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type)
759{
760 switch (channel_type) {
761 case HDMI_AUD_CHAN_TYPE_1_0:
762 case HDMI_AUD_CHAN_TYPE_1_1:
763 case HDMI_AUD_CHAN_TYPE_2_0:
764 return 2;
765 case HDMI_AUD_CHAN_TYPE_2_1:
766 case HDMI_AUD_CHAN_TYPE_3_0:
767 return 3;
768 case HDMI_AUD_CHAN_TYPE_3_1:
769 case HDMI_AUD_CHAN_TYPE_4_0:
770 case HDMI_AUD_CHAN_TYPE_3_0_LRS:
771 return 4;
772 case HDMI_AUD_CHAN_TYPE_4_1:
773 case HDMI_AUD_CHAN_TYPE_5_0:
774 case HDMI_AUD_CHAN_TYPE_3_1_LRS:
775 case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
776 return 5;
777 case HDMI_AUD_CHAN_TYPE_5_1:
778 case HDMI_AUD_CHAN_TYPE_6_0:
779 case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
780 case HDMI_AUD_CHAN_TYPE_6_0_CS:
781 case HDMI_AUD_CHAN_TYPE_6_0_CH:
782 case HDMI_AUD_CHAN_TYPE_6_0_OH:
783 case HDMI_AUD_CHAN_TYPE_6_0_CHR:
784 return 6;
785 case HDMI_AUD_CHAN_TYPE_6_1:
786 case HDMI_AUD_CHAN_TYPE_6_1_CS:
787 case HDMI_AUD_CHAN_TYPE_6_1_CH:
788 case HDMI_AUD_CHAN_TYPE_6_1_OH:
789 case HDMI_AUD_CHAN_TYPE_6_1_CHR:
790 case HDMI_AUD_CHAN_TYPE_7_0:
791 case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
792 case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
793 case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
794 case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
795 case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
796 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
797 case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
798 case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
799 case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
800 case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
801 case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
802 case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
803 case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
804 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
805 case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
806 return 7;
807 case HDMI_AUD_CHAN_TYPE_7_1:
808 case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
809 case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
810 case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
811 case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
812 case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
813 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
814 case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
815 case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
816 case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
817 case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
818 case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
819 case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
820 case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
821 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
822 return 8;
823 default:
824 return 2;
825 }
826}
827
828static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock)
829{
830 unsigned long rate;
831 int ret;
832
833 /* The DPI driver already should have set TVDPLL to the correct rate */
834 ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock);
835 if (ret) {
836 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock,
837 ret);
838 return ret;
839 }
840
841 rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
842
843 if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000))
844 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock,
845 rate);
846 else
847 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate);
848
849 mtk_hdmi_hw_config_sys(hdmi);
850 mtk_hdmi_hw_set_deep_color_mode(hdmi);
851 return 0;
852}
853
854static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi,
855 struct drm_display_mode *mode)
856{
857 mtk_hdmi_hw_reset(hdmi);
858 mtk_hdmi_hw_enable_notice(hdmi, true);
859 mtk_hdmi_hw_write_int_mask(hdmi, 0xff);
860 mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode);
861 mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true);
862
863 mtk_hdmi_hw_msic_setting(hdmi, mode);
864}
865
866static int mtk_hdmi_aud_enable_packet(struct mtk_hdmi *hdmi, bool enable)
867{
868 mtk_hdmi_hw_send_aud_packet(hdmi, enable);
869 return 0;
870}
871
872static int mtk_hdmi_aud_on_off_hw_ncts(struct mtk_hdmi *hdmi, bool on)
873{
874 mtk_hdmi_hw_ncts_enable(hdmi, on);
875 return 0;
876}
877
878static int mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
879{
880 enum hdmi_aud_channel_type chan_type;
881 u8 chan_count;
882 bool dst;
883
884 mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC);
885 mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT);
886
887 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF &&
888 hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) {
889 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
890 } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) {
891 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT;
892 }
893
894 mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt);
895 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
896
897 dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) &&
898 (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST));
899 mtk_hdmi_hw_audio_config(hdmi, dst);
900
901 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF)
902 chan_type = HDMI_AUD_CHAN_TYPE_2_0;
903 else
904 chan_type = hdmi->aud_param.aud_input_chan_type;
905 chan_count = mtk_hdmi_aud_get_chnl_count(chan_type);
906 mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count);
907 mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type);
908
909 return 0;
910}
911
912static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi,
913 struct drm_display_mode *display_mode)
914{
915 unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate;
916
917 mtk_hdmi_aud_on_off_hw_ncts(hdmi, false);
918 mtk_hdmi_hw_aud_src_disable(hdmi);
919 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV);
920
921 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) {
922 switch (sample_rate) {
923 case 32000:
924 case 44100:
925 case 48000:
926 case 88200:
927 case 96000:
928 break;
929 default:
930 return -EINVAL;
931 }
932 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk);
933 } else {
934 switch (sample_rate) {
935 case 32000:
936 case 44100:
937 case 48000:
938 break;
939 default:
940 return -EINVAL;
941 }
942 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS);
943 }
944
945 mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock);
946
947 mtk_hdmi_hw_aud_src_reenable(hdmi);
948 return 0;
949}
950
951static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
952 struct drm_display_mode *display_mode)
953{
954 mtk_hdmi_hw_aud_mute(hdmi);
955 mtk_hdmi_aud_enable_packet(hdmi, false);
956
957 mtk_hdmi_aud_set_input(hdmi);
958 mtk_hdmi_aud_set_src(hdmi, display_mode);
959 mtk_hdmi_hw_aud_set_channel_status(hdmi,
960 hdmi->aud_param.codec_params.iec.status);
961
962 usleep_range(50, 100);
963
964 mtk_hdmi_aud_on_off_hw_ncts(hdmi, true);
965 mtk_hdmi_aud_enable_packet(hdmi, true);
966 mtk_hdmi_hw_aud_unmute(hdmi);
967 return 0;
968}
969
970static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
971 struct drm_display_mode *mode)
972{
973 struct hdmi_avi_infoframe frame;
974 u8 buffer[17];
975 ssize_t err;
976
977 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
978 if (err < 0) {
979 dev_err(hdmi->dev,
980 "Failed to get AVI infoframe from mode: %zd\n", err);
981 return err;
982 }
983
984 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
985 if (err < 0) {
986 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err);
987 return err;
988 }
989
990 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
991 return 0;
992}
993
994static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi,
995 const char *vendor,
996 const char *product)
997{
998 struct hdmi_spd_infoframe frame;
999 u8 buffer[29];
1000 ssize_t err;
1001
1002 err = hdmi_spd_infoframe_init(&frame, vendor, product);
1003 if (err < 0) {
1004 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
1005 err);
1006 return err;
1007 }
1008
1009 err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer));
1010 if (err < 0) {
1011 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err);
1012 return err;
1013 }
1014
1015 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1016 return 0;
1017}
1018
1019static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi)
1020{
1021 struct hdmi_audio_infoframe frame;
1022 u8 buffer[14];
1023 ssize_t err;
1024
1025 err = hdmi_audio_infoframe_init(&frame);
1026 if (err < 0) {
1027 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n",
1028 err);
1029 return err;
1030 }
1031
1032 frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
1033 frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
1034 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
1035 frame.channels = mtk_hdmi_aud_get_chnl_count(
1036 hdmi->aud_param.aud_input_chan_type);
1037
1038 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
1039 if (err < 0) {
1040 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n",
1041 err);
1042 return err;
1043 }
1044
1045 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1046 return 0;
1047}
1048
1049static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
1050 struct drm_display_mode *mode)
1051{
1052 struct hdmi_vendor_infoframe frame;
1053 u8 buffer[10];
1054 ssize_t err;
1055
1056 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode);
1057 if (err) {
1058 dev_err(hdmi->dev,
1059 "Failed to get vendor infoframe from mode: %zd\n", err);
1060 return err;
1061 }
1062
1063 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1064 if (err) {
1065 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1066 err);
1067 return err;
1068 }
1069
1070 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1071 return 0;
1072}
1073
1074static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
1075{
1076 struct hdmi_audio_param *aud_param = &hdmi->aud_param;
1077
1078 hdmi->csp = HDMI_COLORSPACE_RGB;
1079 aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1080 aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1081 aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
1082 aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1083 aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
1084 aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1085
1086 return 0;
1087}
1088
1089void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
1090{
1091 mtk_hdmi_aud_enable_packet(hdmi, true);
1092 hdmi->audio_enable = true;
1093}
1094
1095void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
1096{
1097 mtk_hdmi_aud_enable_packet(hdmi, false);
1098 hdmi->audio_enable = false;
1099}
1100
1101int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi,
1102 struct hdmi_audio_param *param)
1103{
1104 if (!hdmi->audio_enable) {
1105 dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
1106 return -EINVAL;
1107 }
1108 dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
1109 param->aud_codec, param->aud_input_type,
1110 param->aud_input_chan_type, param->codec_params.sample_rate);
1111 memcpy(&hdmi->aud_param, param, sizeof(*param));
1112 return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
1113}
1114
1115static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
1116 struct drm_display_mode *mode)
1117{
1118 int ret;
1119
1120 mtk_hdmi_hw_vid_black(hdmi, true);
1121 mtk_hdmi_hw_aud_mute(hdmi);
1122 mtk_hdmi_hw_send_av_mute(hdmi);
1123 phy_power_off(hdmi->phy);
1124
1125 ret = mtk_hdmi_video_change_vpll(hdmi,
1126 mode->clock * 1000);
1127 if (ret) {
1128 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret);
1129 return ret;
1130 }
1131 mtk_hdmi_video_set_display_mode(hdmi, mode);
1132
1133 phy_power_on(hdmi->phy);
1134 mtk_hdmi_aud_output_config(hdmi, mode);
1135
1136 mtk_hdmi_setup_audio_infoframe(hdmi);
1137 mtk_hdmi_setup_avi_infoframe(hdmi, mode);
1138 mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
1139 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
1140 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
1141
1142 mtk_hdmi_hw_vid_black(hdmi, false);
1143 mtk_hdmi_hw_aud_unmute(hdmi);
1144 mtk_hdmi_hw_send_av_unmute(hdmi);
1145
1146 return 0;
1147}
1148
1149static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
1150 [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel",
1151 [MTK_HDMI_CLK_HDMI_PLL] = "pll",
1152 [MTK_HDMI_CLK_AUD_BCLK] = "bclk",
1153 [MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
1154};
1155
1156static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi,
1157 struct device_node *np)
1158{
1159 int i;
1160
1161 for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) {
1162 hdmi->clk[i] = of_clk_get_by_name(np,
1163 mtk_hdmi_clk_names[i]);
1164 if (IS_ERR(hdmi->clk[i]))
1165 return PTR_ERR(hdmi->clk[i]);
1166 }
1167 return 0;
1168}
1169
1170static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
1171{
1172 int ret;
1173
1174 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1175 if (ret)
1176 return ret;
1177
1178 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1179 if (ret)
1180 goto err;
1181
1182 return 0;
1183err:
1184 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1185 return ret;
1186}
1187
1188static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
1189{
1190 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1191 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1192}
1193
1194static enum drm_connector_status hdmi_conn_detect(struct drm_connector *conn,
1195 bool force)
1196{
1197 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1198
1199 return mtk_cec_hpd_high(hdmi->cec_dev) ?
1200 connector_status_connected : connector_status_disconnected;
1201}
1202
1203static void hdmi_conn_destroy(struct drm_connector *conn)
1204{
1205 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1206
1207 mtk_cec_set_hpd_event(hdmi->cec_dev, NULL, NULL);
1208
1209 drm_connector_cleanup(conn);
1210}
1211
1212static int mtk_hdmi_conn_get_modes(struct drm_connector *conn)
1213{
1214 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1215 struct edid *edid;
1216 int ret;
1217
1218 if (!hdmi->ddc_adpt)
1219 return -ENODEV;
1220
1221 edid = drm_get_edid(conn, hdmi->ddc_adpt);
1222 if (!edid)
1223 return -ENODEV;
1224
1225 hdmi->dvi_mode = !drm_detect_monitor_audio(edid);
1226
1227 drm_mode_connector_update_edid_property(conn, edid);
1228
1229 ret = drm_add_edid_modes(conn, edid);
1230 drm_edid_to_eld(conn, edid);
1231 kfree(edid);
1232 return ret;
1233}
1234
1235static int mtk_hdmi_conn_mode_valid(struct drm_connector *conn,
1236 struct drm_display_mode *mode)
1237{
1238 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1239
1240 dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1241 mode->hdisplay, mode->vdisplay, mode->vrefresh,
1242 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000);
1243
1244 if (hdmi->bridge.next) {
1245 struct drm_display_mode adjusted_mode;
1246
1247 drm_mode_copy(&adjusted_mode, mode);
1248 if (!drm_bridge_mode_fixup(hdmi->bridge.next, mode,
1249 &adjusted_mode))
1250 return MODE_BAD;
1251 }
1252
1253 if (mode->clock < 27000)
1254 return MODE_CLOCK_LOW;
1255 if (mode->clock > 297000)
1256 return MODE_CLOCK_HIGH;
1257
1258 return drm_mode_validate_size(mode, 0x1fff, 0x1fff);
1259}
1260
1261static struct drm_encoder *mtk_hdmi_conn_best_enc(struct drm_connector *conn)
1262{
1263 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1264
1265 return hdmi->bridge.encoder;
1266}
1267
1268static const struct drm_connector_funcs mtk_hdmi_connector_funcs = {
1269 .dpms = drm_atomic_helper_connector_dpms,
1270 .detect = hdmi_conn_detect,
1271 .fill_modes = drm_helper_probe_single_connector_modes,
1272 .destroy = hdmi_conn_destroy,
1273 .reset = drm_atomic_helper_connector_reset,
1274 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1275 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1276};
1277
1278static const struct drm_connector_helper_funcs
1279 mtk_hdmi_connector_helper_funcs = {
1280 .get_modes = mtk_hdmi_conn_get_modes,
1281 .mode_valid = mtk_hdmi_conn_mode_valid,
1282 .best_encoder = mtk_hdmi_conn_best_enc,
1283};
1284
1285static void mtk_hdmi_hpd_event(bool hpd, struct device *dev)
1286{
1287 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1288
1289 if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev)
1290 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);
1291}
1292
1293/*
1294 * Bridge callbacks
1295 */
1296
1297static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge)
1298{
1299 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1300 int ret;
1301
1302 ret = drm_connector_init(bridge->encoder->dev, &hdmi->conn,
1303 &mtk_hdmi_connector_funcs,
1304 DRM_MODE_CONNECTOR_HDMIA);
1305 if (ret) {
1306 dev_err(hdmi->dev, "Failed to initialize connector: %d\n", ret);
1307 return ret;
1308 }
1309 drm_connector_helper_add(&hdmi->conn, &mtk_hdmi_connector_helper_funcs);
1310
1311 hdmi->conn.polled = DRM_CONNECTOR_POLL_HPD;
1312 hdmi->conn.interlace_allowed = true;
1313 hdmi->conn.doublescan_allowed = false;
1314
1315 ret = drm_mode_connector_attach_encoder(&hdmi->conn,
1316 bridge->encoder);
1317 if (ret) {
1318 dev_err(hdmi->dev,
1319 "Failed to attach connector to encoder: %d\n", ret);
1320 return ret;
1321 }
1322
1323 if (bridge->next) {
1324 bridge->next->encoder = bridge->encoder;
1325 ret = drm_bridge_attach(bridge->encoder->dev, bridge->next);
1326 if (ret) {
1327 dev_err(hdmi->dev,
1328 "Failed to attach external bridge: %d\n", ret);
1329 return ret;
1330 }
1331 }
1332
1333 mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
1334
1335 return 0;
1336}
1337
1338static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1339 const struct drm_display_mode *mode,
1340 struct drm_display_mode *adjusted_mode)
1341{
1342 return true;
1343}
1344
1345static void mtk_hdmi_bridge_disable(struct drm_bridge *bridge)
1346{
1347 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1348
1349 if (!hdmi->enabled)
1350 return;
1351
1352 phy_power_off(hdmi->phy);
1353 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1354 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1355
1356 hdmi->enabled = false;
1357}
1358
1359static void mtk_hdmi_bridge_post_disable(struct drm_bridge *bridge)
1360{
1361 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1362
1363 if (!hdmi->powered)
1364 return;
1365
1366 mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1367 mtk_hdmi_hw_make_reg_writable(hdmi, false);
1368
1369 hdmi->powered = false;
1370}
1371
1372static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1373 struct drm_display_mode *mode,
1374 struct drm_display_mode *adjusted_mode)
1375{
1376 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1377
1378 dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
1379 adjusted_mode->name, adjusted_mode->hdisplay);
1380 dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
1381 adjusted_mode->hsync_start, adjusted_mode->hsync_end,
1382 adjusted_mode->htotal);
1383 dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
1384 adjusted_mode->hskew, adjusted_mode->vdisplay);
1385 dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
1386 adjusted_mode->vsync_start, adjusted_mode->vsync_end,
1387 adjusted_mode->vtotal);
1388 dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
1389 adjusted_mode->vscan, adjusted_mode->flags);
1390
1391 drm_mode_copy(&hdmi->mode, adjusted_mode);
1392}
1393
1394static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
1395{
1396 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1397
1398 mtk_hdmi_hw_make_reg_writable(hdmi, true);
1399 mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1400
1401 hdmi->powered = true;
1402}
1403
1404static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge)
1405{
1406 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1407
1408 mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode);
1409 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1410 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1411 phy_power_on(hdmi->phy);
1412
1413 hdmi->enabled = true;
1414}
1415
1416static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
1417 .attach = mtk_hdmi_bridge_attach,
1418 .mode_fixup = mtk_hdmi_bridge_mode_fixup,
1419 .disable = mtk_hdmi_bridge_disable,
1420 .post_disable = mtk_hdmi_bridge_post_disable,
1421 .mode_set = mtk_hdmi_bridge_mode_set,
1422 .pre_enable = mtk_hdmi_bridge_pre_enable,
1423 .enable = mtk_hdmi_bridge_enable,
1424};
1425
1426static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
1427 struct platform_device *pdev)
1428{
1429 struct device *dev = &pdev->dev;
1430 struct device_node *np = dev->of_node;
1431 struct device_node *cec_np, *port, *ep, *remote, *i2c_np;
1432 struct platform_device *cec_pdev;
1433 struct regmap *regmap;
1434 struct resource *mem;
1435 int ret;
1436
1437 ret = mtk_hdmi_get_all_clk(hdmi, np);
1438 if (ret) {
1439 dev_err(dev, "Failed to get clocks: %d\n", ret);
1440 return ret;
1441 }
1442
1443 /* The CEC module handles HDMI hotplug detection */
1444 cec_np = of_find_compatible_node(np->parent, NULL,
1445 "mediatek,mt8173-cec");
1446 if (!cec_np) {
1447 dev_err(dev, "Failed to find CEC node\n");
1448 return -EINVAL;
1449 }
1450
1451 cec_pdev = of_find_device_by_node(cec_np);
1452 if (!cec_pdev) {
1453 dev_err(hdmi->dev, "Waiting for CEC device %s\n",
1454 cec_np->full_name);
1455 return -EPROBE_DEFER;
1456 }
1457 hdmi->cec_dev = &cec_pdev->dev;
1458
1459 /*
1460 * The mediatek,syscon-hdmi property contains a phandle link to the
1461 * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
1462 * registers it contains.
1463 */
1464 regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
1465 ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1,
1466 &hdmi->sys_offset);
1467 if (IS_ERR(regmap))
1468 ret = PTR_ERR(regmap);
1469 if (ret) {
1470 ret = PTR_ERR(regmap);
1471 dev_err(dev,
1472 "Failed to get system configuration registers: %d\n",
1473 ret);
1474 return ret;
1475 }
1476 hdmi->sys_regmap = regmap;
1477
1478 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1479 hdmi->regs = devm_ioremap_resource(dev, mem);
1480 if (IS_ERR(hdmi->regs))
1481 return PTR_ERR(hdmi->regs);
1482
1483 port = of_graph_get_port_by_id(np, 1);
1484 if (!port) {
1485 dev_err(dev, "Missing output port node\n");
1486 return -EINVAL;
1487 }
1488
1489 ep = of_get_child_by_name(port, "endpoint");
1490 if (!ep) {
1491 dev_err(dev, "Missing endpoint node in port %s\n",
1492 port->full_name);
1493 of_node_put(port);
1494 return -EINVAL;
1495 }
1496 of_node_put(port);
1497
1498 remote = of_graph_get_remote_port_parent(ep);
1499 if (!remote) {
1500 dev_err(dev, "Missing connector/bridge node for endpoint %s\n",
1501 ep->full_name);
1502 of_node_put(ep);
1503 return -EINVAL;
1504 }
1505 of_node_put(ep);
1506
1507 if (!of_device_is_compatible(remote, "hdmi-connector")) {
1508 hdmi->bridge.next = of_drm_find_bridge(remote);
1509 if (!hdmi->bridge.next) {
1510 dev_err(dev, "Waiting for external bridge\n");
1511 of_node_put(remote);
1512 return -EPROBE_DEFER;
1513 }
1514 }
1515
1516 i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
1517 if (!i2c_np) {
1518 dev_err(dev, "Failed to find ddc-i2c-bus node in %s\n",
1519 remote->full_name);
1520 of_node_put(remote);
1521 return -EINVAL;
1522 }
1523 of_node_put(remote);
1524
1525 hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
1526 if (!hdmi->ddc_adpt) {
1527 dev_err(dev, "Failed to get ddc i2c adapter by node\n");
1528 return -EINVAL;
1529 }
1530
1531 return 0;
1532}
1533
1534/*
1535 * HDMI audio codec callbacks
1536 */
1537
1538static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
1539 struct hdmi_codec_daifmt *daifmt,
1540 struct hdmi_codec_params *params)
1541{
1542 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1543 struct hdmi_audio_param hdmi_params;
1544 unsigned int chan = params->cea.channels;
1545
1546 dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1547 params->sample_rate, params->sample_width, chan);
1548
1549 if (!hdmi->bridge.encoder)
1550 return -ENODEV;
1551
1552 switch (chan) {
1553 case 2:
1554 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1555 break;
1556 case 4:
1557 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
1558 break;
1559 case 6:
1560 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
1561 break;
1562 case 8:
1563 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
1564 break;
1565 default:
1566 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
1567 return -EINVAL;
1568 }
1569
1570 switch (params->sample_rate) {
1571 case 32000:
1572 case 44100:
1573 case 48000:
1574 case 88200:
1575 case 96000:
1576 case 176400:
1577 case 192000:
1578 break;
1579 default:
1580 dev_err(hdmi->dev, "rate[%d] not supported!\n",
1581 params->sample_rate);
1582 return -EINVAL;
1583 }
1584
1585 switch (daifmt->fmt) {
1586 case HDMI_I2S:
1587 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1588 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1589 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
1590 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1591 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
1592 break;
1593 default:
1594 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
1595 daifmt->fmt);
1596 return -EINVAL;
1597 }
1598
1599 memcpy(&hdmi_params.codec_params, params,
1600 sizeof(hdmi_params.codec_params));
1601
1602 mtk_hdmi_audio_set_param(hdmi, &hdmi_params);
1603
1604 return 0;
1605}
1606
1607static int mtk_hdmi_audio_startup(struct device *dev, void *data)
1608{
1609 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1610
1611 dev_dbg(dev, "%s\n", __func__);
1612
1613 mtk_hdmi_audio_enable(hdmi);
1614
1615 return 0;
1616}
1617
1618static void mtk_hdmi_audio_shutdown(struct device *dev, void *data)
1619{
1620 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1621
1622 dev_dbg(dev, "%s\n", __func__);
1623
1624 mtk_hdmi_audio_disable(hdmi);
1625}
1626
1627int mtk_hdmi_audio_digital_mute(struct device *dev, void *data, bool enable)
1628{
1629 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1630
1631 dev_dbg(dev, "%s(%d)\n", __func__, enable);
1632
1633 if (enable)
1634 mtk_hdmi_hw_aud_mute(hdmi);
1635 else
1636 mtk_hdmi_hw_aud_unmute(hdmi);
1637
1638 return 0;
1639}
1640
1641static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1642{
1643 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1644
1645 dev_dbg(dev, "%s\n", __func__);
1646
1647 memcpy(buf, hdmi->conn.eld, min(sizeof(hdmi->conn.eld), len));
1648
1649 return 0;
1650}
1651
1652static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
1653 .hw_params = mtk_hdmi_audio_hw_params,
1654 .audio_startup = mtk_hdmi_audio_startup,
1655 .audio_shutdown = mtk_hdmi_audio_shutdown,
1656 .digital_mute = mtk_hdmi_audio_digital_mute,
1657 .get_eld = mtk_hdmi_audio_get_eld,
1658};
1659
1660static void mtk_hdmi_register_audio_driver(struct device *dev)
1661{
1662 struct hdmi_codec_pdata codec_data = {
1663 .ops = &mtk_hdmi_audio_codec_ops,
1664 .max_i2s_channels = 2,
1665 .i2s = 1,
1666 };
1667 struct platform_device *pdev;
1668
1669 pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1670 PLATFORM_DEVID_AUTO, &codec_data,
1671 sizeof(codec_data));
1672 if (IS_ERR(pdev))
1673 return;
1674
1675 DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
1676}
1677
1678static int mtk_drm_hdmi_probe(struct platform_device *pdev)
1679{
1680 struct mtk_hdmi *hdmi;
1681 struct device *dev = &pdev->dev;
1682 int ret;
1683
1684 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1685 if (!hdmi)
1686 return -ENOMEM;
1687
1688 hdmi->dev = dev;
1689
1690 ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
1691 if (ret)
1692 return ret;
1693
1694 hdmi->phy = devm_phy_get(dev, "hdmi");
1695 if (IS_ERR(hdmi->phy)) {
1696 ret = PTR_ERR(hdmi->phy);
1697 dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
1698 return ret;
1699 }
1700
1701 platform_set_drvdata(pdev, hdmi);
1702
1703 ret = mtk_hdmi_output_init(hdmi);
1704 if (ret) {
1705 dev_err(dev, "Failed to initialize hdmi output\n");
1706 return ret;
1707 }
1708
1709 mtk_hdmi_register_audio_driver(dev);
1710
1711 hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
1712 hdmi->bridge.of_node = pdev->dev.of_node;
1713 ret = drm_bridge_add(&hdmi->bridge);
1714 if (ret) {
1715 dev_err(dev, "failed to add bridge, ret = %d\n", ret);
1716 return ret;
1717 }
1718
1719 ret = mtk_hdmi_clk_enable_audio(hdmi);
1720 if (ret) {
1721 dev_err(dev, "Failed to enable audio clocks: %d\n", ret);
1722 goto err_bridge_remove;
1723 }
1724
1725 dev_dbg(dev, "mediatek hdmi probe success\n");
1726 return 0;
1727
1728err_bridge_remove:
1729 drm_bridge_remove(&hdmi->bridge);
1730 return ret;
1731}
1732
1733static int mtk_drm_hdmi_remove(struct platform_device *pdev)
1734{
1735 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
1736
1737 drm_bridge_remove(&hdmi->bridge);
1738 mtk_hdmi_clk_disable_audio(hdmi);
1739 return 0;
1740}
1741
1742#ifdef CONFIG_PM_SLEEP
1743static int mtk_hdmi_suspend(struct device *dev)
1744{
1745 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1746
1747 mtk_hdmi_clk_disable_audio(hdmi);
1748 dev_dbg(dev, "hdmi suspend success!\n");
1749 return 0;
1750}
1751
1752static int mtk_hdmi_resume(struct device *dev)
1753{
1754 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1755 int ret = 0;
1756
1757 ret = mtk_hdmi_clk_enable_audio(hdmi);
1758 if (ret) {
1759 dev_err(dev, "hdmi resume failed!\n");
1760 return ret;
1761 }
1762
1763 dev_dbg(dev, "hdmi resume success!\n");
1764 return 0;
1765}
1766#endif
1767static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
1768 mtk_hdmi_suspend, mtk_hdmi_resume);
1769
1770static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
1771 { .compatible = "mediatek,mt8173-hdmi", },
1772 {}
1773};
1774
1775static struct platform_driver mtk_hdmi_driver = {
1776 .probe = mtk_drm_hdmi_probe,
1777 .remove = mtk_drm_hdmi_remove,
1778 .driver = {
1779 .name = "mediatek-drm-hdmi",
1780 .of_match_table = mtk_drm_hdmi_of_ids,
1781 .pm = &mtk_hdmi_pm_ops,
1782 },
1783};
1784
1785static struct platform_driver * const mtk_hdmi_drivers[] = {
1786 &mtk_hdmi_phy_driver,
1787 &mtk_hdmi_ddc_driver,
1788 &mtk_cec_driver,
1789 &mtk_hdmi_driver,
1790};
1791
1792static int __init mtk_hdmitx_init(void)
1793{
1794 int ret;
1795 int i;
1796
1797 for (i = 0; i < ARRAY_SIZE(mtk_hdmi_drivers); i++) {
1798 ret = platform_driver_register(mtk_hdmi_drivers[i]);
1799 if (ret < 0) {
1800 pr_err("Failed to register %s driver: %d\n",
1801 mtk_hdmi_drivers[i]->driver.name, ret);
1802 goto err;
1803 }
1804 }
1805
1806 return 0;
1807
1808err:
1809 while (--i >= 0)
1810 platform_driver_unregister(mtk_hdmi_drivers[i]);
1811
1812 return ret;
1813}
1814
1815static void __exit mtk_hdmitx_exit(void)
1816{
1817 int i;
1818
1819 for (i = ARRAY_SIZE(mtk_hdmi_drivers) - 1; i >= 0; i--)
1820 platform_driver_unregister(mtk_hdmi_drivers[i]);
1821}
1822
1823module_init(mtk_hdmitx_init);
1824module_exit(mtk_hdmitx_exit);
1825
1826MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
1827MODULE_DESCRIPTION("MediaTek HDMI Driver");
1828MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
new file mode 100644
index 000000000000..6371b3de1ff6
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Jie Qiu <jie.qiu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#ifndef _MTK_HDMI_CTRL_H
15#define _MTK_HDMI_CTRL_H
16
17struct platform_driver;
18
19extern struct platform_driver mtk_cec_driver;
20extern struct platform_driver mtk_hdmi_ddc_driver;
21extern struct platform_driver mtk_hdmi_phy_driver;
22
23#endif /* _MTK_HDMI_CTRL_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c b/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c
new file mode 100644
index 000000000000..33c9e1bdb114
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c
@@ -0,0 +1,358 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Jie Qiu <jie.qiu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/i2c.h>
17#include <linux/time.h>
18#include <linux/delay.h>
19#include <linux/errno.h>
20#include <linux/err.h>
21#include <linux/platform_device.h>
22#include <linux/clk.h>
23#include <linux/slab.h>
24#include <linux/io.h>
25#include <linux/iopoll.h>
26#include <linux/of_address.h>
27#include <linux/of_irq.h>
28#include <linux/of_platform.h>
29
30#define SIF1_CLOK (288)
31#define DDC_DDCMCTL0 (0x0)
32#define DDCM_ODRAIN BIT(31)
33#define DDCM_CLK_DIV_OFFSET (16)
34#define DDCM_CLK_DIV_MASK (0xfff << 16)
35#define DDCM_CS_STATUS BIT(4)
36#define DDCM_SCL_STATE BIT(3)
37#define DDCM_SDA_STATE BIT(2)
38#define DDCM_SM0EN BIT(1)
39#define DDCM_SCL_STRECH BIT(0)
40#define DDC_DDCMCTL1 (0x4)
41#define DDCM_ACK_OFFSET (16)
42#define DDCM_ACK_MASK (0xff << 16)
43#define DDCM_PGLEN_OFFSET (8)
44#define DDCM_PGLEN_MASK (0x7 << 8)
45#define DDCM_SIF_MODE_OFFSET (4)
46#define DDCM_SIF_MODE_MASK (0x7 << 4)
47#define DDCM_START (0x1)
48#define DDCM_WRITE_DATA (0x2)
49#define DDCM_STOP (0x3)
50#define DDCM_READ_DATA_NO_ACK (0x4)
51#define DDCM_READ_DATA_ACK (0x5)
52#define DDCM_TRI BIT(0)
53#define DDC_DDCMD0 (0x8)
54#define DDCM_DATA3 (0xff << 24)
55#define DDCM_DATA2 (0xff << 16)
56#define DDCM_DATA1 (0xff << 8)
57#define DDCM_DATA0 (0xff << 0)
58#define DDC_DDCMD1 (0xc)
59#define DDCM_DATA7 (0xff << 24)
60#define DDCM_DATA6 (0xff << 16)
61#define DDCM_DATA5 (0xff << 8)
62#define DDCM_DATA4 (0xff << 0)
63
64struct mtk_hdmi_ddc {
65 struct i2c_adapter adap;
66 struct clk *clk;
67 void __iomem *regs;
68};
69
70static inline void sif_set_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset,
71 unsigned int val)
72{
73 writel(readl(ddc->regs + offset) | val, ddc->regs + offset);
74}
75
76static inline void sif_clr_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset,
77 unsigned int val)
78{
79 writel(readl(ddc->regs + offset) & ~val, ddc->regs + offset);
80}
81
82static inline bool sif_bit_is_set(struct mtk_hdmi_ddc *ddc, unsigned int offset,
83 unsigned int val)
84{
85 return (readl(ddc->regs + offset) & val) == val;
86}
87
88static inline void sif_write_mask(struct mtk_hdmi_ddc *ddc, unsigned int offset,
89 unsigned int mask, unsigned int shift,
90 unsigned int val)
91{
92 unsigned int tmp;
93
94 tmp = readl(ddc->regs + offset);
95 tmp &= ~mask;
96 tmp |= (val << shift) & mask;
97 writel(tmp, ddc->regs + offset);
98}
99
100static inline unsigned int sif_read_mask(struct mtk_hdmi_ddc *ddc,
101 unsigned int offset, unsigned int mask,
102 unsigned int shift)
103{
104 return (readl(ddc->regs + offset) & mask) >> shift;
105}
106
107static void ddcm_trigger_mode(struct mtk_hdmi_ddc *ddc, int mode)
108{
109 u32 val;
110
111 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_SIF_MODE_MASK,
112 DDCM_SIF_MODE_OFFSET, mode);
113 sif_set_bit(ddc, DDC_DDCMCTL1, DDCM_TRI);
114 readl_poll_timeout(ddc->regs + DDC_DDCMCTL1, val,
115 (val & DDCM_TRI) != DDCM_TRI, 4, 20000);
116}
117
118static int mtk_hdmi_ddc_read_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg)
119{
120 struct device *dev = ddc->adap.dev.parent;
121 u32 remain_count, ack_count, ack_final, read_count, temp_count;
122 u32 index = 0;
123 u32 ack;
124 int i;
125
126 ddcm_trigger_mode(ddc, DDCM_START);
127 sif_write_mask(ddc, DDC_DDCMD0, 0xff, 0, (msg->addr << 1) | 0x01);
128 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,
129 0x00);
130 ddcm_trigger_mode(ddc, DDCM_WRITE_DATA);
131 ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);
132 dev_dbg(dev, "ack = 0x%x\n", ack);
133 if (ack != 0x01) {
134 dev_err(dev, "i2c ack err!\n");
135 return -ENXIO;
136 }
137
138 remain_count = msg->len;
139 ack_count = (msg->len - 1) / 8;
140 ack_final = 0;
141
142 while (remain_count > 0) {
143 if (ack_count > 0) {
144 read_count = 8;
145 ack_final = 0;
146 ack_count--;
147 } else {
148 read_count = remain_count;
149 ack_final = 1;
150 }
151
152 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK,
153 DDCM_PGLEN_OFFSET, read_count - 1);
154 ddcm_trigger_mode(ddc, (ack_final == 1) ?
155 DDCM_READ_DATA_NO_ACK :
156 DDCM_READ_DATA_ACK);
157
158 ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK,
159 DDCM_ACK_OFFSET);
160 temp_count = 0;
161 while (((ack & (1 << temp_count)) != 0) && (temp_count < 8))
162 temp_count++;
163 if (((ack_final == 1) && (temp_count != (read_count - 1))) ||
164 ((ack_final == 0) && (temp_count != read_count))) {
165 dev_err(dev, "Address NACK! ACK(0x%x)\n", ack);
166 break;
167 }
168
169 for (i = read_count; i >= 1; i--) {
170 int shift;
171 int offset;
172
173 if (i > 4) {
174 offset = DDC_DDCMD1;
175 shift = (i - 5) * 8;
176 } else {
177 offset = DDC_DDCMD0;
178 shift = (i - 1) * 8;
179 }
180
181 msg->buf[index + i - 1] = sif_read_mask(ddc, offset,
182 0xff << shift,
183 shift);
184 }
185
186 remain_count -= read_count;
187 index += read_count;
188 }
189
190 return 0;
191}
192
193static int mtk_hdmi_ddc_write_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg)
194{
195 struct device *dev = ddc->adap.dev.parent;
196 u32 ack;
197
198 ddcm_trigger_mode(ddc, DDCM_START);
199 sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA0, 0, msg->addr << 1);
200 sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA1, 8, msg->buf[0]);
201 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,
202 0x1);
203 ddcm_trigger_mode(ddc, DDCM_WRITE_DATA);
204
205 ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);
206 dev_dbg(dev, "ack = %d\n", ack);
207
208 if (ack != 0x03) {
209 dev_err(dev, "i2c ack err!\n");
210 return -EIO;
211 }
212
213 return 0;
214}
215
216static int mtk_hdmi_ddc_xfer(struct i2c_adapter *adapter,
217 struct i2c_msg *msgs, int num)
218{
219 struct mtk_hdmi_ddc *ddc = adapter->algo_data;
220 struct device *dev = adapter->dev.parent;
221 int ret;
222 int i;
223
224 if (!ddc) {
225 dev_err(dev, "invalid arguments\n");
226 return -EINVAL;
227 }
228
229 sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SCL_STRECH);
230 sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SM0EN);
231 sif_clr_bit(ddc, DDC_DDCMCTL0, DDCM_ODRAIN);
232
233 if (sif_bit_is_set(ddc, DDC_DDCMCTL1, DDCM_TRI)) {
234 dev_err(dev, "ddc line is busy!\n");
235 return -EBUSY;
236 }
237
238 sif_write_mask(ddc, DDC_DDCMCTL0, DDCM_CLK_DIV_MASK,
239 DDCM_CLK_DIV_OFFSET, SIF1_CLOK);
240
241 for (i = 0; i < num; i++) {
242 struct i2c_msg *msg = &msgs[i];
243
244 dev_dbg(dev, "i2c msg, adr:0x%x, flags:%d, len :0x%x\n",
245 msg->addr, msg->flags, msg->len);
246
247 if (msg->flags & I2C_M_RD)
248 ret = mtk_hdmi_ddc_read_msg(ddc, msg);
249 else
250 ret = mtk_hdmi_ddc_write_msg(ddc, msg);
251 if (ret < 0)
252 goto xfer_end;
253 }
254
255 ddcm_trigger_mode(ddc, DDCM_STOP);
256
257 return i;
258
259xfer_end:
260 ddcm_trigger_mode(ddc, DDCM_STOP);
261 dev_err(dev, "ddc failed!\n");
262 return ret;
263}
264
265static u32 mtk_hdmi_ddc_func(struct i2c_adapter *adapter)
266{
267 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
268}
269
270static const struct i2c_algorithm mtk_hdmi_ddc_algorithm = {
271 .master_xfer = mtk_hdmi_ddc_xfer,
272 .functionality = mtk_hdmi_ddc_func,
273};
274
275static int mtk_hdmi_ddc_probe(struct platform_device *pdev)
276{
277 struct device *dev = &pdev->dev;
278 struct mtk_hdmi_ddc *ddc;
279 struct resource *mem;
280 int ret;
281
282 ddc = devm_kzalloc(dev, sizeof(struct mtk_hdmi_ddc), GFP_KERNEL);
283 if (!ddc)
284 return -ENOMEM;
285
286 ddc->clk = devm_clk_get(dev, "ddc-i2c");
287 if (IS_ERR(ddc->clk)) {
288 dev_err(dev, "get ddc_clk failed: %p ,\n", ddc->clk);
289 return PTR_ERR(ddc->clk);
290 }
291
292 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
293 ddc->regs = devm_ioremap_resource(&pdev->dev, mem);
294 if (IS_ERR(ddc->regs))
295 return PTR_ERR(ddc->regs);
296
297 ret = clk_prepare_enable(ddc->clk);
298 if (ret) {
299 dev_err(dev, "enable ddc clk failed!\n");
300 return ret;
301 }
302
303 strlcpy(ddc->adap.name, "mediatek-hdmi-ddc", sizeof(ddc->adap.name));
304 ddc->adap.owner = THIS_MODULE;
305 ddc->adap.class = I2C_CLASS_DDC;
306 ddc->adap.algo = &mtk_hdmi_ddc_algorithm;
307 ddc->adap.retries = 3;
308 ddc->adap.dev.of_node = dev->of_node;
309 ddc->adap.algo_data = ddc;
310 ddc->adap.dev.parent = &pdev->dev;
311
312 ret = i2c_add_adapter(&ddc->adap);
313 if (ret < 0) {
314 dev_err(dev, "failed to add bus to i2c core\n");
315 goto err_clk_disable;
316 }
317
318 platform_set_drvdata(pdev, ddc);
319
320 dev_dbg(dev, "ddc->adap: %p\n", &ddc->adap);
321 dev_dbg(dev, "ddc->clk: %p\n", ddc->clk);
322 dev_dbg(dev, "physical adr: %pa, end: %pa\n", &mem->start,
323 &mem->end);
324
325 return 0;
326
327err_clk_disable:
328 clk_disable_unprepare(ddc->clk);
329 return ret;
330}
331
332static int mtk_hdmi_ddc_remove(struct platform_device *pdev)
333{
334 struct mtk_hdmi_ddc *ddc = platform_get_drvdata(pdev);
335
336 i2c_del_adapter(&ddc->adap);
337 clk_disable_unprepare(ddc->clk);
338
339 return 0;
340}
341
342static const struct of_device_id mtk_hdmi_ddc_match[] = {
343 { .compatible = "mediatek,mt8173-hdmi-ddc", },
344 {},
345};
346
347struct platform_driver mtk_hdmi_ddc_driver = {
348 .probe = mtk_hdmi_ddc_probe,
349 .remove = mtk_hdmi_ddc_remove,
350 .driver = {
351 .name = "mediatek-hdmi-ddc",
352 .of_match_table = mtk_hdmi_ddc_match,
353 },
354};
355
356MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
357MODULE_DESCRIPTION("MediaTek HDMI DDC Driver");
358MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
new file mode 100644
index 000000000000..a5cb07d12c9c
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
@@ -0,0 +1,238 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Jie Qiu <jie.qiu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#ifndef _MTK_HDMI_REGS_H
15#define _MTK_HDMI_REGS_H
16
17#define GRL_INT_MASK 0x18
18#define GRL_IFM_PORT 0x188
19#define GRL_CH_SWAP 0x198
20#define LR_SWAP BIT(0)
21#define LFE_CC_SWAP BIT(1)
22#define LSRS_SWAP BIT(2)
23#define RLS_RRS_SWAP BIT(3)
24#define LR_STATUS_SWAP BIT(4)
25#define GRL_I2S_C_STA0 0x140
26#define GRL_I2S_C_STA1 0x144
27#define GRL_I2S_C_STA2 0x148
28#define GRL_I2S_C_STA3 0x14C
29#define GRL_I2S_C_STA4 0x150
30#define GRL_I2S_UV 0x154
31#define I2S_UV_V BIT(0)
32#define I2S_UV_U BIT(1)
33#define I2S_UV_CH_EN_MASK 0x3c
34#define I2S_UV_CH_EN(x) BIT((x) + 2)
35#define I2S_UV_TMDS_DEBUG BIT(6)
36#define I2S_UV_NORMAL_INFO_INV BIT(7)
37#define GRL_ACP_ISRC_CTRL 0x158
38#define VS_EN BIT(0)
39#define ACP_EN BIT(1)
40#define ISRC1_EN BIT(2)
41#define ISRC2_EN BIT(3)
42#define GAMUT_EN BIT(4)
43#define GRL_CTS_CTRL 0x160
44#define CTS_CTRL_SOFT BIT(0)
45#define GRL_INT 0x14
46#define INT_MDI BIT(0)
47#define INT_HDCP BIT(1)
48#define INT_FIFO_O BIT(2)
49#define INT_FIFO_U BIT(3)
50#define INT_IFM_ERR BIT(4)
51#define INT_INF_DONE BIT(5)
52#define INT_NCTS_DONE BIT(6)
53#define INT_CTRL_PKT_DONE BIT(7)
54#define GRL_INT_MASK 0x18
55#define GRL_CTRL 0x1C
56#define CTRL_GEN_EN BIT(2)
57#define CTRL_SPD_EN BIT(3)
58#define CTRL_MPEG_EN BIT(4)
59#define CTRL_AUDIO_EN BIT(5)
60#define CTRL_AVI_EN BIT(6)
61#define CTRL_AVMUTE BIT(7)
62#define GRL_STATUS 0x20
63#define STATUS_HTPLG BIT(0)
64#define STATUS_PORD BIT(1)
65#define GRL_DIVN 0x170
66#define NCTS_WRI_ANYTIME BIT(6)
67#define GRL_AUDIO_CFG 0x17C
68#define AUDIO_ZERO BIT(0)
69#define HIGH_BIT_RATE BIT(1)
70#define SACD_DST BIT(2)
71#define DST_NORMAL_DOUBLE BIT(3)
72#define DSD_INV BIT(4)
73#define LR_INV BIT(5)
74#define LR_MIX BIT(6)
75#define DSD_SEL BIT(7)
76#define GRL_NCTS 0x184
77#define GRL_CH_SW0 0x18C
78#define GRL_CH_SW1 0x190
79#define GRL_CH_SW2 0x194
80#define CH_SWITCH(from, to) ((from) << ((to) * 3))
81#define GRL_INFOFRM_VER 0x19C
82#define GRL_INFOFRM_TYPE 0x1A0
83#define GRL_INFOFRM_LNG 0x1A4
84#define GRL_MIX_CTRL 0x1B4
85#define MIX_CTRL_SRC_EN BIT(0)
86#define BYPASS_VOLUME BIT(1)
87#define MIX_CTRL_FLAT BIT(7)
88#define GRL_AOUT_CFG 0x1C4
89#define AOUT_BNUM_SEL_MASK 0x03
90#define AOUT_24BIT 0x00
91#define AOUT_20BIT 0x02
92#define AOUT_16BIT 0x03
93#define AOUT_FIFO_ADAP_CTRL BIT(6)
94#define AOUT_BURST_PREAMBLE_EN BIT(7)
95#define HIGH_BIT_RATE_PACKET_ALIGN (AOUT_BURST_PREAMBLE_EN | \
96 AOUT_FIFO_ADAP_CTRL)
97#define GRL_SHIFT_L1 0x1C0
98#define GRL_SHIFT_R2 0x1B0
99#define AUDIO_PACKET_OFF BIT(6)
100#define GRL_CFG0 0x24
101#define CFG0_I2S_MODE_MASK 0x3
102#define CFG0_I2S_MODE_RTJ 0x1
103#define CFG0_I2S_MODE_LTJ 0x0
104#define CFG0_I2S_MODE_I2S 0x2
105#define CFG0_W_LENGTH_MASK 0x30
106#define CFG0_W_LENGTH_24BIT 0x00
107#define CFG0_W_LENGTH_16BIT 0x10
108#define GRL_CFG1 0x28
109#define CFG1_EDG_SEL BIT(0)
110#define CFG1_SPDIF BIT(1)
111#define CFG1_DVI BIT(2)
112#define CFG1_HDCP_DEBUG BIT(3)
113#define GRL_CFG2 0x2c
114#define CFG2_MHL_DE_SEL BIT(3)
115#define CFG2_MHL_FAKE_DE_SEL BIT(4)
116#define CFG2_MHL_DATA_REMAP BIT(5)
117#define CFG2_NOTICE_EN BIT(6)
118#define CFG2_ACLK_INV BIT(7)
119#define GRL_CFG3 0x30
120#define CFG3_AES_KEY_INDEX_MASK 0x3f
121#define CFG3_CONTROL_PACKET_DELAY BIT(6)
122#define CFG3_KSV_LOAD_START BIT(7)
123#define GRL_CFG4 0x34
124#define CFG4_AES_KEY_LOAD BIT(4)
125#define CFG4_AV_UNMUTE_EN BIT(5)
126#define CFG4_AV_UNMUTE_SET BIT(6)
127#define CFG4_MHL_MODE BIT(7)
128#define GRL_CFG5 0x38
129#define CFG5_CD_RATIO_MASK 0x8F
130#define CFG5_FS128 (0x1 << 4)
131#define CFG5_FS256 (0x2 << 4)
132#define CFG5_FS384 (0x3 << 4)
133#define CFG5_FS512 (0x4 << 4)
134#define CFG5_FS768 (0x6 << 4)
135#define DUMMY_304 0x304
136#define CHMO_SEL (0x3 << 2)
137#define CHM1_SEL (0x3 << 4)
138#define CHM2_SEL (0x3 << 6)
139#define AUDIO_I2S_NCTS_SEL BIT(1)
140#define AUDIO_I2S_NCTS_SEL_64 (1 << 1)
141#define AUDIO_I2S_NCTS_SEL_128 (0 << 1)
142#define NEW_GCP_CTRL BIT(0)
143#define NEW_GCP_CTRL_MERGE BIT(0)
144#define GRL_L_STATUS_0 0x200
145#define GRL_L_STATUS_1 0x204
146#define GRL_L_STATUS_2 0x208
147#define GRL_L_STATUS_3 0x20c
148#define GRL_L_STATUS_4 0x210
149#define GRL_L_STATUS_5 0x214
150#define GRL_L_STATUS_6 0x218
151#define GRL_L_STATUS_7 0x21c
152#define GRL_L_STATUS_8 0x220
153#define GRL_L_STATUS_9 0x224
154#define GRL_L_STATUS_10 0x228
155#define GRL_L_STATUS_11 0x22c
156#define GRL_L_STATUS_12 0x230
157#define GRL_L_STATUS_13 0x234
158#define GRL_L_STATUS_14 0x238
159#define GRL_L_STATUS_15 0x23c
160#define GRL_L_STATUS_16 0x240
161#define GRL_L_STATUS_17 0x244
162#define GRL_L_STATUS_18 0x248
163#define GRL_L_STATUS_19 0x24c
164#define GRL_L_STATUS_20 0x250
165#define GRL_L_STATUS_21 0x254
166#define GRL_L_STATUS_22 0x258
167#define GRL_L_STATUS_23 0x25c
168#define GRL_R_STATUS_0 0x260
169#define GRL_R_STATUS_1 0x264
170#define GRL_R_STATUS_2 0x268
171#define GRL_R_STATUS_3 0x26c
172#define GRL_R_STATUS_4 0x270
173#define GRL_R_STATUS_5 0x274
174#define GRL_R_STATUS_6 0x278
175#define GRL_R_STATUS_7 0x27c
176#define GRL_R_STATUS_8 0x280
177#define GRL_R_STATUS_9 0x284
178#define GRL_R_STATUS_10 0x288
179#define GRL_R_STATUS_11 0x28c
180#define GRL_R_STATUS_12 0x290
181#define GRL_R_STATUS_13 0x294
182#define GRL_R_STATUS_14 0x298
183#define GRL_R_STATUS_15 0x29c
184#define GRL_R_STATUS_16 0x2a0
185#define GRL_R_STATUS_17 0x2a4
186#define GRL_R_STATUS_18 0x2a8
187#define GRL_R_STATUS_19 0x2ac
188#define GRL_R_STATUS_20 0x2b0
189#define GRL_R_STATUS_21 0x2b4
190#define GRL_R_STATUS_22 0x2b8
191#define GRL_R_STATUS_23 0x2bc
192#define GRL_ABIST_CTRL0 0x2D4
193#define GRL_ABIST_CTRL1 0x2D8
194#define ABIST_EN BIT(7)
195#define ABIST_DATA_FMT (0x7 << 0)
196#define VIDEO_CFG_0 0x380
197#define VIDEO_CFG_1 0x384
198#define VIDEO_CFG_2 0x388
199#define VIDEO_CFG_3 0x38c
200#define VIDEO_CFG_4 0x390
201#define VIDEO_SOURCE_SEL BIT(7)
202#define NORMAL_PATH (1 << 7)
203#define GEN_RGB (0 << 7)
204
205#define HDMI_SYS_CFG1C 0x000
206#define HDMI_ON BIT(0)
207#define HDMI_RST BIT(1)
208#define ANLG_ON BIT(2)
209#define CFG10_DVI BIT(3)
210#define HDMI_TST BIT(3)
211#define SYS_KEYMASK1 (0xff << 8)
212#define SYS_KEYMASK2 (0xff << 16)
213#define AUD_OUTSYNC_EN BIT(24)
214#define AUD_OUTSYNC_PRE_EN BIT(25)
215#define I2CM_ON BIT(26)
216#define E2PROM_TYPE_8BIT BIT(27)
217#define MCM_E2PROM_ON BIT(28)
218#define EXT_E2PROM_ON BIT(29)
219#define HTPLG_PIN_SEL_OFF BIT(30)
220#define AES_EFUSE_ENABLE BIT(31)
221#define HDMI_SYS_CFG20 0x004
222#define DEEP_COLOR_MODE_MASK (3 << 1)
223#define COLOR_8BIT_MODE (0 << 1)
224#define COLOR_10BIT_MODE (1 << 1)
225#define COLOR_12BIT_MODE (2 << 1)
226#define COLOR_16BIT_MODE (3 << 1)
227#define DEEP_COLOR_EN BIT(0)
228#define HDMI_AUDIO_TEST_SEL BIT(8)
229#define HDMI2P0_EN BIT(11)
230#define HDMI_OUT_FIFO_EN BIT(16)
231#define HDMI_OUT_FIFO_CLK_INV BIT(17)
232#define MHL_MODE_ON BIT(28)
233#define MHL_PP_MODE BIT(29)
234#define MHL_SYNC_AUTO_EN BIT(30)
235#define HDMI_PCLK_FREE_RUN BIT(31)
236
237#define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x82000001
238#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
new file mode 100644
index 000000000000..8a24754b440f
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
@@ -0,0 +1,515 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Jie Qiu <jie.qiu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk.h>
16#include <linux/clk-provider.h>
17#include <linux/delay.h>
18#include <linux/io.h>
19#include <linux/mfd/syscon.h>
20#include <linux/module.h>
21#include <linux/phy/phy.h>
22#include <linux/platform_device.h>
23#include <linux/types.h>
24
25#define HDMI_CON0 0x00
26#define RG_HDMITX_PLL_EN BIT(31)
27#define RG_HDMITX_PLL_FBKDIV (0x7f << 24)
28#define PLL_FBKDIV_SHIFT 24
29#define RG_HDMITX_PLL_FBKSEL (0x3 << 22)
30#define PLL_FBKSEL_SHIFT 22
31#define RG_HDMITX_PLL_PREDIV (0x3 << 20)
32#define PREDIV_SHIFT 20
33#define RG_HDMITX_PLL_POSDIV (0x3 << 18)
34#define POSDIV_SHIFT 18
35#define RG_HDMITX_PLL_RST_DLY (0x3 << 16)
36#define RG_HDMITX_PLL_IR (0xf << 12)
37#define PLL_IR_SHIFT 12
38#define RG_HDMITX_PLL_IC (0xf << 8)
39#define PLL_IC_SHIFT 8
40#define RG_HDMITX_PLL_BP (0xf << 4)
41#define PLL_BP_SHIFT 4
42#define RG_HDMITX_PLL_BR (0x3 << 2)
43#define PLL_BR_SHIFT 2
44#define RG_HDMITX_PLL_BC (0x3 << 0)
45#define PLL_BC_SHIFT 0
46#define HDMI_CON1 0x04
47#define RG_HDMITX_PLL_DIVEN (0x7 << 29)
48#define PLL_DIVEN_SHIFT 29
49#define RG_HDMITX_PLL_AUTOK_EN BIT(28)
50#define RG_HDMITX_PLL_AUTOK_KF (0x3 << 26)
51#define RG_HDMITX_PLL_AUTOK_KS (0x3 << 24)
52#define RG_HDMITX_PLL_AUTOK_LOAD BIT(23)
53#define RG_HDMITX_PLL_BAND (0x3f << 16)
54#define RG_HDMITX_PLL_REF_SEL BIT(15)
55#define RG_HDMITX_PLL_BIAS_EN BIT(14)
56#define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13)
57#define RG_HDMITX_PLL_TXDIV_EN BIT(12)
58#define RG_HDMITX_PLL_TXDIV (0x3 << 10)
59#define PLL_TXDIV_SHIFT 10
60#define RG_HDMITX_PLL_LVROD_EN BIT(9)
61#define RG_HDMITX_PLL_MONVC_EN BIT(8)
62#define RG_HDMITX_PLL_MONCK_EN BIT(7)
63#define RG_HDMITX_PLL_MONREF_EN BIT(6)
64#define RG_HDMITX_PLL_TST_EN BIT(5)
65#define RG_HDMITX_PLL_TST_CK_EN BIT(4)
66#define RG_HDMITX_PLL_TST_SEL (0xf << 0)
67#define HDMI_CON2 0x08
68#define RGS_HDMITX_PLL_AUTOK_BAND (0x7f << 8)
69#define RGS_HDMITX_PLL_AUTOK_FAIL BIT(1)
70#define RG_HDMITX_EN_TX_CKLDO BIT(0)
71#define HDMI_CON3 0x0c
72#define RG_HDMITX_SER_EN (0xf << 28)
73#define RG_HDMITX_PRD_EN (0xf << 24)
74#define RG_HDMITX_PRD_IMP_EN (0xf << 20)
75#define RG_HDMITX_DRV_EN (0xf << 16)
76#define RG_HDMITX_DRV_IMP_EN (0xf << 12)
77#define DRV_IMP_EN_SHIFT 12
78#define RG_HDMITX_MHLCK_FORCE BIT(10)
79#define RG_HDMITX_MHLCK_PPIX_EN BIT(9)
80#define RG_HDMITX_MHLCK_EN BIT(8)
81#define RG_HDMITX_SER_DIN_SEL (0xf << 4)
82#define RG_HDMITX_SER_5T1_BIST_EN BIT(3)
83#define RG_HDMITX_SER_BIST_TOG BIT(2)
84#define RG_HDMITX_SER_DIN_TOG BIT(1)
85#define RG_HDMITX_SER_CLKDIG_INV BIT(0)
86#define HDMI_CON4 0x10
87#define RG_HDMITX_PRD_IBIAS_CLK (0xf << 24)
88#define RG_HDMITX_PRD_IBIAS_D2 (0xf << 16)
89#define RG_HDMITX_PRD_IBIAS_D1 (0xf << 8)
90#define RG_HDMITX_PRD_IBIAS_D0 (0xf << 0)
91#define PRD_IBIAS_CLK_SHIFT 24
92#define PRD_IBIAS_D2_SHIFT 16
93#define PRD_IBIAS_D1_SHIFT 8
94#define PRD_IBIAS_D0_SHIFT 0
95#define HDMI_CON5 0x14
96#define RG_HDMITX_DRV_IBIAS_CLK (0x3f << 24)
97#define RG_HDMITX_DRV_IBIAS_D2 (0x3f << 16)
98#define RG_HDMITX_DRV_IBIAS_D1 (0x3f << 8)
99#define RG_HDMITX_DRV_IBIAS_D0 (0x3f << 0)
100#define DRV_IBIAS_CLK_SHIFT 24
101#define DRV_IBIAS_D2_SHIFT 16
102#define DRV_IBIAS_D1_SHIFT 8
103#define DRV_IBIAS_D0_SHIFT 0
104#define HDMI_CON6 0x18
105#define RG_HDMITX_DRV_IMP_CLK (0x3f << 24)
106#define RG_HDMITX_DRV_IMP_D2 (0x3f << 16)
107#define RG_HDMITX_DRV_IMP_D1 (0x3f << 8)
108#define RG_HDMITX_DRV_IMP_D0 (0x3f << 0)
109#define DRV_IMP_CLK_SHIFT 24
110#define DRV_IMP_D2_SHIFT 16
111#define DRV_IMP_D1_SHIFT 8
112#define DRV_IMP_D0_SHIFT 0
113#define HDMI_CON7 0x1c
114#define RG_HDMITX_MHLCK_DRV_IBIAS (0x1f << 27)
115#define RG_HDMITX_SER_DIN (0x3ff << 16)
116#define RG_HDMITX_CHLDC_TST (0xf << 12)
117#define RG_HDMITX_CHLCK_TST (0xf << 8)
118#define RG_HDMITX_RESERVE (0xff << 0)
119#define HDMI_CON8 0x20
120#define RGS_HDMITX_2T1_LEV (0xf << 16)
121#define RGS_HDMITX_2T1_EDG (0xf << 12)
122#define RGS_HDMITX_5T1_LEV (0xf << 8)
123#define RGS_HDMITX_5T1_EDG (0xf << 4)
124#define RGS_HDMITX_PLUG_TST BIT(0)
125
126struct mtk_hdmi_phy {
127 void __iomem *regs;
128 struct device *dev;
129 struct clk *pll;
130 struct clk_hw pll_hw;
131 unsigned long pll_rate;
132 u8 drv_imp_clk;
133 u8 drv_imp_d2;
134 u8 drv_imp_d1;
135 u8 drv_imp_d0;
136 u32 ibias;
137 u32 ibias_up;
138};
139
140static const u8 PREDIV[3][4] = {
141 {0x0, 0x0, 0x0, 0x0}, /* 27Mhz */
142 {0x1, 0x1, 0x1, 0x1}, /* 74Mhz */
143 {0x1, 0x1, 0x1, 0x1} /* 148Mhz */
144};
145
146static const u8 TXDIV[3][4] = {
147 {0x3, 0x3, 0x3, 0x2}, /* 27Mhz */
148 {0x2, 0x1, 0x1, 0x1}, /* 74Mhz */
149 {0x1, 0x0, 0x0, 0x0} /* 148Mhz */
150};
151
152static const u8 FBKSEL[3][4] = {
153 {0x1, 0x1, 0x1, 0x1}, /* 27Mhz */
154 {0x1, 0x0, 0x1, 0x1}, /* 74Mhz */
155 {0x1, 0x0, 0x1, 0x1} /* 148Mhz */
156};
157
158static const u8 FBKDIV[3][4] = {
159 {19, 24, 29, 19}, /* 27Mhz */
160 {19, 24, 14, 19}, /* 74Mhz */
161 {19, 24, 14, 19} /* 148Mhz */
162};
163
164static const u8 DIVEN[3][4] = {
165 {0x2, 0x1, 0x1, 0x2}, /* 27Mhz */
166 {0x2, 0x2, 0x2, 0x2}, /* 74Mhz */
167 {0x2, 0x2, 0x2, 0x2} /* 148Mhz */
168};
169
170static const u8 HTPLLBP[3][4] = {
171 {0xc, 0xc, 0x8, 0xc}, /* 27Mhz */
172 {0xc, 0xf, 0xf, 0xc}, /* 74Mhz */
173 {0xc, 0xf, 0xf, 0xc} /* 148Mhz */
174};
175
176static const u8 HTPLLBC[3][4] = {
177 {0x2, 0x3, 0x3, 0x2}, /* 27Mhz */
178 {0x2, 0x3, 0x3, 0x2}, /* 74Mhz */
179 {0x2, 0x3, 0x3, 0x2} /* 148Mhz */
180};
181
182static const u8 HTPLLBR[3][4] = {
183 {0x1, 0x1, 0x0, 0x1}, /* 27Mhz */
184 {0x1, 0x2, 0x2, 0x1}, /* 74Mhz */
185 {0x1, 0x2, 0x2, 0x1} /* 148Mhz */
186};
187
188static void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
189 u32 bits)
190{
191 void __iomem *reg = hdmi_phy->regs + offset;
192 u32 tmp;
193
194 tmp = readl(reg);
195 tmp &= ~bits;
196 writel(tmp, reg);
197}
198
199static void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
200 u32 bits)
201{
202 void __iomem *reg = hdmi_phy->regs + offset;
203 u32 tmp;
204
205 tmp = readl(reg);
206 tmp |= bits;
207 writel(tmp, reg);
208}
209
210static void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
211 u32 val, u32 mask)
212{
213 void __iomem *reg = hdmi_phy->regs + offset;
214 u32 tmp;
215
216 tmp = readl(reg);
217 tmp = (tmp & ~mask) | (val & mask);
218 writel(tmp, reg);
219}
220
221static inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
222{
223 return container_of(hw, struct mtk_hdmi_phy, pll_hw);
224}
225
226static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
227{
228 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
229
230 dev_dbg(hdmi_phy->dev, "%s\n", __func__);
231
232 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
233 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
234 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN);
235 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
236 usleep_range(100, 150);
237 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
238 usleep_range(100, 150);
239 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
240 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
241
242 return 0;
243}
244
245static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
246{
247 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
248
249 dev_dbg(hdmi_phy->dev, "%s\n", __func__);
250
251 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
252 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
253 usleep_range(100, 150);
254 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
255 usleep_range(100, 150);
256 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
257 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
258 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
259 usleep_range(100, 150);
260}
261
262static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
263 unsigned long parent_rate)
264{
265 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
266 unsigned int pre_div;
267 unsigned int div;
268
269 dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__,
270 rate, parent_rate);
271
272 if (rate <= 27000000) {
273 pre_div = 0;
274 div = 3;
275 } else if (rate <= 74250000) {
276 pre_div = 1;
277 div = 2;
278 } else {
279 pre_div = 1;
280 div = 1;
281 }
282
283 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
284 (pre_div << PREDIV_SHIFT), RG_HDMITX_PLL_PREDIV);
285 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
286 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
287 (0x1 << PLL_IC_SHIFT) | (0x1 << PLL_IR_SHIFT),
288 RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR);
289 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
290 (div << PLL_TXDIV_SHIFT), RG_HDMITX_PLL_TXDIV);
291 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
292 (0x1 << PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT),
293 RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV);
294 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
295 (0x2 << PLL_DIVEN_SHIFT), RG_HDMITX_PLL_DIVEN);
296 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
297 (0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) |
298 (0x1 << PLL_BR_SHIFT),
299 RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
300 RG_HDMITX_PLL_BR);
301 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
302 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
303 (0x3 << PRD_IBIAS_CLK_SHIFT) |
304 (0x3 << PRD_IBIAS_D2_SHIFT) |
305 (0x3 << PRD_IBIAS_D1_SHIFT) |
306 (0x3 << PRD_IBIAS_D0_SHIFT),
307 RG_HDMITX_PRD_IBIAS_CLK |
308 RG_HDMITX_PRD_IBIAS_D2 |
309 RG_HDMITX_PRD_IBIAS_D1 |
310 RG_HDMITX_PRD_IBIAS_D0);
311 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
312 (0x0 << DRV_IMP_EN_SHIFT), RG_HDMITX_DRV_IMP_EN);
313 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
314 (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
315 (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
316 (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
317 (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
318 RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
319 RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
320 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
321 (hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) |
322 (hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) |
323 (hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) |
324 (hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT),
325 RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 |
326 RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0);
327 return 0;
328}
329
330static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
331 unsigned long *parent_rate)
332{
333 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
334
335 hdmi_phy->pll_rate = rate;
336 if (rate <= 74250000)
337 *parent_rate = rate;
338 else
339 *parent_rate = rate / 2;
340
341 return rate;
342}
343
344static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
345 unsigned long parent_rate)
346{
347 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
348
349 return hdmi_phy->pll_rate;
350}
351
352static const struct clk_ops mtk_hdmi_pll_ops = {
353 .prepare = mtk_hdmi_pll_prepare,
354 .unprepare = mtk_hdmi_pll_unprepare,
355 .set_rate = mtk_hdmi_pll_set_rate,
356 .round_rate = mtk_hdmi_pll_round_rate,
357 .recalc_rate = mtk_hdmi_pll_recalc_rate,
358};
359
360static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
361{
362 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
363 RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN |
364 RG_HDMITX_DRV_EN);
365 usleep_range(100, 150);
366}
367
368static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
369{
370 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
371 RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN |
372 RG_HDMITX_SER_EN);
373}
374
375static int mtk_hdmi_phy_power_on(struct phy *phy)
376{
377 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
378 int ret;
379
380 ret = clk_prepare_enable(hdmi_phy->pll);
381 if (ret < 0)
382 return ret;
383
384 mtk_hdmi_phy_enable_tmds(hdmi_phy);
385
386 return 0;
387}
388
389static int mtk_hdmi_phy_power_off(struct phy *phy)
390{
391 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
392
393 mtk_hdmi_phy_disable_tmds(hdmi_phy);
394 clk_disable_unprepare(hdmi_phy->pll);
395
396 return 0;
397}
398
399static const struct phy_ops mtk_hdmi_phy_ops = {
400 .power_on = mtk_hdmi_phy_power_on,
401 .power_off = mtk_hdmi_phy_power_off,
402 .owner = THIS_MODULE,
403};
404
405static int mtk_hdmi_phy_probe(struct platform_device *pdev)
406{
407 struct device *dev = &pdev->dev;
408 struct mtk_hdmi_phy *hdmi_phy;
409 struct resource *mem;
410 struct clk *ref_clk;
411 const char *ref_clk_name;
412 struct clk_init_data clk_init = {
413 .ops = &mtk_hdmi_pll_ops,
414 .num_parents = 1,
415 .parent_names = (const char * const *)&ref_clk_name,
416 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
417 };
418 struct phy *phy;
419 struct phy_provider *phy_provider;
420 int ret;
421
422 hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
423 if (!hdmi_phy)
424 return -ENOMEM;
425
426 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
427 hdmi_phy->regs = devm_ioremap_resource(dev, mem);
428 if (IS_ERR(hdmi_phy->regs)) {
429 ret = PTR_ERR(hdmi_phy->regs);
430 dev_err(dev, "Failed to get memory resource: %d\n", ret);
431 return ret;
432 }
433
434 ref_clk = devm_clk_get(dev, "pll_ref");
435 if (IS_ERR(ref_clk)) {
436 ret = PTR_ERR(ref_clk);
437 dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
438 ret);
439 return ret;
440 }
441 ref_clk_name = __clk_get_name(ref_clk);
442
443 ret = of_property_read_string(dev->of_node, "clock-output-names",
444 &clk_init.name);
445 if (ret < 0) {
446 dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
447 return ret;
448 }
449
450 hdmi_phy->pll_hw.init = &clk_init;
451 hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
452 if (IS_ERR(hdmi_phy->pll)) {
453 ret = PTR_ERR(hdmi_phy->pll);
454 dev_err(dev, "Failed to register PLL: %d\n", ret);
455 return ret;
456 }
457
458 ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
459 &hdmi_phy->ibias);
460 if (ret < 0) {
461 dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
462 return ret;
463 }
464
465 ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
466 &hdmi_phy->ibias_up);
467 if (ret < 0) {
468 dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
469 return ret;
470 }
471
472 dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
473 hdmi_phy->drv_imp_clk = 0x30;
474 hdmi_phy->drv_imp_d2 = 0x30;
475 hdmi_phy->drv_imp_d1 = 0x30;
476 hdmi_phy->drv_imp_d0 = 0x30;
477
478 phy = devm_phy_create(dev, NULL, &mtk_hdmi_phy_ops);
479 if (IS_ERR(phy)) {
480 dev_err(dev, "Failed to create HDMI PHY\n");
481 return PTR_ERR(phy);
482 }
483 phy_set_drvdata(phy, hdmi_phy);
484
485 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
486 if (IS_ERR(phy_provider))
487 return PTR_ERR(phy_provider);
488
489 hdmi_phy->dev = dev;
490 return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
491 hdmi_phy->pll);
492}
493
494static int mtk_hdmi_phy_remove(struct platform_device *pdev)
495{
496 return 0;
497}
498
499static const struct of_device_id mtk_hdmi_phy_match[] = {
500 { .compatible = "mediatek,mt8173-hdmi-phy", },
501 {},
502};
503
504struct platform_driver mtk_hdmi_phy_driver = {
505 .probe = mtk_hdmi_phy_probe,
506 .remove = mtk_hdmi_phy_remove,
507 .driver = {
508 .name = "mediatek-hdmi-phy",
509 .of_match_table = mtk_hdmi_phy_match,
510 },
511};
512
513MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
514MODULE_DESCRIPTION("MediaTek MT8173 HDMI PHY Driver");
515MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 17:41:48 -0500