8 files changed, 44 insertions, 40 deletions

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index b10770cfccd2..32f96b8cd9c4 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -329,15 +329,7 @@ __create_hw_context(struct drm_i915_private *dev_priv,
         ctx->desc_template =
                 default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
 
-        /*
-         * GuC requires the ring to be placed in Non-WOPCM memory. If GuC is not
-         * present or not in use we still need a small bias as ring wraparound
-         * at offset 0 sometimes hangs. No idea why.
-         */
-        if (USES_GUC(dev_priv))
-                ctx->ggtt_offset_bias = dev_priv->guc.ggtt_pin_bias;
-        else
-                ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
+        ctx->ggtt_offset_bias = dev_priv->ggtt.pin_bias;
 
         return ctx;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 1b476423bfab..87219870d559 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2929,6 +2929,15 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
         struct drm_mm_node *entry;
         int ret;
 
+        /*
+         * GuC requires all resources that we're sharing with it to be placed in
+         * non-WOPCM memory. If GuC is not present or not in use we still need a
+         * small bias as ring wraparound at offset 0 sometimes hangs. No idea
+         * why.
+         */
+        ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
+                               intel_guc_reserved_gtt_size(&dev_priv->guc));
+
         ret = intel_vgt_balloon(dev_priv);
         if (ret)
                 return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 2a116a91420b..ce945bf78a89 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -401,6 +401,8 @@ struct i915_ggtt {
 
         int mtrr;
 
+        u32 pin_bias;
+
         struct drm_mm_node error_capture;
 };
 
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index af5296b015f5..f1ba40bbe6f9 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -208,6 +208,11 @@ static inline u32 i915_ggtt_offset(const struct i915_vma *vma)
         return lower_32_bits(vma->node.start);
 }
 
+static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma)
+{
+        return i915_vm_to_ggtt(vma->vm)->pin_bias;
+}
+
 static inline struct i915_vma *i915_vma_get(struct i915_vma *vma)
 {
         i915_gem_object_get(vma->obj);
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index deb6a2053eaf..230aea69385d 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -27,8 +27,6 @@
 #include "intel_guc_submission.h"
 #include "i915_drv.h"
 
-static void guc_init_ggtt_pin_bias(struct intel_guc *guc);
-
 static void gen8_guc_raise_irq(struct intel_guc *guc)
 {
         struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -144,8 +142,6 @@ int intel_guc_init_misc(struct intel_guc *guc)
         struct drm_i915_private *i915 = guc_to_i915(guc);
         int ret;
 
-        guc_init_ggtt_pin_bias(guc);
-
         ret = guc_init_wq(guc);
         if (ret)
                 return ret;
@@ -607,22 +603,6 @@ int intel_guc_resume(struct intel_guc *guc)
  */
 
 /**
- * guc_init_ggtt_pin_bias() - Initialize the GuC ggtt_pin_bias value.
- * @guc: intel_guc structure.
- *
- * This function will calculate and initialize the ggtt_pin_bias value
- * based on the GuC WOPCM size.
- */
-static void guc_init_ggtt_pin_bias(struct intel_guc *guc)
-{
-        struct drm_i915_private *i915 = guc_to_i915(guc);
-
-        GEM_BUG_ON(!i915->wopcm.size);
-
-        guc->ggtt_pin_bias = i915->wopcm.guc.size;
-}
-
-/**
  * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
  * @guc:        the guc
  * @size:       size of area to allocate (both virtual space and memory)
@@ -640,6 +620,7 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
         struct drm_i915_private *dev_priv = guc_to_i915(guc);
         struct drm_i915_gem_object *obj;
         struct i915_vma *vma;
+        u64 flags;
         int ret;
 
         obj = i915_gem_object_create(dev_priv, size);
@@ -650,8 +631,8 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
         if (IS_ERR(vma))
                 goto err;
 
-        ret = i915_vma_pin(vma, 0, 0,
-                           PIN_GLOBAL | PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
+        flags = PIN_GLOBAL | PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
+        ret = i915_vma_pin(vma, 0, 0, flags);
         if (ret) {
                 vma = ERR_PTR(ret);
                 goto err;
@@ -663,3 +644,20 @@ err:
         i915_gem_object_put(obj);
         return vma;
 }
+
+/**
+ * intel_guc_reserved_gtt_size()
+ * @guc:        intel_guc structure
+ *
+ * The GuC WOPCM mapping shadows the lower part of the GGTT, so if we are using
+ * GuC we can't have any objects pinned in that region. This function returns
+ * the size of the shadowed region.
+ *
+ * Returns:
+ * 0 if GuC is not present or not in use.
+ * Otherwise, the GuC WOPCM size.
+ */
+u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
+{
+        return guc_to_i915(guc)->wopcm.guc.size;
+}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 4121928a495e..ad42faf48c46 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -49,9 +49,6 @@ struct intel_guc {
         struct intel_guc_log log;
         struct intel_guc_ct ct;
 
-        /* Offset where Non-WOPCM memory starts. */
-        u32 ggtt_pin_bias;
-
         /* Log snapshot if GuC errors during load */
         struct drm_i915_gem_object *load_err_log;
 
@@ -130,10 +127,10 @@ static inline void intel_guc_to_host_event_handler(struct intel_guc *guc)
  * @vma: i915 graphics virtual memory area.
  *
  * GuC does not allow any gfx GGTT address that falls into range
- * [0, GuC ggtt_pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
- * Currently, in order to exclude [0, GuC ggtt_pin_bias) address space from
+ * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
+ * Currently, in order to exclude [0, ggtt.pin_bias) address space from
  * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma()
- * and pinned with PIN_OFFSET_BIAS along with the value of GuC ggtt_pin_bias.
+ * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.
  *
  * Return: GGTT offset of the @vma.
  */
@@ -142,7 +139,7 @@ static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
 {
         u32 offset = i915_ggtt_offset(vma);
 
-        GEM_BUG_ON(offset < guc->ggtt_pin_bias);
+        GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma));
         GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
 
         return offset;
@@ -168,6 +165,7 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
 int intel_guc_suspend(struct intel_guc *guc);
 int intel_guc_resume(struct intel_guc *guc);
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
+u32 intel_guc_reserved_gtt_size(struct intel_guc *guc);
 
 static inline int intel_guc_sanitize(struct intel_guc *guc)
 {
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index ffcad5fad6a7..37ef540dd280 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -63,7 +63,7 @@ int intel_huc_auth(struct intel_huc *huc)
                 return -ENOEXEC;
 
         vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
-                                       PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
+                                       PIN_OFFSET_BIAS | i915->ggtt.pin_bias);
         if (IS_ERR(vma)) {
                 ret = PTR_ERR(vma);
                 DRM_ERROR("HuC: Failed to pin huc fw object %d\n", ret);
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c
index 6e8e0b546743..fd496416087c 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/intel_uc_fw.c
@@ -222,7 +222,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
                 goto fail;
         }
 
-        ggtt_pin_bias = to_i915(uc_fw->obj->base.dev)->guc.ggtt_pin_bias;
+        ggtt_pin_bias = to_i915(uc_fw->obj->base.dev)->ggtt.pin_bias;
         vma = i915_gem_object_ggtt_pin(uc_fw->obj, NULL, 0, 0,
                                        PIN_OFFSET_BIAS | ggtt_pin_bias);
         if (IS_ERR(vma)) {