17 files changed, 81 insertions, 62 deletions

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 701a3c6f1669..85d4c57870fb 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -1628,7 +1628,7 @@ static int perform_bb_shadow(struct parser_exec_state *s)
         struct intel_shadow_bb_entry *entry_obj;
         struct intel_vgpu *vgpu = s->vgpu;
         unsigned long gma = 0;
-        uint32_t bb_size;
+        int bb_size;
         void *dst = NULL;
         int ret = 0;
 
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 3c318439a659..355120865efd 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -282,6 +282,7 @@ static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
                                     int type, unsigned int resolution)
 {
+        struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
         struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
 
         if (WARN_ON(resolution >= GVT_EDID_NUM))
@@ -307,6 +308,7 @@ static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
         port->type = type;
 
         emulate_monitor_status_change(vgpu);
+        vgpu_vreg(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
         return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c
index 4427be18e4a9..940cdaaa3f24 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.c
+++ b/drivers/gpu/drm/i915/gvt/execlist.c
@@ -496,6 +496,12 @@ static int prepare_execlist_workload(struct intel_vgpu_workload *workload)
                 goto err_unpin_mm;
         }
 
+        ret = intel_gvt_generate_request(workload);
+        if (ret) {
+                gvt_vgpu_err("fail to generate request\n");
+                goto err_unpin_mm;
+        }
+
         ret = prepare_shadow_batch_buffer(workload);
         if (ret) {
                 gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 2801d70579d8..8e331142badb 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -311,9 +311,9 @@ static inline int gtt_set_entry64(void *pt,
 
 #define GTT_HAW 46
 
-#define ADDR_1G_MASK (((1UL << (GTT_HAW - 30 + 1)) - 1) << 30)
-#define ADDR_2M_MASK (((1UL << (GTT_HAW - 21 + 1)) - 1) << 21)
-#define ADDR_4K_MASK (((1UL << (GTT_HAW - 12 + 1)) - 1) << 12)
+#define ADDR_1G_MASK (((1UL << (GTT_HAW - 30)) - 1) << 30)
+#define ADDR_2M_MASK (((1UL << (GTT_HAW - 21)) - 1) << 21)
+#define ADDR_4K_MASK (((1UL << (GTT_HAW - 12)) - 1) << 12)
 
 static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
 {
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index a5bed2e71b92..44cd5ff5e97d 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1381,40 +1381,6 @@ static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
         return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
 }
 
-static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset,
-                void *p_data, unsigned int bytes)
-{
-        struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
-        u32 v = *(u32 *)p_data;
-
-        if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
-                return intel_vgpu_default_mmio_write(vgpu,
-                                offset, p_data, bytes);
-
-        switch (offset) {
-        case 0x4ddc:
-                /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
-                vgpu_vreg(vgpu, offset) = v & ~(1 << 31);
-                break;
-        case 0x42080:
-                /* bypass WaCompressedResourceDisplayNewHashMode */
-                vgpu_vreg(vgpu, offset) = v & ~(1 << 15);
-                break;
-        case 0xe194:
-                /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
-                vgpu_vreg(vgpu, offset) = v & ~(1 << 8);
-                break;
-        case 0x7014:
-                /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
-                vgpu_vreg(vgpu, offset) = v & ~(1 << 13);
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
                 void *p_data, unsigned int bytes)
 {
@@ -1671,8 +1637,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
         MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
         MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
                 NULL, NULL);
-        MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
-                 skl_misc_ctl_write);
+        MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
+                 NULL, NULL);
         MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL);
         MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL);
         MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL);
@@ -2564,8 +2530,7 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
         MMIO_D(0x6e570, D_BDW_PLUS);
         MMIO_D(0x65f10, D_BDW_PLUS);
 
-        MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,
-                 skl_misc_ctl_write);
+        MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
         MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
         MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
         MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
@@ -2615,8 +2580,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
         MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
         MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
         MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
-        MMIO_DH(0x4ddc, D_SKL_PLUS, NULL, skl_misc_ctl_write);
-        MMIO_DH(0x42080, D_SKL_PLUS, NULL, skl_misc_ctl_write);
+        MMIO_DH(0x4ddc, D_SKL_PLUS, NULL, NULL);
+        MMIO_DH(0x42080, D_SKL_PLUS, NULL, NULL);
         MMIO_D(0x45504, D_SKL_PLUS);
         MMIO_D(0x45520, D_SKL_PLUS);
         MMIO_D(0x46000, D_SKL_PLUS);
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index f6ded475bb2c..3ac1dc97a7a0 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -140,9 +140,10 @@ static int shadow_context_status_change(struct notifier_block *nb,
         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
         enum intel_engine_id ring_id = req->engine->id;
         struct intel_vgpu_workload *workload;
+        unsigned long flags;
 
         if (!is_gvt_request(req)) {
-                spin_lock_bh(&scheduler->mmio_context_lock);
+                spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
                 if (action == INTEL_CONTEXT_SCHEDULE_IN &&
                     scheduler->engine_owner[ring_id]) {
                         /* Switch ring from vGPU to host. */
@@ -150,7 +151,7 @@ static int shadow_context_status_change(struct notifier_block *nb,
                                               NULL, ring_id);
                         scheduler->engine_owner[ring_id] = NULL;
                 }
-                spin_unlock_bh(&scheduler->mmio_context_lock);
+                spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
 
                 return NOTIFY_OK;
         }
@@ -161,7 +162,7 @@ static int shadow_context_status_change(struct notifier_block *nb,
 
         switch (action) {
         case INTEL_CONTEXT_SCHEDULE_IN:
-                spin_lock_bh(&scheduler->mmio_context_lock);
+                spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
                 if (workload->vgpu != scheduler->engine_owner[ring_id]) {
                         /* Switch ring from host to vGPU or vGPU to vGPU. */
                         intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
@@ -170,7 +171,7 @@ static int shadow_context_status_change(struct notifier_block *nb,
                 } else
                         gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n",
                                       ring_id, workload->vgpu->id);
-                spin_unlock_bh(&scheduler->mmio_context_lock);
+                spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
                 atomic_set(&workload->shadow_ctx_active, 1);
                 break;
         case INTEL_CONTEXT_SCHEDULE_OUT:
@@ -253,7 +254,6 @@ int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
         struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
         struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
         struct intel_engine_cs *engine = dev_priv->engine[ring_id];
-        struct drm_i915_gem_request *rq;
         struct intel_vgpu *vgpu = workload->vgpu;
         struct intel_ring *ring;
         int ret;
@@ -299,6 +299,26 @@ int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
         ret = populate_shadow_context(workload);
         if (ret)
                 goto err_unpin;
+        workload->shadowed = true;
+        return 0;
+
+err_unpin:
+        engine->context_unpin(engine, shadow_ctx);
+err_shadow:
+        release_shadow_wa_ctx(&workload->wa_ctx);
+err_scan:
+        return ret;
+}
+
+int intel_gvt_generate_request(struct intel_vgpu_workload *workload)
+{
+        int ring_id = workload->ring_id;
+        struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
+        struct intel_engine_cs *engine = dev_priv->engine[ring_id];
+        struct drm_i915_gem_request *rq;
+        struct intel_vgpu *vgpu = workload->vgpu;
+        struct i915_gem_context *shadow_ctx = vgpu->shadow_ctx;
+        int ret;
 
         rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx);
         if (IS_ERR(rq)) {
@@ -313,14 +333,11 @@ int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
         ret = copy_workload_to_ring_buffer(workload);
         if (ret)
                 goto err_unpin;
-        workload->shadowed = true;
         return 0;
 
 err_unpin:
         engine->context_unpin(engine, shadow_ctx);
-err_shadow:
         release_shadow_wa_ctx(&workload->wa_ctx);
-err_scan:
         return ret;
 }
 
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.h b/drivers/gpu/drm/i915/gvt/scheduler.h
index 2d694f6c0907..b9f872204d7e 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.h
+++ b/drivers/gpu/drm/i915/gvt/scheduler.h
@@ -142,4 +142,7 @@ int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu);
 void intel_vgpu_clean_gvt_context(struct intel_vgpu *vgpu);
 
 void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx);
+
+int intel_gvt_generate_request(struct intel_vgpu_workload *workload);
+
 #endif
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 960d3d8b95b8..2cf10d17acfb 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1714,6 +1714,7 @@ static int i915_drm_resume(struct drm_device *dev)
         intel_guc_resume(dev_priv);
 
         intel_modeset_init_hw(dev);
+        intel_init_clock_gating(dev_priv);
 
         spin_lock_irq(&dev_priv->irq_lock);
         if (dev_priv->display.hpd_irq_setup)
@@ -2618,6 +2619,8 @@ static int intel_runtime_resume(struct device *kdev)
                 ret = vlv_resume_prepare(dev_priv, true);
         }
 
+        intel_uncore_runtime_resume(dev_priv);
+
         /*
          * No point of rolling back things in case of an error, as the best
          * we can do is to hope that things will still work (and disable RPM).
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c
index 135fc750a837..382a77a1097e 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -172,7 +172,9 @@ i915_mmu_notifier_create(struct mm_struct *mm)
         spin_lock_init(&mn->lock);
         mn->mn.ops = &i915_gem_userptr_notifier;
         mn->objects = RB_ROOT_CACHED;
-        mn->wq = alloc_workqueue("i915-userptr-release", WQ_UNBOUND, 0);
+        mn->wq = alloc_workqueue("i915-userptr-release",
+                                 WQ_UNBOUND | WQ_MEM_RECLAIM,
+                                 0);
         if (mn->wq == NULL) {
                 kfree(mn);
                 return ERR_PTR(-ENOMEM);
@@ -827,7 +829,7 @@ int i915_gem_init_userptr(struct drm_i915_private *dev_priv)
 
         dev_priv->mm.userptr_wq =
                 alloc_workqueue("i915-userptr-acquire",
-                                WQ_HIGHPRI | WQ_MEM_RECLAIM,
+                                WQ_HIGHPRI | WQ_UNBOUND,
                                 0);
         if (!dev_priv->mm.userptr_wq)
                 return -ENOMEM;
diff --git a/drivers/gpu/drm/i915/i915_gemfs.c b/drivers/gpu/drm/i915/i915_gemfs.c
index e2993857df37..888b7d3f04c3 100644
--- a/drivers/gpu/drm/i915/i915_gemfs.c
+++ b/drivers/gpu/drm/i915/i915_gemfs.c
@@ -52,7 +52,8 @@ int i915_gemfs_init(struct drm_i915_private *i915)
 
         if (has_transparent_hugepage()) {
                 struct super_block *sb = gemfs->mnt_sb;
-                char options[] = "huge=within_size";
+                /* FIXME: Disabled until we get W/A for read BW issue. */
+                char options[] = "huge=never";
                 int flags = 0;
                 int err;
 
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 48e1ba01ccf8..5f8b9f1f40f1 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -517,6 +517,7 @@ static void __intel_engine_remove_wait(struct intel_engine_cs *engine,
 
         GEM_BUG_ON(RB_EMPTY_NODE(&wait->node));
         rb_erase(&wait->node, &b->waiters);
+        RB_CLEAR_NODE(&wait->node);
 
 out:
         GEM_BUG_ON(b->irq_wait == wait);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7bc60c848940..6c7f8bca574e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1736,7 +1736,7 @@ extern struct drm_display_mode *intel_find_panel_downclock(
 int intel_backlight_device_register(struct intel_connector *connector);
 void intel_backlight_device_unregister(struct intel_connector *connector);
 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
-static int intel_backlight_device_register(struct intel_connector *connector)
+static inline int intel_backlight_device_register(struct intel_connector *connector)
 {
         return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index b8af35187d22..ea96682568e8 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -697,10 +697,8 @@ static void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
 
         /* Due to peculiar init order wrt to hpd handling this is separate. */
         if (drm_fb_helper_initial_config(&ifbdev->helper,
-                                         ifbdev->preferred_bpp)) {
+                                         ifbdev->preferred_bpp))
                 intel_fbdev_unregister(to_i915(ifbdev->helper.dev));
-                intel_fbdev_fini(to_i915(ifbdev->helper.dev));
-        }
 }
 
 void intel_fbdev_initial_config_async(struct drm_device *dev)
@@ -800,7 +798,11 @@ void intel_fbdev_output_poll_changed(struct drm_device *dev)
 {
         struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
 
-        if (ifbdev)
+        if (!ifbdev)
+                return;
+
+        intel_fbdev_sync(ifbdev);
+        if (ifbdev->vma)
                 drm_fb_helper_hotplug_event(&ifbdev->helper);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 5132dc814788..4dea833f9d1b 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -487,7 +487,8 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
                                            crtc_state->limited_color_range ?
                                            HDMI_QUANTIZATION_RANGE_LIMITED :
                                            HDMI_QUANTIZATION_RANGE_FULL,
-                                           intel_hdmi->rgb_quant_range_selectable);
+                                           intel_hdmi->rgb_quant_range_selectable,
+                                           is_hdmi2_sink);
 
         /* TODO: handle pixel repetition for YCBCR420 outputs */
         intel_write_infoframe(encoder, crtc_state, &frame);
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index eb5827110d8f..49fdf09f9919 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -438,7 +438,9 @@ static bool
 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
 {
         return (i + 1 < num &&
-                !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
+                msgs[i].addr == msgs[i + 1].addr &&
+                !(msgs[i].flags & I2C_M_RD) &&
+                (msgs[i].len == 1 || msgs[i].len == 2) &&
                 (msgs[i + 1].flags & I2C_M_RD));
 }
 
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 20e3c65c0999..8c2ce81f01c2 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -434,6 +434,12 @@ void intel_uncore_resume_early(struct drm_i915_private *dev_priv)
         i915_check_and_clear_faults(dev_priv);
 }
 
+void intel_uncore_runtime_resume(struct drm_i915_private *dev_priv)
+{
+        iosf_mbi_register_pmic_bus_access_notifier(
+                &dev_priv->uncore.pmic_bus_access_nb);
+}
+
 void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
 {
         i915_modparams.enable_rc6 =
@@ -1240,8 +1246,15 @@ static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
                  * bus, which will be busy after this notification, leading to:
                  * "render: timed out waiting for forcewake ack request."
                  * errors.
+                 *
+                 * The notifier is unregistered during intel_runtime_suspend(),
+                 * so it's ok to access the HW here without holding a RPM
+                 * wake reference -> disable wakeref asserts for the time of
+                 * the access.
                  */
+                disable_rpm_wakeref_asserts(dev_priv);
                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+                enable_rpm_wakeref_asserts(dev_priv);
                 break;
         case MBI_PMIC_BUS_ACCESS_END:
                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 582771251b57..9ce079b5dd0d 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -134,6 +134,7 @@ bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv
 void intel_uncore_fini(struct drm_i915_private *dev_priv);
 void intel_uncore_suspend(struct drm_i915_private *dev_priv);
 void intel_uncore_resume_early(struct drm_i915_private *dev_priv);
+void intel_uncore_runtime_resume(struct drm_i915_private *dev_priv);
 
 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);