1 files changed, 40 insertions, 32 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 87eebc13c0d8..c5eb26a7ee79 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -150,8 +150,7 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode)
          */
         if (mode & EMIT_INVALIDATE) {
                 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
-                *cs++ = i915_ggtt_offset(rq->engine->scratch) |
-                        PIPE_CONTROL_GLOBAL_GTT;
+                *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;
                 *cs++ = 0;
                 *cs++ = 0;
 
@@ -159,8 +158,7 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode)
                         *cs++ = MI_FLUSH;
 
                 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
-                *cs++ = i915_ggtt_offset(rq->engine->scratch) |
-                        PIPE_CONTROL_GLOBAL_GTT;
+                *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;
                 *cs++ = 0;
                 *cs++ = 0;
         }
@@ -212,8 +210,7 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode)
 static int
 intel_emit_post_sync_nonzero_flush(struct i915_request *rq)
 {
-        u32 scratch_addr =
-                i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
+        u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
         u32 *cs;
 
         cs = intel_ring_begin(rq, 6);
@@ -246,8 +243,7 @@ intel_emit_post_sync_nonzero_flush(struct i915_request *rq)
 static int
 gen6_render_ring_flush(struct i915_request *rq, u32 mode)
 {
-        u32 scratch_addr =
-                i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
+        u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
         u32 *cs, flags = 0;
         int ret;
 
@@ -316,8 +312,7 @@ gen7_render_ring_cs_stall_wa(struct i915_request *rq)
 static int
 gen7_render_ring_flush(struct i915_request *rq, u32 mode)
 {
-        u32 scratch_addr =
-                i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
+        u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
         u32 *cs, flags = 0;
 
         /*
@@ -529,6 +524,13 @@ static int init_ring_common(struct intel_engine_cs *engine)
 
         intel_engine_reset_breadcrumbs(engine);
 
+        if (HAS_LEGACY_SEMAPHORES(engine->i915)) {
+                I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
+                I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
+                if (HAS_VEBOX(dev_priv))
+                        I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
+        }
+
         /* Enforce ordering by reading HEAD register back */
         I915_READ_HEAD(engine);
 
@@ -546,10 +548,11 @@ static int init_ring_common(struct intel_engine_cs *engine)
         /* Check that the ring offsets point within the ring! */
         GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
         GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
-
         intel_ring_update_space(ring);
+
+        /* First wake the ring up to an empty/idle ring */
         I915_WRITE_HEAD(engine, ring->head);
-        I915_WRITE_TAIL(engine, ring->tail);
+        I915_WRITE_TAIL(engine, ring->head);
         (void)I915_READ_TAIL(engine);
 
         I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID);
@@ -574,6 +577,12 @@ static int init_ring_common(struct intel_engine_cs *engine)
         if (INTEL_GEN(dev_priv) > 2)
                 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 
+        /* Now awake, let it get started */
+        if (ring->tail != ring->head) {
+                I915_WRITE_TAIL(engine, ring->tail);
+                (void)I915_READ_TAIL(engine);
+        }
+
         /* Papering over lost _interrupts_ immediately following the restart */
         intel_engine_wakeup(engine);
 out:
@@ -642,7 +651,7 @@ static int intel_rcs_ctx_init(struct i915_request *rq)
 {
         int ret;
 
-        ret = intel_ctx_workarounds_emit(rq);
+        ret = intel_engine_emit_ctx_wa(rq);
         if (ret != 0)
                 return ret;
 
@@ -660,8 +669,6 @@ static int init_render_ring(struct intel_engine_cs *engine)
         if (ret)
                 return ret;
 
-        intel_whitelist_workarounds_apply(engine);
-
         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
         if (IS_GEN(dev_priv, 4, 6))
                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
@@ -743,9 +750,18 @@ static void cancel_requests(struct intel_engine_cs *engine)
         /* Mark all submitted requests as skipped. */
         list_for_each_entry(request, &engine->timeline.requests, link) {
                 GEM_BUG_ON(!request->global_seqno);
-                if (!i915_request_completed(request))
-                        dma_fence_set_error(&request->fence, -EIO);
+
+                if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
+                             &request->fence.flags))
+                        continue;
+
+                dma_fence_set_error(&request->fence, -EIO);
         }
+
+        intel_write_status_page(engine,
+                                I915_GEM_HWS_INDEX,
+                                intel_engine_last_submit(engine));
+
         /* Remaining _unready_ requests will be nop'ed when submitted */
 
         spin_unlock_irqrestore(&engine->timeline.lock, flags);
@@ -973,7 +989,7 @@ i965_emit_bb_start(struct i915_request *rq,
 }
 
 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
-#define I830_BATCH_LIMIT (256*1024)
+#define I830_BATCH_LIMIT SZ_256K
 #define I830_TLB_ENTRIES (2)
 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
 static int
@@ -981,7 +997,9 @@ i830_emit_bb_start(struct i915_request *rq,
                    u64 offset, u32 len,
                    unsigned int dispatch_flags)
 {
-        u32 *cs, cs_offset = i915_ggtt_offset(rq->engine->scratch);
+        u32 *cs, cs_offset = i915_scratch_offset(rq->i915);
+
+        GEM_BUG_ON(rq->i915->gt.scratch->size < I830_WA_SIZE);
 
         cs = intel_ring_begin(rq, 6);
         if (IS_ERR(cs))
@@ -1438,7 +1456,6 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
 {
         struct i915_timeline *timeline;
         struct intel_ring *ring;
-        unsigned int size;
         int err;
 
         intel_engine_setup_common(engine);
@@ -1463,21 +1480,12 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
         GEM_BUG_ON(engine->buffer);
         engine->buffer = ring;
 
-        size = PAGE_SIZE;
-        if (HAS_BROKEN_CS_TLB(engine->i915))
-                size = I830_WA_SIZE;
-        err = intel_engine_create_scratch(engine, size);
-        if (err)
-                goto err_unpin;
-
         err = intel_engine_init_common(engine);
         if (err)
-                goto err_scratch;
+                goto err_unpin;
 
         return 0;
 
-err_scratch:
-        intel_engine_cleanup_scratch(engine);
 err_unpin:
         intel_ring_unpin(ring);
 err_ring:
@@ -1551,7 +1559,7 @@ static int flush_pd_dir(struct i915_request *rq)
         /* Stall until the page table load is complete */
         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
         *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
-        *cs++ = i915_ggtt_offset(engine->scratch);
+        *cs++ = i915_scratch_offset(rq->i915);
         *cs++ = MI_NOOP;
 
         intel_ring_advance(rq, cs);
@@ -1660,7 +1668,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
                         /* Insert a delay before the next switch! */
                         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
                         *cs++ = i915_mmio_reg_offset(last_reg);
-                        *cs++ = i915_ggtt_offset(engine->scratch);
+                        *cs++ = i915_scratch_offset(rq->i915);
                         *cs++ = MI_NOOP;
                 }
                 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;