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path: root/drivers/gpu/drm/i915/intel_psr.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_psr.c')
-rw-r--r--drivers/gpu/drm/i915/intel_psr.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 419e56342523..f71970df9936 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -274,10 +274,16 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
274 DRM_DEBUG_KMS("eDP panel supports PSR version %x\n", 274 DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",
275 intel_dp->psr_dpcd[0]); 275 intel_dp->psr_dpcd[0]);
276 276
277 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
278 DRM_DEBUG_KMS("PSR support not currently available for this panel\n");
279 return;
280 }
281
277 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 282 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
278 DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n"); 283 DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n");
279 return; 284 return;
280 } 285 }
286
281 dev_priv->psr.sink_support = true; 287 dev_priv->psr.sink_support = true;
282 dev_priv->psr.sink_sync_latency = 288 dev_priv->psr.sink_sync_latency =
283 intel_dp_get_sink_sync_latency(intel_dp); 289 intel_dp_get_sink_sync_latency(intel_dp);