1 files changed, 130 insertions, 118 deletions

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b6838b525502..54fa17a5596a 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -71,6 +71,10 @@ static bool psr_global_enabled(u32 debug)
 static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
                                const struct intel_crtc_state *crtc_state)
 {
+        /* Disable PSR2 by default for all platforms */
+        if (i915_modparams.enable_psr == -1)
+                return false;
+
         switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
         case I915_PSR_DEBUG_FORCE_PSR1:
                 return false;
@@ -79,25 +83,42 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
         }
 }
 
+static int edp_psr_shift(enum transcoder cpu_transcoder)
+{
+        switch (cpu_transcoder) {
+        case TRANSCODER_A:
+                return EDP_PSR_TRANSCODER_A_SHIFT;
+        case TRANSCODER_B:
+                return EDP_PSR_TRANSCODER_B_SHIFT;
+        case TRANSCODER_C:
+                return EDP_PSR_TRANSCODER_C_SHIFT;
+        default:
+                MISSING_CASE(cpu_transcoder);
+                /* fallthrough */
+        case TRANSCODER_EDP:
+                return EDP_PSR_TRANSCODER_EDP_SHIFT;
+        }
+}
+
 void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
 {
         u32 debug_mask, mask;
+        enum transcoder cpu_transcoder;
+        u32 transcoders = BIT(TRANSCODER_EDP);
+
+        if (INTEL_GEN(dev_priv) >= 8)
+                transcoders |= BIT(TRANSCODER_A) |
+                               BIT(TRANSCODER_B) |
+                               BIT(TRANSCODER_C);
 
-        mask = EDP_PSR_ERROR(TRANSCODER_EDP);
-        debug_mask = EDP_PSR_POST_EXIT(TRANSCODER_EDP) |
-                     EDP_PSR_PRE_ENTRY(TRANSCODER_EDP);
-
-        if (INTEL_GEN(dev_priv) >= 8) {
-                mask |= EDP_PSR_ERROR(TRANSCODER_A) |
-                        EDP_PSR_ERROR(TRANSCODER_B) |
-                        EDP_PSR_ERROR(TRANSCODER_C);
-
-                debug_mask |= EDP_PSR_POST_EXIT(TRANSCODER_A) |
-                              EDP_PSR_PRE_ENTRY(TRANSCODER_A) |
-                              EDP_PSR_POST_EXIT(TRANSCODER_B) |
-                              EDP_PSR_PRE_ENTRY(TRANSCODER_B) |
-                              EDP_PSR_POST_EXIT(TRANSCODER_C) |
-                              EDP_PSR_PRE_ENTRY(TRANSCODER_C);
+        debug_mask = 0;
+        mask = 0;
+        for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
+                int shift = edp_psr_shift(cpu_transcoder);
+
+                mask |= EDP_PSR_ERROR(shift);
+                debug_mask |= EDP_PSR_POST_EXIT(shift) |
+                              EDP_PSR_PRE_ENTRY(shift);
         }
 
         if (debug & I915_PSR_DEBUG_IRQ)
@@ -155,18 +176,20 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
                                BIT(TRANSCODER_C);
 
         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
+                int shift = edp_psr_shift(cpu_transcoder);
+
                 /* FIXME: Exit PSR and link train manually when this happens. */
-                if (psr_iir & EDP_PSR_ERROR(cpu_transcoder))
+                if (psr_iir & EDP_PSR_ERROR(shift))
                         DRM_DEBUG_KMS("[transcoder %s] PSR aux error\n",
                                       transcoder_name(cpu_transcoder));
 
-                if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
+                if (psr_iir & EDP_PSR_PRE_ENTRY(shift)) {
                         dev_priv->psr.last_entry_attempt = time_ns;
                         DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
                                       transcoder_name(cpu_transcoder));
                 }
 
-                if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
+                if (psr_iir & EDP_PSR_POST_EXIT(shift)) {
                         dev_priv->psr.last_exit = time_ns;
                         DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
                                       transcoder_name(cpu_transcoder));
@@ -294,7 +317,8 @@ static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
                 psr_vsc.sdp_header.HB3 = 0x8;
         }
 
-        intel_dig_port->write_infoframe(&intel_dig_port->base.base, crtc_state,
+        intel_dig_port->write_infoframe(&intel_dig_port->base,
+                                        crtc_state,
                                         DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));
 }
 
@@ -553,11 +577,31 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
         dev_priv->psr.active = true;
 }
 
+static i915_reg_t gen9_chicken_trans_reg(struct drm_i915_private *dev_priv,
+                                         enum transcoder cpu_transcoder)
+{
+        static const i915_reg_t regs[] = {
+                [TRANSCODER_A] = CHICKEN_TRANS_A,
+                [TRANSCODER_B] = CHICKEN_TRANS_B,
+                [TRANSCODER_C] = CHICKEN_TRANS_C,
+                [TRANSCODER_EDP] = CHICKEN_TRANS_EDP,
+        };
+
+        WARN_ON(INTEL_GEN(dev_priv) < 9);
+
+        if (WARN_ON(cpu_transcoder >= ARRAY_SIZE(regs) ||
+                    !regs[cpu_transcoder].reg))
+                cpu_transcoder = TRANSCODER_A;
+
+        return regs[cpu_transcoder];
+}
+
 static void intel_psr_enable_source(struct intel_dp *intel_dp,
                                     const struct intel_crtc_state *crtc_state)
 {
         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+        u32 mask;
 
         /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
          * use hardcoded values PSR AUX transactions
@@ -566,37 +610,34 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
                 hsw_psr_setup_aux(intel_dp);
 
         if (dev_priv->psr.psr2_enabled) {
-                u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
+                i915_reg_t reg = gen9_chicken_trans_reg(dev_priv,
+                                                        cpu_transcoder);
+                u32 chicken = I915_READ(reg);
 
-                if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
+                if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
                         chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
                                    | PSR2_ADD_VERTICAL_LINE_COUNT);
 
                 else
                         chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
-                I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
-
-                I915_WRITE(EDP_PSR_DEBUG,
-                           EDP_PSR_DEBUG_MASK_MEMUP |
-                           EDP_PSR_DEBUG_MASK_HPD |
-                           EDP_PSR_DEBUG_MASK_LPSP |
-                           EDP_PSR_DEBUG_MASK_MAX_SLEEP |
-                           EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
-        } else {
-                /*
-                 * Per Spec: Avoid continuous PSR exit by masking MEMUP
-                 * and HPD. also mask LPSP to avoid dependency on other
-                 * drivers that might block runtime_pm besides
-                 * preventing  other hw tracking issues now we can rely
-                 * on frontbuffer tracking.
-                 */
-                I915_WRITE(EDP_PSR_DEBUG,
-                           EDP_PSR_DEBUG_MASK_MEMUP |
-                           EDP_PSR_DEBUG_MASK_HPD |
-                           EDP_PSR_DEBUG_MASK_LPSP |
-                           EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
-                           EDP_PSR_DEBUG_MASK_MAX_SLEEP);
+                I915_WRITE(reg, chicken);
         }
+
+        /*
+         * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
+         * mask LPSP to avoid dependency on other drivers that might block
+         * runtime_pm besides preventing  other hw tracking issues now we
+         * can rely on frontbuffer tracking.
+         */
+        mask = EDP_PSR_DEBUG_MASK_MEMUP |
+               EDP_PSR_DEBUG_MASK_HPD |
+               EDP_PSR_DEBUG_MASK_LPSP |
+               EDP_PSR_DEBUG_MASK_MAX_SLEEP;
+
+        if (INTEL_GEN(dev_priv) < 11)
+                mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
+
+        I915_WRITE(EDP_PSR_DEBUG, mask);
 }
 
 static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
@@ -656,49 +697,34 @@ unlock:
         mutex_unlock(&dev_priv->psr.lock);
 }
 
-static void
-intel_psr_disable_source(struct intel_dp *intel_dp)
+static void intel_psr_exit(struct drm_i915_private *dev_priv)
 {
-        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
-        if (dev_priv->psr.active) {
-                i915_reg_t psr_status;
-                u32 psr_status_mask;
-
-                if (dev_priv->psr.psr2_enabled) {
-                        psr_status = EDP_PSR2_STATUS;
-                        psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
-
-                        I915_WRITE(EDP_PSR2_CTL,
-                                   I915_READ(EDP_PSR2_CTL) &
-                                   ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
-
-                } else {
-                        psr_status = EDP_PSR_STATUS;
-                        psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
-
-                        I915_WRITE(EDP_PSR_CTL,
-                                   I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
-                }
+        u32 val;
 
-                /* Wait till PSR is idle */
-                if (intel_wait_for_register(dev_priv,
-                                            psr_status, psr_status_mask, 0,
-                                            2000))
-                        DRM_ERROR("Timed out waiting for PSR Idle State\n");
+        if (!dev_priv->psr.active) {
+                if (INTEL_GEN(dev_priv) >= 9)
+                        WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
+                WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
+                return;
+        }
 
-                dev_priv->psr.active = false;
+        if (dev_priv->psr.psr2_enabled) {
+                val = I915_READ(EDP_PSR2_CTL);
+                WARN_ON(!(val & EDP_PSR2_ENABLE));
+                I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
         } else {
-                if (dev_priv->psr.psr2_enabled)
-                        WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
-                else
-                        WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
+                val = I915_READ(EDP_PSR_CTL);
+                WARN_ON(!(val & EDP_PSR_ENABLE));
+                I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
         }
+        dev_priv->psr.active = false;
 }
 
 static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 {
         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+        i915_reg_t psr_status;
+        u32 psr_status_mask;
 
         lockdep_assert_held(&dev_priv->psr.lock);
 
@@ -707,7 +733,21 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 
         DRM_DEBUG_KMS("Disabling PSR%s\n",
                       dev_priv->psr.psr2_enabled ? "2" : "1");
-        intel_psr_disable_source(intel_dp);
+
+        intel_psr_exit(dev_priv);
+
+        if (dev_priv->psr.psr2_enabled) {
+                psr_status = EDP_PSR2_STATUS;
+                psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
+        } else {
+                psr_status = EDP_PSR_STATUS;
+                psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
+        }
+
+        /* Wait till PSR is idle */
+        if (intel_wait_for_register(dev_priv, psr_status, psr_status_mask, 0,
+                                    2000))
+                DRM_ERROR("Timed out waiting PSR idle state\n");
 
         /* Disable PSR on Sink */
         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
@@ -925,25 +965,6 @@ unlock:
         mutex_unlock(&dev_priv->psr.lock);
 }
 
-static void intel_psr_exit(struct drm_i915_private *dev_priv)
-{
-        u32 val;
-
-        if (!dev_priv->psr.active)
-                return;
-
-        if (dev_priv->psr.psr2_enabled) {
-                val = I915_READ(EDP_PSR2_CTL);
-                WARN_ON(!(val & EDP_PSR2_ENABLE));
-                I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
-        } else {
-                val = I915_READ(EDP_PSR_CTL);
-                WARN_ON(!(val & EDP_PSR_ENABLE));
-                I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
-        }
-        dev_priv->psr.active = false;
-}
-
 /**
  * intel_psr_invalidate - Invalidade PSR
  * @dev_priv: i915 device
@@ -1026,20 +1047,16 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
 
         /* By definition flush = invalidate + flush */
         if (frontbuffer_bits) {
-                if (dev_priv->psr.psr2_enabled) {
-                        intel_psr_exit(dev_priv);
-                } else {
-                        /*
-                         * Display WA #0884: all
-                         * This documented WA for bxt can be safely applied
-                         * broadly so we can force HW tracking to exit PSR
-                         * instead of disabling and re-enabling.
-                         * Workaround tells us to write 0 to CUR_SURFLIVE_A,
-                         * but it makes more sense write to the current active
-                         * pipe.
-                         */
-                        I915_WRITE(CURSURFLIVE(pipe), 0);
-                }
+                /*
+                 * Display WA #0884: all
+                 * This documented WA for bxt can be safely applied
+                 * broadly so we can force HW tracking to exit PSR
+                 * instead of disabling and re-enabling.
+                 * Workaround tells us to write 0 to CUR_SURFLIVE_A,
+                 * but it makes more sense write to the current active
+                 * pipe.
+                 */
+                I915_WRITE(CURSURFLIVE(pipe), 0);
         }
 
         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
@@ -1065,12 +1082,9 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
         if (!dev_priv->psr.sink_support)
                 return;
 
-        if (i915_modparams.enable_psr == -1) {
-                i915_modparams.enable_psr = dev_priv->vbt.psr.enable;
-
-                /* Per platform default: all disabled. */
-                i915_modparams.enable_psr = 0;
-        }
+        if (i915_modparams.enable_psr == -1)
+                if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
+                        i915_modparams.enable_psr = 0;
 
         /* Set link_standby x link_off defaults */
         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
@@ -1130,8 +1144,6 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
                 intel_psr_disable_locked(intel_dp);
         /* clear status register */
         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
-
-        /* TODO: handle PSR2 errors */
 exit:
         mutex_unlock(&psr->lock);
 }