1 files changed, 15 insertions, 6 deletions

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index eb5fa05cf476..b28c29f20e75 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1783,16 +1783,20 @@ static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
                                    const struct intel_plane_state *pstate,
                                    uint32_t mem_value)
 {
-        int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
+        /*
+         * We treat the cursor plane as always-on for the purposes of watermark
+         * calculation.  Until we have two-stage watermark programming merged,
+         * this is necessary to avoid flickering.
+         */
+        int cpp = 4;
+        int width = pstate->visible ? pstate->base.crtc_w : 64;
 
-        if (!cstate->base.active || !pstate->visible)
+        if (!cstate->base.active)
                 return 0;
 
         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
                               cstate->base.adjusted_mode.crtc_htotal,
-                              drm_rect_width(&pstate->dst),
-                              bpp,
-                              mem_value);
+                              width, cpp, mem_value);
 }
 
 /* Only for WM_LP. */
@@ -2825,7 +2829,10 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
         memset(ddb, 0, sizeof(*ddb));
 
         for_each_pipe(dev_priv, pipe) {
-                if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
+                enum intel_display_power_domain power_domain;
+
+                power_domain = POWER_DOMAIN_PIPE(pipe);
+                if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
                         continue;
 
                 for_each_plane(dev_priv, pipe, plane) {
@@ -2837,6 +2844,8 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
                 val = I915_READ(CUR_BUF_CFG(pipe));
                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
                                            val);
+
+                intel_display_power_put(dev_priv, power_domain);
         }
 }