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path: root/drivers/gpu/drm/i915/intel_hdmi.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_hdmi.c')
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c213
1 files changed, 124 insertions, 89 deletions
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index d7234e03fdb0..e2c6a2b3e8f2 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -148,14 +148,13 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
148 } 148 }
149} 149}
150 150
151static void g4x_write_infoframe(struct drm_encoder *encoder, 151static void g4x_write_infoframe(struct intel_encoder *encoder,
152 const struct intel_crtc_state *crtc_state, 152 const struct intel_crtc_state *crtc_state,
153 unsigned int type, 153 unsigned int type,
154 const void *frame, ssize_t len) 154 const void *frame, ssize_t len)
155{ 155{
156 const u32 *data = frame; 156 const u32 *data = frame;
157 struct drm_device *dev = encoder->dev; 157 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
158 struct drm_i915_private *dev_priv = to_i915(dev);
159 u32 val = I915_READ(VIDEO_DIP_CTL); 158 u32 val = I915_READ(VIDEO_DIP_CTL);
160 int i; 159 int i;
161 160
@@ -186,31 +185,29 @@ static void g4x_write_infoframe(struct drm_encoder *encoder,
186 POSTING_READ(VIDEO_DIP_CTL); 185 POSTING_READ(VIDEO_DIP_CTL);
187} 186}
188 187
189static bool g4x_infoframe_enabled(struct drm_encoder *encoder, 188static bool g4x_infoframe_enabled(struct intel_encoder *encoder,
190 const struct intel_crtc_state *pipe_config) 189 const struct intel_crtc_state *pipe_config)
191{ 190{
192 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 191 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
193 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
194 u32 val = I915_READ(VIDEO_DIP_CTL); 192 u32 val = I915_READ(VIDEO_DIP_CTL);
195 193
196 if ((val & VIDEO_DIP_ENABLE) == 0) 194 if ((val & VIDEO_DIP_ENABLE) == 0)
197 return false; 195 return false;
198 196
199 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port)) 197 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
200 return false; 198 return false;
201 199
202 return val & (VIDEO_DIP_ENABLE_AVI | 200 return val & (VIDEO_DIP_ENABLE_AVI |
203 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 201 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
204} 202}
205 203
206static void ibx_write_infoframe(struct drm_encoder *encoder, 204static void ibx_write_infoframe(struct intel_encoder *encoder,
207 const struct intel_crtc_state *crtc_state, 205 const struct intel_crtc_state *crtc_state,
208 unsigned int type, 206 unsigned int type,
209 const void *frame, ssize_t len) 207 const void *frame, ssize_t len)
210{ 208{
211 const u32 *data = frame; 209 const u32 *data = frame;
212 struct drm_device *dev = encoder->dev; 210 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
213 struct drm_i915_private *dev_priv = to_i915(dev);
214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
215 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 212 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
216 u32 val = I915_READ(reg); 213 u32 val = I915_READ(reg);
@@ -243,11 +240,10 @@ static void ibx_write_infoframe(struct drm_encoder *encoder,
243 POSTING_READ(reg); 240 POSTING_READ(reg);
244} 241}
245 242
246static bool ibx_infoframe_enabled(struct drm_encoder *encoder, 243static bool ibx_infoframe_enabled(struct intel_encoder *encoder,
247 const struct intel_crtc_state *pipe_config) 244 const struct intel_crtc_state *pipe_config)
248{ 245{
249 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 246 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
250 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
251 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 247 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
252 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 248 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
253 u32 val = I915_READ(reg); 249 u32 val = I915_READ(reg);
@@ -255,7 +251,7 @@ static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
255 if ((val & VIDEO_DIP_ENABLE) == 0) 251 if ((val & VIDEO_DIP_ENABLE) == 0)
256 return false; 252 return false;
257 253
258 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port)) 254 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
259 return false; 255 return false;
260 256
261 return val & (VIDEO_DIP_ENABLE_AVI | 257 return val & (VIDEO_DIP_ENABLE_AVI |
@@ -263,14 +259,13 @@ static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
263 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 259 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
264} 260}
265 261
266static void cpt_write_infoframe(struct drm_encoder *encoder, 262static void cpt_write_infoframe(struct intel_encoder *encoder,
267 const struct intel_crtc_state *crtc_state, 263 const struct intel_crtc_state *crtc_state,
268 unsigned int type, 264 unsigned int type,
269 const void *frame, ssize_t len) 265 const void *frame, ssize_t len)
270{ 266{
271 const u32 *data = frame; 267 const u32 *data = frame;
272 struct drm_device *dev = encoder->dev; 268 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
273 struct drm_i915_private *dev_priv = to_i915(dev);
274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
275 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 270 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
276 u32 val = I915_READ(reg); 271 u32 val = I915_READ(reg);
@@ -306,10 +301,10 @@ static void cpt_write_infoframe(struct drm_encoder *encoder,
306 POSTING_READ(reg); 301 POSTING_READ(reg);
307} 302}
308 303
309static bool cpt_infoframe_enabled(struct drm_encoder *encoder, 304static bool cpt_infoframe_enabled(struct intel_encoder *encoder,
310 const struct intel_crtc_state *pipe_config) 305 const struct intel_crtc_state *pipe_config)
311{ 306{
312 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 307 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
313 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 308 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
314 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); 309 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
315 310
@@ -321,14 +316,13 @@ static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
321 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 316 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
322} 317}
323 318
324static void vlv_write_infoframe(struct drm_encoder *encoder, 319static void vlv_write_infoframe(struct intel_encoder *encoder,
325 const struct intel_crtc_state *crtc_state, 320 const struct intel_crtc_state *crtc_state,
326 unsigned int type, 321 unsigned int type,
327 const void *frame, ssize_t len) 322 const void *frame, ssize_t len)
328{ 323{
329 const u32 *data = frame; 324 const u32 *data = frame;
330 struct drm_device *dev = encoder->dev; 325 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
331 struct drm_i915_private *dev_priv = to_i915(dev);
332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
333 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 327 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
334 u32 val = I915_READ(reg); 328 u32 val = I915_READ(reg);
@@ -361,18 +355,17 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,
361 POSTING_READ(reg); 355 POSTING_READ(reg);
362} 356}
363 357
364static bool vlv_infoframe_enabled(struct drm_encoder *encoder, 358static bool vlv_infoframe_enabled(struct intel_encoder *encoder,
365 const struct intel_crtc_state *pipe_config) 359 const struct intel_crtc_state *pipe_config)
366{ 360{
367 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 361 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
368 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
369 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 362 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
370 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); 363 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
371 364
372 if ((val & VIDEO_DIP_ENABLE) == 0) 365 if ((val & VIDEO_DIP_ENABLE) == 0)
373 return false; 366 return false;
374 367
375 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port)) 368 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
376 return false; 369 return false;
377 370
378 return val & (VIDEO_DIP_ENABLE_AVI | 371 return val & (VIDEO_DIP_ENABLE_AVI |
@@ -380,14 +373,13 @@ static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
380 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 373 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
381} 374}
382 375
383static void hsw_write_infoframe(struct drm_encoder *encoder, 376static void hsw_write_infoframe(struct intel_encoder *encoder,
384 const struct intel_crtc_state *crtc_state, 377 const struct intel_crtc_state *crtc_state,
385 unsigned int type, 378 unsigned int type,
386 const void *frame, ssize_t len) 379 const void *frame, ssize_t len)
387{ 380{
388 const u32 *data = frame; 381 const u32 *data = frame;
389 struct drm_device *dev = encoder->dev; 382 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
390 struct drm_i915_private *dev_priv = to_i915(dev);
391 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 383 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
392 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 384 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
393 int data_size = type == DP_SDP_VSC ? 385 int data_size = type == DP_SDP_VSC ?
@@ -415,10 +407,10 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
415 POSTING_READ(ctl_reg); 407 POSTING_READ(ctl_reg);
416} 408}
417 409
418static bool hsw_infoframe_enabled(struct drm_encoder *encoder, 410static bool hsw_infoframe_enabled(struct intel_encoder *encoder,
419 const struct intel_crtc_state *pipe_config) 411 const struct intel_crtc_state *pipe_config)
420{ 412{
421 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 413 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
422 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 414 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
423 415
424 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 416 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
@@ -443,11 +435,11 @@ static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
443 * trick them by giving an offset into the buffer and moving back the header 435 * trick them by giving an offset into the buffer and moving back the header
444 * bytes by one. 436 * bytes by one.
445 */ 437 */
446static void intel_write_infoframe(struct drm_encoder *encoder, 438static void intel_write_infoframe(struct intel_encoder *encoder,
447 const struct intel_crtc_state *crtc_state, 439 const struct intel_crtc_state *crtc_state,
448 union hdmi_infoframe *frame) 440 union hdmi_infoframe *frame)
449{ 441{
450 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 442 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
451 u8 buffer[VIDEO_DIP_DATA_SIZE]; 443 u8 buffer[VIDEO_DIP_DATA_SIZE];
452 ssize_t len; 444 ssize_t len;
453 445
@@ -457,20 +449,20 @@ static void intel_write_infoframe(struct drm_encoder *encoder,
457 return; 449 return;
458 450
459 /* Insert the 'hole' (see big comment above) at position 3 */ 451 /* Insert the 'hole' (see big comment above) at position 3 */
460 buffer[0] = buffer[1]; 452 memmove(&buffer[0], &buffer[1], 3);
461 buffer[1] = buffer[2];
462 buffer[2] = buffer[3];
463 buffer[3] = 0; 453 buffer[3] = 0;
464 len++; 454 len++;
465 455
466 intel_dig_port->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len); 456 intel_dig_port->write_infoframe(encoder,
457 crtc_state,
458 frame->any.type, buffer, len);
467} 459}
468 460
469static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, 461static void intel_hdmi_set_avi_infoframe(struct intel_encoder *encoder,
470 const struct intel_crtc_state *crtc_state, 462 const struct intel_crtc_state *crtc_state,
471 const struct drm_connector_state *conn_state) 463 const struct drm_connector_state *conn_state)
472{ 464{
473 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 465 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
474 const struct drm_display_mode *adjusted_mode = 466 const struct drm_display_mode *adjusted_mode =
475 &crtc_state->base.adjusted_mode; 467 &crtc_state->base.adjusted_mode;
476 struct drm_connector *connector = &intel_hdmi->attached_connector->base; 468 struct drm_connector *connector = &intel_hdmi->attached_connector->base;
@@ -487,8 +479,10 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
487 return; 479 return;
488 } 480 }
489 481
490 if (crtc_state->ycbcr420) 482 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
491 frame.avi.colorspace = HDMI_COLORSPACE_YUV420; 483 frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
484 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
485 frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
492 else 486 else
493 frame.avi.colorspace = HDMI_COLORSPACE_RGB; 487 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
494 488
@@ -503,10 +497,11 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
503 conn_state); 497 conn_state);
504 498
505 /* TODO: handle pixel repetition for YCBCR420 outputs */ 499 /* TODO: handle pixel repetition for YCBCR420 outputs */
506 intel_write_infoframe(encoder, crtc_state, &frame); 500 intel_write_infoframe(encoder, crtc_state,
501 &frame);
507} 502}
508 503
509static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder, 504static void intel_hdmi_set_spd_infoframe(struct intel_encoder *encoder,
510 const struct intel_crtc_state *crtc_state) 505 const struct intel_crtc_state *crtc_state)
511{ 506{
512 union hdmi_infoframe frame; 507 union hdmi_infoframe frame;
@@ -520,11 +515,12 @@ static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder,
520 515
521 frame.spd.sdi = HDMI_SPD_SDI_PC; 516 frame.spd.sdi = HDMI_SPD_SDI_PC;
522 517
523 intel_write_infoframe(encoder, crtc_state, &frame); 518 intel_write_infoframe(encoder, crtc_state,
519 &frame);
524} 520}
525 521
526static void 522static void
527intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, 523intel_hdmi_set_hdmi_infoframe(struct intel_encoder *encoder,
528 const struct intel_crtc_state *crtc_state, 524 const struct intel_crtc_state *crtc_state,
529 const struct drm_connector_state *conn_state) 525 const struct drm_connector_state *conn_state)
530{ 526{
@@ -537,20 +533,21 @@ intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
537 if (ret < 0) 533 if (ret < 0)
538 return; 534 return;
539 535
540 intel_write_infoframe(encoder, crtc_state, &frame); 536 intel_write_infoframe(encoder, crtc_state,
537 &frame);
541} 538}
542 539
543static void g4x_set_infoframes(struct drm_encoder *encoder, 540static void g4x_set_infoframes(struct intel_encoder *encoder,
544 bool enable, 541 bool enable,
545 const struct intel_crtc_state *crtc_state, 542 const struct intel_crtc_state *crtc_state,
546 const struct drm_connector_state *conn_state) 543 const struct drm_connector_state *conn_state)
547{ 544{
548 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 545 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
549 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 546 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
550 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 547 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
551 i915_reg_t reg = VIDEO_DIP_CTL; 548 i915_reg_t reg = VIDEO_DIP_CTL;
552 u32 val = I915_READ(reg); 549 u32 val = I915_READ(reg);
553 u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port); 550 u32 port = VIDEO_DIP_PORT(encoder->port);
554 551
555 assert_hdmi_port_disabled(intel_hdmi); 552 assert_hdmi_port_disabled(intel_hdmi);
556 553
@@ -658,11 +655,11 @@ static bool gcp_default_phase_possible(int pipe_bpp,
658 mode->crtc_htotal/2 % pixels_per_group == 0); 655 mode->crtc_htotal/2 % pixels_per_group == 0);
659} 656}
660 657
661static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder, 658static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
662 const struct intel_crtc_state *crtc_state, 659 const struct intel_crtc_state *crtc_state,
663 const struct drm_connector_state *conn_state) 660 const struct drm_connector_state *conn_state)
664{ 661{
665 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 662 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
666 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 663 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
667 i915_reg_t reg; 664 i915_reg_t reg;
668 u32 val = 0; 665 u32 val = 0;
@@ -690,18 +687,18 @@ static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder,
690 return val != 0; 687 return val != 0;
691} 688}
692 689
693static void ibx_set_infoframes(struct drm_encoder *encoder, 690static void ibx_set_infoframes(struct intel_encoder *encoder,
694 bool enable, 691 bool enable,
695 const struct intel_crtc_state *crtc_state, 692 const struct intel_crtc_state *crtc_state,
696 const struct drm_connector_state *conn_state) 693 const struct drm_connector_state *conn_state)
697{ 694{
698 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 695 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
700 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 697 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
701 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 698 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
702 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 699 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
703 u32 val = I915_READ(reg); 700 u32 val = I915_READ(reg);
704 u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port); 701 u32 port = VIDEO_DIP_PORT(encoder->port);
705 702
706 assert_hdmi_port_disabled(intel_hdmi); 703 assert_hdmi_port_disabled(intel_hdmi);
707 704
@@ -743,14 +740,14 @@ static void ibx_set_infoframes(struct drm_encoder *encoder,
743 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state); 740 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
744} 741}
745 742
746static void cpt_set_infoframes(struct drm_encoder *encoder, 743static void cpt_set_infoframes(struct intel_encoder *encoder,
747 bool enable, 744 bool enable,
748 const struct intel_crtc_state *crtc_state, 745 const struct intel_crtc_state *crtc_state,
749 const struct drm_connector_state *conn_state) 746 const struct drm_connector_state *conn_state)
750{ 747{
751 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 748 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
753 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 750 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
754 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 751 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
755 u32 val = I915_READ(reg); 752 u32 val = I915_READ(reg);
756 753
@@ -786,18 +783,17 @@ static void cpt_set_infoframes(struct drm_encoder *encoder,
786 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state); 783 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
787} 784}
788 785
789static void vlv_set_infoframes(struct drm_encoder *encoder, 786static void vlv_set_infoframes(struct intel_encoder *encoder,
790 bool enable, 787 bool enable,
791 const struct intel_crtc_state *crtc_state, 788 const struct intel_crtc_state *crtc_state,
792 const struct drm_connector_state *conn_state) 789 const struct drm_connector_state *conn_state)
793{ 790{
794 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 791 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
795 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
797 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 793 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
798 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 794 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
799 u32 val = I915_READ(reg); 795 u32 val = I915_READ(reg);
800 u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port); 796 u32 port = VIDEO_DIP_PORT(encoder->port);
801 797
802 assert_hdmi_port_disabled(intel_hdmi); 798 assert_hdmi_port_disabled(intel_hdmi);
803 799
@@ -839,12 +835,12 @@ static void vlv_set_infoframes(struct drm_encoder *encoder,
839 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state); 835 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
840} 836}
841 837
842static void hsw_set_infoframes(struct drm_encoder *encoder, 838static void hsw_set_infoframes(struct intel_encoder *encoder,
843 bool enable, 839 bool enable,
844 const struct intel_crtc_state *crtc_state, 840 const struct intel_crtc_state *crtc_state,
845 const struct drm_connector_state *conn_state) 841 const struct drm_connector_state *conn_state)
846{ 842{
847 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 843 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
848 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); 844 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
849 u32 val = I915_READ(reg); 845 u32 val = I915_READ(reg);
850 846
@@ -966,13 +962,13 @@ int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
966 ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an, 962 ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
967 DRM_HDCP_AN_LEN); 963 DRM_HDCP_AN_LEN);
968 if (ret) { 964 if (ret) {
969 DRM_ERROR("Write An over DDC failed (%d)\n", ret); 965 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
970 return ret; 966 return ret;
971 } 967 }
972 968
973 ret = intel_gmbus_output_aksv(adapter); 969 ret = intel_gmbus_output_aksv(adapter);
974 if (ret < 0) { 970 if (ret < 0) {
975 DRM_ERROR("Failed to output aksv (%d)\n", ret); 971 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
976 return ret; 972 return ret;
977 } 973 }
978 return 0; 974 return 0;
@@ -985,7 +981,7 @@ static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
985 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv, 981 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
986 DRM_HDCP_KSV_LEN); 982 DRM_HDCP_KSV_LEN);
987 if (ret) 983 if (ret)
988 DRM_ERROR("Read Bksv over DDC failed (%d)\n", ret); 984 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
989 return ret; 985 return ret;
990} 986}
991 987
@@ -997,7 +993,7 @@ int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
997 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS, 993 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
998 bstatus, DRM_HDCP_BSTATUS_LEN); 994 bstatus, DRM_HDCP_BSTATUS_LEN);
999 if (ret) 995 if (ret)
1000 DRM_ERROR("Read bstatus over DDC failed (%d)\n", ret); 996 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
1001 return ret; 997 return ret;
1002} 998}
1003 999
@@ -1010,7 +1006,7 @@ int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1010 1006
1011 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1007 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1012 if (ret) { 1008 if (ret) {
1013 DRM_ERROR("Read bcaps over DDC failed (%d)\n", ret); 1009 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1014 return ret; 1010 return ret;
1015 } 1011 }
1016 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1012 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
@@ -1025,7 +1021,7 @@ int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1025 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME, 1021 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1026 ri_prime, DRM_HDCP_RI_LEN); 1022 ri_prime, DRM_HDCP_RI_LEN);
1027 if (ret) 1023 if (ret)
1028 DRM_ERROR("Read Ri' over DDC failed (%d)\n", ret); 1024 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
1029 return ret; 1025 return ret;
1030} 1026}
1031 1027
@@ -1038,7 +1034,7 @@ int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1038 1034
1039 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1035 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1040 if (ret) { 1036 if (ret) {
1041 DRM_ERROR("Read bcaps over DDC failed (%d)\n", ret); 1037 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1042 return ret; 1038 return ret;
1043 } 1039 }
1044 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1040 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
@@ -1053,7 +1049,7 @@ int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1053 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO, 1049 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1054 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1050 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1055 if (ret) { 1051 if (ret) {
1056 DRM_ERROR("Read ksv fifo over DDC failed (%d)\n", ret); 1052 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
1057 return ret; 1053 return ret;
1058 } 1054 }
1059 return 0; 1055 return 0;
@@ -1071,7 +1067,7 @@ int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1071 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i), 1067 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1072 part, DRM_HDCP_V_PRIME_PART_LEN); 1068 part, DRM_HDCP_V_PRIME_PART_LEN);
1073 if (ret) 1069 if (ret)
1074 DRM_ERROR("Read V'[%d] over DDC failed (%d)\n", i, ret); 1070 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
1075 return ret; 1071 return ret;
1076} 1072}
1077 1073
@@ -1218,7 +1214,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
1218 if (tmp & HDMI_MODE_SELECT_HDMI) 1214 if (tmp & HDMI_MODE_SELECT_HDMI)
1219 pipe_config->has_hdmi_sink = true; 1215 pipe_config->has_hdmi_sink = true;
1220 1216
1221 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config)) 1217 if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
1222 pipe_config->has_infoframe = true; 1218 pipe_config->has_infoframe = true;
1223 1219
1224 if (tmp & SDVO_AUDIO_ENABLE) 1220 if (tmp & SDVO_AUDIO_ENABLE)
@@ -1439,7 +1435,8 @@ static void intel_disable_hdmi(struct intel_encoder *encoder,
1439 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1435 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1440 } 1436 }
1441 1437
1442 intel_dig_port->set_infoframes(&encoder->base, false, 1438 intel_dig_port->set_infoframes(encoder,
1439 false,
1443 old_crtc_state, old_conn_state); 1440 old_crtc_state, old_conn_state);
1444 1441
1445 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 1442 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
@@ -1598,6 +1595,8 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1598 struct drm_atomic_state *state = crtc_state->base.state; 1595 struct drm_atomic_state *state = crtc_state->base.state;
1599 struct drm_connector_state *connector_state; 1596 struct drm_connector_state *connector_state;
1600 struct drm_connector *connector; 1597 struct drm_connector *connector;
1598 const struct drm_display_mode *adjusted_mode =
1599 &crtc_state->base.adjusted_mode;
1601 int i; 1600 int i;
1602 1601
1603 if (HAS_GMCH_DISPLAY(dev_priv)) 1602 if (HAS_GMCH_DISPLAY(dev_priv))
@@ -1625,7 +1624,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1625 if (connector_state->crtc != crtc_state->base.crtc) 1624 if (connector_state->crtc != crtc_state->base.crtc)
1626 continue; 1625 continue;
1627 1626
1628 if (crtc_state->ycbcr420) { 1627 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
1629 const struct drm_hdmi_info *hdmi = &info->hdmi; 1628 const struct drm_hdmi_info *hdmi = &info->hdmi;
1630 1629
1631 if (bpc == 12 && !(hdmi->y420_dc_modes & 1630 if (bpc == 12 && !(hdmi->y420_dc_modes &
@@ -1646,7 +1645,14 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1646 1645
1647 /* Display WA #1139: glk */ 1646 /* Display WA #1139: glk */
1648 if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && 1647 if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1649 crtc_state->base.adjusted_mode.htotal > 5460) 1648 adjusted_mode->htotal > 5460)
1649 return false;
1650
1651 /* Display Wa_1405510057:icl */
1652 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1653 bpc == 10 && IS_ICELAKE(dev_priv) &&
1654 (adjusted_mode->crtc_hblank_end -
1655 adjusted_mode->crtc_hblank_start) % 8 == 2)
1650 return false; 1656 return false;
1651 1657
1652 return true; 1658 return true;
@@ -1670,7 +1676,7 @@ intel_hdmi_ycbcr420_config(struct drm_connector *connector,
1670 *clock_12bpc /= 2; 1676 *clock_12bpc /= 2;
1671 *clock_10bpc /= 2; 1677 *clock_10bpc /= 2;
1672 *clock_8bpc /= 2; 1678 *clock_8bpc /= 2;
1673 config->ycbcr420 = true; 1679 config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1674 1680
1675 /* YCBCR 420 output conversion needs a scaler */ 1681 /* YCBCR 420 output conversion needs a scaler */
1676 if (skl_update_scaler_crtc(config)) { 1682 if (skl_update_scaler_crtc(config)) {
@@ -1704,6 +1710,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1704 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 1710 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1705 return false; 1711 return false;
1706 1712
1713 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1707 pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink; 1714 pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
1708 1715
1709 if (pipe_config->has_hdmi_sink) 1716 if (pipe_config->has_hdmi_sink)
@@ -1974,7 +1981,7 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1974 1981
1975 intel_hdmi_prepare(encoder, pipe_config); 1982 intel_hdmi_prepare(encoder, pipe_config);
1976 1983
1977 intel_dig_port->set_infoframes(&encoder->base, 1984 intel_dig_port->set_infoframes(encoder,
1978 pipe_config->has_infoframe, 1985 pipe_config->has_infoframe,
1979 pipe_config, conn_state); 1986 pipe_config, conn_state);
1980} 1987}
@@ -1992,7 +1999,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1992 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, 1999 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1993 0x2b247878); 2000 0x2b247878);
1994 2001
1995 dport->set_infoframes(&encoder->base, 2002 dport->set_infoframes(encoder,
1996 pipe_config->has_infoframe, 2003 pipe_config->has_infoframe,
1997 pipe_config, conn_state); 2004 pipe_config, conn_state);
1998 2005
@@ -2063,7 +2070,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2063 /* Use 800mV-0dB */ 2070 /* Use 800mV-0dB */
2064 chv_set_phy_signal_level(encoder, 128, 102, false); 2071 chv_set_phy_signal_level(encoder, 128, 102, false);
2065 2072
2066 dport->set_infoframes(&encoder->base, 2073 dport->set_infoframes(encoder,
2067 pipe_config->has_infoframe, 2074 pipe_config->has_infoframe,
2068 pipe_config, conn_state); 2075 pipe_config, conn_state);
2069 2076
@@ -2075,13 +2082,26 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2075 chv_phy_release_cl2_override(encoder); 2082 chv_phy_release_cl2_override(encoder);
2076} 2083}
2077 2084
2085static int
2086intel_hdmi_connector_register(struct drm_connector *connector)
2087{
2088 int ret;
2089
2090 ret = intel_connector_register(connector);
2091 if (ret)
2092 return ret;
2093
2094 i915_debugfs_connector_add(connector);
2095
2096 return ret;
2097}
2098
2078static void intel_hdmi_destroy(struct drm_connector *connector) 2099static void intel_hdmi_destroy(struct drm_connector *connector)
2079{ 2100{
2080 if (intel_attached_hdmi(connector)->cec_notifier) 2101 if (intel_attached_hdmi(connector)->cec_notifier)
2081 cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier); 2102 cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier);
2082 kfree(to_intel_connector(connector)->detect_edid); 2103
2083 drm_connector_cleanup(connector); 2104 intel_connector_destroy(connector);
2084 kfree(connector);
2085} 2105}
2086 2106
2087static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2107static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
@@ -2090,7 +2110,7 @@ static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2090 .fill_modes = drm_helper_probe_single_connector_modes, 2110 .fill_modes = drm_helper_probe_single_connector_modes,
2091 .atomic_get_property = intel_digital_connector_atomic_get_property, 2111 .atomic_get_property = intel_digital_connector_atomic_get_property,
2092 .atomic_set_property = intel_digital_connector_atomic_set_property, 2112 .atomic_set_property = intel_digital_connector_atomic_set_property,
2093 .late_register = intel_connector_register, 2113 .late_register = intel_hdmi_connector_register,
2094 .early_unregister = intel_connector_unregister, 2114 .early_unregister = intel_connector_unregister,
2095 .destroy = intel_hdmi_destroy, 2115 .destroy = intel_hdmi_destroy,
2096 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2116 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
@@ -2110,11 +2130,16 @@ static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2110static void 2130static void
2111intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2131intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2112{ 2132{
2133 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2134
2113 intel_attach_force_audio_property(connector); 2135 intel_attach_force_audio_property(connector);
2114 intel_attach_broadcast_rgb_property(connector); 2136 intel_attach_broadcast_rgb_property(connector);
2115 intel_attach_aspect_ratio_property(connector); 2137 intel_attach_aspect_ratio_property(connector);
2116 drm_connector_attach_content_type_property(connector); 2138 drm_connector_attach_content_type_property(connector);
2117 connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 2139 connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2140
2141 if (!HAS_GMCH_DISPLAY(dev_priv))
2142 drm_connector_attach_max_bpc_property(connector, 8, 12);
2118} 2143}
2119 2144
2120/* 2145/*
@@ -2325,9 +2350,18 @@ void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
2325 intel_dig_port->set_infoframes = g4x_set_infoframes; 2350 intel_dig_port->set_infoframes = g4x_set_infoframes;
2326 intel_dig_port->infoframe_enabled = g4x_infoframe_enabled; 2351 intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
2327 } else if (HAS_DDI(dev_priv)) { 2352 } else if (HAS_DDI(dev_priv)) {
2328 intel_dig_port->write_infoframe = hsw_write_infoframe; 2353 if (intel_dig_port->lspcon.active) {
2329 intel_dig_port->set_infoframes = hsw_set_infoframes; 2354 intel_dig_port->write_infoframe =
2330 intel_dig_port->infoframe_enabled = hsw_infoframe_enabled; 2355 lspcon_write_infoframe;
2356 intel_dig_port->set_infoframes = lspcon_set_infoframes;
2357 intel_dig_port->infoframe_enabled =
2358 lspcon_infoframe_enabled;
2359 } else {
2360 intel_dig_port->set_infoframes = hsw_set_infoframes;
2361 intel_dig_port->infoframe_enabled =
2362 hsw_infoframe_enabled;
2363 intel_dig_port->write_infoframe = hsw_write_infoframe;
2364 }
2331 } else if (HAS_PCH_IBX(dev_priv)) { 2365 } else if (HAS_PCH_IBX(dev_priv)) {
2332 intel_dig_port->write_infoframe = ibx_write_infoframe; 2366 intel_dig_port->write_infoframe = ibx_write_infoframe;
2333 intel_dig_port->set_infoframes = ibx_set_infoframes; 2367 intel_dig_port->set_infoframes = ibx_set_infoframes;
@@ -2486,5 +2520,6 @@ void intel_hdmi_init(struct drm_i915_private *dev_priv,
2486 2520
2487 intel_infoframe_init(intel_dig_port); 2521 intel_infoframe_init(intel_dig_port);
2488 2522
2523 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
2489 intel_hdmi_init_connector(intel_dig_port, intel_connector); 2524 intel_hdmi_init_connector(intel_dig_port, intel_connector);
2490} 2525}