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path: root/drivers/gpu/drm/i915/intel_dp.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c831
1 files changed, 417 insertions, 414 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 13f9b56a9ce7..7699f9b7b2d2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -45,6 +45,17 @@
45 45
46#define DP_DPRX_ESI_LEN 14 46#define DP_DPRX_ESI_LEN 14
47 47
48/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
49#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
50
51/* DP DSC throughput values used for slice count calculations KPixels/s */
52#define DP_DSC_PEAK_PIXEL_RATE 2720000
53#define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
54#define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
55
56/* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
57#define DP_DSC_FEC_OVERHEAD_FACTOR 976
58
48/* Compliance test status bits */ 59/* Compliance test status bits */
49#define INTEL_DP_RESOLUTION_SHIFT_MASK 0 60#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
50#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) 61#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
@@ -93,6 +104,14 @@ static const struct dp_link_dpll chv_dpll[] = {
93 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, 104 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
94}; 105};
95 106
107/* Constants for DP DSC configurations */
108static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
109
110/* With Single pipe configuration, HW is capable of supporting maximum
111 * of 4 slices per line.
112 */
113static const u8 valid_dsc_slicecount[] = {1, 2, 4};
114
96/** 115/**
97 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) 116 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
98 * @intel_dp: DP struct 117 * @intel_dp: DP struct
@@ -222,138 +241,6 @@ intel_dp_link_required(int pixel_clock, int bpp)
222 return DIV_ROUND_UP(pixel_clock * bpp, 8); 241 return DIV_ROUND_UP(pixel_clock * bpp, 8);
223} 242}
224 243
225void icl_program_mg_dp_mode(struct intel_dp *intel_dp)
226{
227 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
228 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
229 enum port port = intel_dig_port->base.port;
230 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
231 u32 ln0, ln1, lane_info;
232
233 if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
234 return;
235
236 ln0 = I915_READ(MG_DP_MODE(port, 0));
237 ln1 = I915_READ(MG_DP_MODE(port, 1));
238
239 switch (intel_dig_port->tc_type) {
240 case TC_PORT_TYPEC:
241 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
242 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
243
244 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
245 DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
246 DP_LANE_ASSIGNMENT_SHIFT(tc_port);
247
248 switch (lane_info) {
249 case 0x1:
250 case 0x4:
251 break;
252 case 0x2:
253 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
254 break;
255 case 0x3:
256 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
257 MG_DP_MODE_CFG_DP_X2_MODE;
258 break;
259 case 0x8:
260 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
261 break;
262 case 0xC:
263 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
264 MG_DP_MODE_CFG_DP_X2_MODE;
265 break;
266 case 0xF:
267 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
268 MG_DP_MODE_CFG_DP_X2_MODE;
269 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
270 MG_DP_MODE_CFG_DP_X2_MODE;
271 break;
272 default:
273 MISSING_CASE(lane_info);
274 }
275 break;
276
277 case TC_PORT_LEGACY:
278 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
279 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
280 break;
281
282 default:
283 MISSING_CASE(intel_dig_port->tc_type);
284 return;
285 }
286
287 I915_WRITE(MG_DP_MODE(port, 0), ln0);
288 I915_WRITE(MG_DP_MODE(port, 1), ln1);
289}
290
291void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
292{
293 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
294 enum port port = dig_port->base.port;
295 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
296 i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
297 u32 val;
298 int i;
299
300 if (tc_port == PORT_TC_NONE)
301 return;
302
303 for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
304 val = I915_READ(mg_regs[i]);
305 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
306 MG_DP_MODE_CFG_TRPWR_GATING |
307 MG_DP_MODE_CFG_CLNPWR_GATING |
308 MG_DP_MODE_CFG_DIGPWR_GATING |
309 MG_DP_MODE_CFG_GAONPWR_GATING;
310 I915_WRITE(mg_regs[i], val);
311 }
312
313 val = I915_READ(MG_MISC_SUS0(tc_port));
314 val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
315 MG_MISC_SUS0_CFG_TR2PWR_GATING |
316 MG_MISC_SUS0_CFG_CL2PWR_GATING |
317 MG_MISC_SUS0_CFG_GAONPWR_GATING |
318 MG_MISC_SUS0_CFG_TRPWR_GATING |
319 MG_MISC_SUS0_CFG_CL1PWR_GATING |
320 MG_MISC_SUS0_CFG_DGPWR_GATING;
321 I915_WRITE(MG_MISC_SUS0(tc_port), val);
322}
323
324void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
325{
326 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
327 enum port port = dig_port->base.port;
328 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
329 i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
330 u32 val;
331 int i;
332
333 if (tc_port == PORT_TC_NONE)
334 return;
335
336 for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
337 val = I915_READ(mg_regs[i]);
338 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
339 MG_DP_MODE_CFG_TRPWR_GATING |
340 MG_DP_MODE_CFG_CLNPWR_GATING |
341 MG_DP_MODE_CFG_DIGPWR_GATING |
342 MG_DP_MODE_CFG_GAONPWR_GATING);
343 I915_WRITE(mg_regs[i], val);
344 }
345
346 val = I915_READ(MG_MISC_SUS0(tc_port));
347 val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
348 MG_MISC_SUS0_CFG_TR2PWR_GATING |
349 MG_MISC_SUS0_CFG_CL2PWR_GATING |
350 MG_MISC_SUS0_CFG_GAONPWR_GATING |
351 MG_MISC_SUS0_CFG_TRPWR_GATING |
352 MG_MISC_SUS0_CFG_CL1PWR_GATING |
353 MG_MISC_SUS0_CFG_DGPWR_GATING);
354 I915_WRITE(MG_MISC_SUS0(tc_port), val);
355}
356
357int 244int
358intel_dp_max_data_rate(int max_link_clock, int max_lanes) 245intel_dp_max_data_rate(int max_link_clock, int max_lanes)
359{ 246{
@@ -455,7 +342,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
455 if (INTEL_GEN(dev_priv) >= 10) { 342 if (INTEL_GEN(dev_priv) >= 10) {
456 source_rates = cnl_rates; 343 source_rates = cnl_rates;
457 size = ARRAY_SIZE(cnl_rates); 344 size = ARRAY_SIZE(cnl_rates);
458 if (INTEL_GEN(dev_priv) == 10) 345 if (IS_GEN10(dev_priv))
459 max_rate = cnl_max_source_rate(intel_dp); 346 max_rate = cnl_max_source_rate(intel_dp);
460 else 347 else
461 max_rate = icl_max_source_rate(intel_dp); 348 max_rate = icl_max_source_rate(intel_dp);
@@ -616,9 +503,12 @@ intel_dp_mode_valid(struct drm_connector *connector,
616 struct intel_dp *intel_dp = intel_attached_dp(connector); 503 struct intel_dp *intel_dp = intel_attached_dp(connector);
617 struct intel_connector *intel_connector = to_intel_connector(connector); 504 struct intel_connector *intel_connector = to_intel_connector(connector);
618 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 505 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
506 struct drm_i915_private *dev_priv = to_i915(connector->dev);
619 int target_clock = mode->clock; 507 int target_clock = mode->clock;
620 int max_rate, mode_rate, max_lanes, max_link_clock; 508 int max_rate, mode_rate, max_lanes, max_link_clock;
621 int max_dotclk; 509 int max_dotclk;
510 u16 dsc_max_output_bpp = 0;
511 u8 dsc_slice_count = 0;
622 512
623 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 513 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
624 return MODE_NO_DBLESCAN; 514 return MODE_NO_DBLESCAN;
@@ -641,7 +531,33 @@ intel_dp_mode_valid(struct drm_connector *connector,
641 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 531 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
642 mode_rate = intel_dp_link_required(target_clock, 18); 532 mode_rate = intel_dp_link_required(target_clock, 18);
643 533
644 if (mode_rate > max_rate || target_clock > max_dotclk) 534 /*
535 * Output bpp is stored in 6.4 format so right shift by 4 to get the
536 * integer value since we support only integer values of bpp.
537 */
538 if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
539 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
540 if (intel_dp_is_edp(intel_dp)) {
541 dsc_max_output_bpp =
542 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
543 dsc_slice_count =
544 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
545 true);
546 } else {
547 dsc_max_output_bpp =
548 intel_dp_dsc_get_output_bpp(max_link_clock,
549 max_lanes,
550 target_clock,
551 mode->hdisplay) >> 4;
552 dsc_slice_count =
553 intel_dp_dsc_get_slice_count(intel_dp,
554 target_clock,
555 mode->hdisplay);
556 }
557 }
558
559 if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
560 target_clock > max_dotclk)
645 return MODE_CLOCK_HIGH; 561 return MODE_CLOCK_HIGH;
646 562
647 if (mode->clock < 10000) 563 if (mode->clock < 10000)
@@ -690,7 +606,8 @@ static void pps_lock(struct intel_dp *intel_dp)
690 * See intel_power_sequencer_reset() why we need 606 * See intel_power_sequencer_reset() why we need
691 * a power domain reference here. 607 * a power domain reference here.
692 */ 608 */
693 intel_display_power_get(dev_priv, intel_dp->aux_power_domain); 609 intel_display_power_get(dev_priv,
610 intel_aux_power_domain(dp_to_dig_port(intel_dp)));
694 611
695 mutex_lock(&dev_priv->pps_mutex); 612 mutex_lock(&dev_priv->pps_mutex);
696} 613}
@@ -701,7 +618,8 @@ static void pps_unlock(struct intel_dp *intel_dp)
701 618
702 mutex_unlock(&dev_priv->pps_mutex); 619 mutex_unlock(&dev_priv->pps_mutex);
703 620
704 intel_display_power_put(dev_priv, intel_dp->aux_power_domain); 621 intel_display_power_put(dev_priv,
622 intel_aux_power_domain(dp_to_dig_port(intel_dp)));
705} 623}
706 624
707static void 625static void
@@ -1156,6 +1074,7 @@ static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1156static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 1074static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1157{ 1075{
1158 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1076 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1077 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1159 1078
1160 if (index) 1079 if (index)
1161 return 0; 1080 return 0;
@@ -1165,7 +1084,7 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1165 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and 1084 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
1166 * divide by 2000 and use that 1085 * divide by 2000 and use that
1167 */ 1086 */
1168 if (intel_dp->aux_ch == AUX_CH_A) 1087 if (dig_port->aux_ch == AUX_CH_A)
1169 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000); 1088 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1170 else 1089 else
1171 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); 1090 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
@@ -1174,8 +1093,9 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1174static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 1093static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1175{ 1094{
1176 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1095 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1096 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1177 1097
1178 if (intel_dp->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) { 1098 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1179 /* Workaround for non-ULT HSW */ 1099 /* Workaround for non-ULT HSW */
1180 switch (index) { 1100 switch (index) {
1181 case 0: return 63; 1101 case 0: return 63;
@@ -1503,80 +1423,12 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1503 return ret; 1423 return ret;
1504} 1424}
1505 1425
1506static enum aux_ch intel_aux_ch(struct intel_dp *intel_dp)
1507{
1508 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1509 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1510 enum port port = encoder->port;
1511 const struct ddi_vbt_port_info *info =
1512 &dev_priv->vbt.ddi_port_info[port];
1513 enum aux_ch aux_ch;
1514
1515 if (!info->alternate_aux_channel) {
1516 aux_ch = (enum aux_ch) port;
1517
1518 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1519 aux_ch_name(aux_ch), port_name(port));
1520 return aux_ch;
1521 }
1522
1523 switch (info->alternate_aux_channel) {
1524 case DP_AUX_A:
1525 aux_ch = AUX_CH_A;
1526 break;
1527 case DP_AUX_B:
1528 aux_ch = AUX_CH_B;
1529 break;
1530 case DP_AUX_C:
1531 aux_ch = AUX_CH_C;
1532 break;
1533 case DP_AUX_D:
1534 aux_ch = AUX_CH_D;
1535 break;
1536 case DP_AUX_E:
1537 aux_ch = AUX_CH_E;
1538 break;
1539 case DP_AUX_F:
1540 aux_ch = AUX_CH_F;
1541 break;
1542 default:
1543 MISSING_CASE(info->alternate_aux_channel);
1544 aux_ch = AUX_CH_A;
1545 break;
1546 }
1547
1548 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1549 aux_ch_name(aux_ch), port_name(port));
1550
1551 return aux_ch;
1552}
1553
1554static enum intel_display_power_domain
1555intel_aux_power_domain(struct intel_dp *intel_dp)
1556{
1557 switch (intel_dp->aux_ch) {
1558 case AUX_CH_A:
1559 return POWER_DOMAIN_AUX_A;
1560 case AUX_CH_B:
1561 return POWER_DOMAIN_AUX_B;
1562 case AUX_CH_C:
1563 return POWER_DOMAIN_AUX_C;
1564 case AUX_CH_D:
1565 return POWER_DOMAIN_AUX_D;
1566 case AUX_CH_E:
1567 return POWER_DOMAIN_AUX_E;
1568 case AUX_CH_F:
1569 return POWER_DOMAIN_AUX_F;
1570 default:
1571 MISSING_CASE(intel_dp->aux_ch);
1572 return POWER_DOMAIN_AUX_A;
1573 }
1574}
1575 1426
1576static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) 1427static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1577{ 1428{
1578 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1429 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1579 enum aux_ch aux_ch = intel_dp->aux_ch; 1430 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1431 enum aux_ch aux_ch = dig_port->aux_ch;
1580 1432
1581 switch (aux_ch) { 1433 switch (aux_ch) {
1582 case AUX_CH_B: 1434 case AUX_CH_B:
@@ -1592,7 +1444,8 @@ static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1592static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) 1444static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1593{ 1445{
1594 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1446 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1595 enum aux_ch aux_ch = intel_dp->aux_ch; 1447 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1448 enum aux_ch aux_ch = dig_port->aux_ch;
1596 1449
1597 switch (aux_ch) { 1450 switch (aux_ch) {
1598 case AUX_CH_B: 1451 case AUX_CH_B:
@@ -1608,7 +1461,8 @@ static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1608static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) 1461static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1609{ 1462{
1610 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1463 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1611 enum aux_ch aux_ch = intel_dp->aux_ch; 1464 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1465 enum aux_ch aux_ch = dig_port->aux_ch;
1612 1466
1613 switch (aux_ch) { 1467 switch (aux_ch) {
1614 case AUX_CH_A: 1468 case AUX_CH_A:
@@ -1626,7 +1480,8 @@ static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1626static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) 1480static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1627{ 1481{
1628 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1482 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1629 enum aux_ch aux_ch = intel_dp->aux_ch; 1483 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1484 enum aux_ch aux_ch = dig_port->aux_ch;
1630 1485
1631 switch (aux_ch) { 1486 switch (aux_ch) {
1632 case AUX_CH_A: 1487 case AUX_CH_A:
@@ -1644,7 +1499,8 @@ static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1644static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) 1499static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1645{ 1500{
1646 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1501 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1647 enum aux_ch aux_ch = intel_dp->aux_ch; 1502 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1503 enum aux_ch aux_ch = dig_port->aux_ch;
1648 1504
1649 switch (aux_ch) { 1505 switch (aux_ch) {
1650 case AUX_CH_A: 1506 case AUX_CH_A:
@@ -1663,7 +1519,8 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1663static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) 1519static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1664{ 1520{
1665 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1521 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1666 enum aux_ch aux_ch = intel_dp->aux_ch; 1522 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1523 enum aux_ch aux_ch = dig_port->aux_ch;
1667 1524
1668 switch (aux_ch) { 1525 switch (aux_ch) {
1669 case AUX_CH_A: 1526 case AUX_CH_A:
@@ -1689,10 +1546,8 @@ static void
1689intel_dp_aux_init(struct intel_dp *intel_dp) 1546intel_dp_aux_init(struct intel_dp *intel_dp)
1690{ 1547{
1691 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1548 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1692 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1549 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1693 1550 struct intel_encoder *encoder = &dig_port->base;
1694 intel_dp->aux_ch = intel_aux_ch(intel_dp);
1695 intel_dp->aux_power_domain = intel_aux_power_domain(intel_dp);
1696 1551
1697 if (INTEL_GEN(dev_priv) >= 9) { 1552 if (INTEL_GEN(dev_priv) >= 9) {
1698 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; 1553 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
@@ -1951,6 +1806,42 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1951 return false; 1806 return false;
1952} 1807}
1953 1808
1809/* Optimize link config in order: max bpp, min lanes, min clock */
1810static bool
1811intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
1812 struct intel_crtc_state *pipe_config,
1813 const struct link_config_limits *limits)
1814{
1815 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1816 int bpp, clock, lane_count;
1817 int mode_rate, link_clock, link_avail;
1818
1819 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1820 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1821 bpp);
1822
1823 for (lane_count = limits->min_lane_count;
1824 lane_count <= limits->max_lane_count;
1825 lane_count <<= 1) {
1826 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1827 link_clock = intel_dp->common_rates[clock];
1828 link_avail = intel_dp_max_data_rate(link_clock,
1829 lane_count);
1830
1831 if (mode_rate <= link_avail) {
1832 pipe_config->lane_count = lane_count;
1833 pipe_config->pipe_bpp = bpp;
1834 pipe_config->port_clock = link_clock;
1835
1836 return true;
1837 }
1838 }
1839 }
1840 }
1841
1842 return false;
1843}
1844
1954static bool 1845static bool
1955intel_dp_compute_link_config(struct intel_encoder *encoder, 1846intel_dp_compute_link_config(struct intel_encoder *encoder,
1956 struct intel_crtc_state *pipe_config) 1847 struct intel_crtc_state *pipe_config)
@@ -1975,13 +1866,15 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
1975 limits.min_bpp = 6 * 3; 1866 limits.min_bpp = 6 * 3;
1976 limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config); 1867 limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1977 1868
1978 if (intel_dp_is_edp(intel_dp)) { 1869 if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
1979 /* 1870 /*
1980 * Use the maximum clock and number of lanes the eDP panel 1871 * Use the maximum clock and number of lanes the eDP panel
1981 * advertizes being capable of. The panels are generally 1872 * advertizes being capable of. The eDP 1.3 and earlier panels
1982 * designed to support only a single clock and lane 1873 * are generally designed to support only a single clock and
1983 * configuration, and typically these values correspond to the 1874 * lane configuration, and typically these values correspond to
1984 * native resolution of the panel. 1875 * the native resolution of the panel. With eDP 1.4 rate select
1876 * and DSC, this is decreasingly the case, and we need to be
1877 * able to select less than maximum link config.
1985 */ 1878 */
1986 limits.min_lane_count = limits.max_lane_count; 1879 limits.min_lane_count = limits.max_lane_count;
1987 limits.min_clock = limits.max_clock; 1880 limits.min_clock = limits.max_clock;
@@ -1995,12 +1888,25 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
1995 intel_dp->common_rates[limits.max_clock], 1888 intel_dp->common_rates[limits.max_clock],
1996 limits.max_bpp, adjusted_mode->crtc_clock); 1889 limits.max_bpp, adjusted_mode->crtc_clock);
1997 1890
1998 /* 1891 if (intel_dp_is_edp(intel_dp)) {
1999 * Optimize for slow and wide. This is the place to add alternative 1892 /*
2000 * optimization policy. 1893 * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
2001 */ 1894 * section A.1: "It is recommended that the minimum number of
2002 if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits)) 1895 * lanes be used, using the minimum link rate allowed for that
2003 return false; 1896 * lane configuration."
1897 *
1898 * Note that we use the max clock and lane count for eDP 1.3 and
1899 * earlier, and fast vs. wide is irrelevant.
1900 */
1901 if (!intel_dp_compute_link_config_fast(intel_dp, pipe_config,
1902 &limits))
1903 return false;
1904 } else {
1905 /* Optimize for slow and wide. */
1906 if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config,
1907 &limits))
1908 return false;
1909 }
2004 1910
2005 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n", 1911 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2006 pipe_config->lane_count, pipe_config->port_clock, 1912 pipe_config->lane_count, pipe_config->port_clock,
@@ -2023,6 +1929,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
2023 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1929 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2024 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1930 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2025 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1931 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1932 struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
2026 enum port port = encoder->port; 1933 enum port port = encoder->port;
2027 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 1934 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2028 struct intel_connector *intel_connector = intel_dp->attached_connector; 1935 struct intel_connector *intel_connector = intel_dp->attached_connector;
@@ -2034,6 +1941,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
2034 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) 1941 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2035 pipe_config->has_pch_encoder = true; 1942 pipe_config->has_pch_encoder = true;
2036 1943
1944 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1945 if (lspcon->active)
1946 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
1947
2037 pipe_config->has_drrs = false; 1948 pipe_config->has_drrs = false;
2038 if (IS_G4X(dev_priv) || port == PORT_A) 1949 if (IS_G4X(dev_priv) || port == PORT_A)
2039 pipe_config->has_audio = false; 1950 pipe_config->has_audio = false;
@@ -2338,7 +2249,8 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2338 if (edp_have_panel_vdd(intel_dp)) 2249 if (edp_have_panel_vdd(intel_dp))
2339 return need_to_disable; 2250 return need_to_disable;
2340 2251
2341 intel_display_power_get(dev_priv, intel_dp->aux_power_domain); 2252 intel_display_power_get(dev_priv,
2253 intel_aux_power_domain(intel_dig_port));
2342 2254
2343 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", 2255 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2344 port_name(intel_dig_port->base.port)); 2256 port_name(intel_dig_port->base.port));
@@ -2424,7 +2336,8 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2424 if ((pp & PANEL_POWER_ON) == 0) 2336 if ((pp & PANEL_POWER_ON) == 0)
2425 intel_dp->panel_power_off_time = ktime_get_boottime(); 2337 intel_dp->panel_power_off_time = ktime_get_boottime();
2426 2338
2427 intel_display_power_put(dev_priv, intel_dp->aux_power_domain); 2339 intel_display_power_put(dev_priv,
2340 intel_aux_power_domain(intel_dig_port));
2428} 2341}
2429 2342
2430static void edp_panel_vdd_work(struct work_struct *__work) 2343static void edp_panel_vdd_work(struct work_struct *__work)
@@ -2537,6 +2450,7 @@ void intel_edp_panel_on(struct intel_dp *intel_dp)
2537static void edp_panel_off(struct intel_dp *intel_dp) 2450static void edp_panel_off(struct intel_dp *intel_dp)
2538{ 2451{
2539 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2452 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2453 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2540 u32 pp; 2454 u32 pp;
2541 i915_reg_t pp_ctrl_reg; 2455 i915_reg_t pp_ctrl_reg;
2542 2456
@@ -2546,10 +2460,10 @@ static void edp_panel_off(struct intel_dp *intel_dp)
2546 return; 2460 return;
2547 2461
2548 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", 2462 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2549 port_name(dp_to_dig_port(intel_dp)->base.port)); 2463 port_name(dig_port->base.port));
2550 2464
2551 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", 2465 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2552 port_name(dp_to_dig_port(intel_dp)->base.port)); 2466 port_name(dig_port->base.port));
2553 2467
2554 pp = ironlake_get_pp_control(intel_dp); 2468 pp = ironlake_get_pp_control(intel_dp);
2555 /* We need to switch off panel power _and_ force vdd, for otherwise some 2469 /* We need to switch off panel power _and_ force vdd, for otherwise some
@@ -2568,7 +2482,7 @@ static void edp_panel_off(struct intel_dp *intel_dp)
2568 intel_dp->panel_power_off_time = ktime_get_boottime(); 2482 intel_dp->panel_power_off_time = ktime_get_boottime();
2569 2483
2570 /* We got a reference when we enabled the VDD. */ 2484 /* We got a reference when we enabled the VDD. */
2571 intel_display_power_put(dev_priv, intel_dp->aux_power_domain); 2485 intel_display_power_put(dev_priv, intel_aux_power_domain(dig_port));
2572} 2486}
2573 2487
2574void intel_edp_panel_off(struct intel_dp *intel_dp) 2488void intel_edp_panel_off(struct intel_dp *intel_dp)
@@ -3900,6 +3814,41 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
3900 return intel_dp->dpcd[DP_DPCD_REV] != 0; 3814 return intel_dp->dpcd[DP_DPCD_REV] != 0;
3901} 3815}
3902 3816
3817static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
3818{
3819 /*
3820 * Clear the cached register set to avoid using stale values
3821 * for the sinks that do not support DSC.
3822 */
3823 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
3824
3825 /* Clear fec_capable to avoid using stale values */
3826 intel_dp->fec_capable = 0;
3827
3828 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
3829 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
3830 intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3831 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
3832 intel_dp->dsc_dpcd,
3833 sizeof(intel_dp->dsc_dpcd)) < 0)
3834 DRM_ERROR("Failed to read DPCD register 0x%x\n",
3835 DP_DSC_SUPPORT);
3836
3837 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
3838 (int)sizeof(intel_dp->dsc_dpcd),
3839 intel_dp->dsc_dpcd);
3840 /* FEC is supported only on DP 1.4 */
3841 if (!intel_dp_is_edp(intel_dp)) {
3842 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
3843 &intel_dp->fec_capable) < 0)
3844 DRM_ERROR("Failed to read FEC DPCD register\n");
3845
3846 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n",
3847 intel_dp->fec_capable);
3848 }
3849 }
3850}
3851
3903static bool 3852static bool
3904intel_edp_init_dpcd(struct intel_dp *intel_dp) 3853intel_edp_init_dpcd(struct intel_dp *intel_dp)
3905{ 3854{
@@ -3976,6 +3925,10 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
3976 3925
3977 intel_dp_set_common_rates(intel_dp); 3926 intel_dp_set_common_rates(intel_dp);
3978 3927
3928 /* Read the eDP DSC DPCD registers */
3929 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3930 intel_dp_get_dsc_sink_cap(intel_dp);
3931
3979 return true; 3932 return true;
3980} 3933}
3981 3934
@@ -4029,16 +3982,10 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
4029} 3982}
4030 3983
4031static bool 3984static bool
4032intel_dp_can_mst(struct intel_dp *intel_dp) 3985intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4033{ 3986{
4034 u8 mstm_cap; 3987 u8 mstm_cap;
4035 3988
4036 if (!i915_modparams.enable_dp_mst)
4037 return false;
4038
4039 if (!intel_dp->can_mst)
4040 return false;
4041
4042 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) 3989 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4043 return false; 3990 return false;
4044 3991
@@ -4048,34 +3995,36 @@ intel_dp_can_mst(struct intel_dp *intel_dp)
4048 return mstm_cap & DP_MST_CAP; 3995 return mstm_cap & DP_MST_CAP;
4049} 3996}
4050 3997
3998static bool
3999intel_dp_can_mst(struct intel_dp *intel_dp)
4000{
4001 return i915_modparams.enable_dp_mst &&
4002 intel_dp->can_mst &&
4003 intel_dp_sink_can_mst(intel_dp);
4004}
4005
4051static void 4006static void
4052intel_dp_configure_mst(struct intel_dp *intel_dp) 4007intel_dp_configure_mst(struct intel_dp *intel_dp)
4053{ 4008{
4054 if (!i915_modparams.enable_dp_mst) 4009 struct intel_encoder *encoder =
4055 return; 4010 &dp_to_dig_port(intel_dp)->base;
4011 bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4012
4013 DRM_DEBUG_KMS("MST support? port %c: %s, sink: %s, modparam: %s\n",
4014 port_name(encoder->port), yesno(intel_dp->can_mst),
4015 yesno(sink_can_mst), yesno(i915_modparams.enable_dp_mst));
4056 4016
4057 if (!intel_dp->can_mst) 4017 if (!intel_dp->can_mst)
4058 return; 4018 return;
4059 4019
4060 intel_dp->is_mst = intel_dp_can_mst(intel_dp); 4020 intel_dp->is_mst = sink_can_mst &&
4061 4021 i915_modparams.enable_dp_mst;
4062 if (intel_dp->is_mst)
4063 DRM_DEBUG_KMS("Sink is MST capable\n");
4064 else
4065 DRM_DEBUG_KMS("Sink is not MST capable\n");
4066 4022
4067 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 4023 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4068 intel_dp->is_mst); 4024 intel_dp->is_mst);
4069} 4025}
4070 4026
4071static bool 4027static bool
4072intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4073{
4074 return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
4075 sink_irq_vector) == 1;
4076}
4077
4078static bool
4079intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) 4028intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4080{ 4029{
4081 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, 4030 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
@@ -4083,6 +4032,91 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4083 DP_DPRX_ESI_LEN; 4032 DP_DPRX_ESI_LEN;
4084} 4033}
4085 4034
4035u16 intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
4036 int mode_clock, int mode_hdisplay)
4037{
4038 u16 bits_per_pixel, max_bpp_small_joiner_ram;
4039 int i;
4040
4041 /*
4042 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
4043 * (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
4044 * FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
4045 * for MST -> TimeSlotsPerMTP has to be calculated
4046 */
4047 bits_per_pixel = (link_clock * lane_count * 8 *
4048 DP_DSC_FEC_OVERHEAD_FACTOR) /
4049 mode_clock;
4050
4051 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
4052 max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
4053 mode_hdisplay;
4054
4055 /*
4056 * Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
4057 * check, output bpp from small joiner RAM check)
4058 */
4059 bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
4060
4061 /* Error out if the max bpp is less than smallest allowed valid bpp */
4062 if (bits_per_pixel < valid_dsc_bpp[0]) {
4063 DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel);
4064 return 0;
4065 }
4066
4067 /* Find the nearest match in the array of known BPPs from VESA */
4068 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
4069 if (bits_per_pixel < valid_dsc_bpp[i + 1])
4070 break;
4071 }
4072 bits_per_pixel = valid_dsc_bpp[i];
4073
4074 /*
4075 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
4076 * fractional part is 0
4077 */
4078 return bits_per_pixel << 4;
4079}
4080
4081u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
4082 int mode_clock,
4083 int mode_hdisplay)
4084{
4085 u8 min_slice_count, i;
4086 int max_slice_width;
4087
4088 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
4089 min_slice_count = DIV_ROUND_UP(mode_clock,
4090 DP_DSC_MAX_ENC_THROUGHPUT_0);
4091 else
4092 min_slice_count = DIV_ROUND_UP(mode_clock,
4093 DP_DSC_MAX_ENC_THROUGHPUT_1);
4094
4095 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
4096 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
4097 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
4098 max_slice_width);
4099 return 0;
4100 }
4101 /* Also take into account max slice width */
4102 min_slice_count = min_t(uint8_t, min_slice_count,
4103 DIV_ROUND_UP(mode_hdisplay,
4104 max_slice_width));
4105
4106 /* Find the closest match to the valid slice count values */
4107 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
4108 if (valid_dsc_slicecount[i] >
4109 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
4110 false))
4111 break;
4112 if (min_slice_count <= valid_dsc_slicecount[i])
4113 return valid_dsc_slicecount[i];
4114 }
4115
4116 DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
4117 return 0;
4118}
4119
4086static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) 4120static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4087{ 4121{
4088 int status = 0; 4122 int status = 0;
@@ -4403,7 +4437,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
4403 4437
4404 /* Suppress underruns caused by re-training */ 4438 /* Suppress underruns caused by re-training */
4405 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 4439 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4406 if (crtc->config->has_pch_encoder) 4440 if (crtc_state->has_pch_encoder)
4407 intel_set_pch_fifo_underrun_reporting(dev_priv, 4441 intel_set_pch_fifo_underrun_reporting(dev_priv,
4408 intel_crtc_pch_transcoder(crtc), false); 4442 intel_crtc_pch_transcoder(crtc), false);
4409 4443
@@ -4414,7 +4448,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
4414 intel_wait_for_vblank(dev_priv, crtc->pipe); 4448 intel_wait_for_vblank(dev_priv, crtc->pipe);
4415 4449
4416 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 4450 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4417 if (crtc->config->has_pch_encoder) 4451 if (crtc_state->has_pch_encoder)
4418 intel_set_pch_fifo_underrun_reporting(dev_priv, 4452 intel_set_pch_fifo_underrun_reporting(dev_priv,
4419 intel_crtc_pch_transcoder(crtc), true); 4453 intel_crtc_pch_transcoder(crtc), true);
4420 4454
@@ -4462,6 +4496,29 @@ static bool intel_dp_hotplug(struct intel_encoder *encoder,
4462 return changed; 4496 return changed;
4463} 4497}
4464 4498
4499static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
4500{
4501 u8 val;
4502
4503 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4504 return;
4505
4506 if (drm_dp_dpcd_readb(&intel_dp->aux,
4507 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4508 return;
4509
4510 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4511
4512 if (val & DP_AUTOMATED_TEST_REQUEST)
4513 intel_dp_handle_test_request(intel_dp);
4514
4515 if (val & DP_CP_IRQ)
4516 intel_hdcp_check_link(intel_dp->attached_connector);
4517
4518 if (val & DP_SINK_SPECIFIC_IRQ)
4519 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
4520}
4521
4465/* 4522/*
4466 * According to DP spec 4523 * According to DP spec
4467 * 5.1.2: 4524 * 5.1.2:
@@ -4479,7 +4536,6 @@ static bool
4479intel_dp_short_pulse(struct intel_dp *intel_dp) 4536intel_dp_short_pulse(struct intel_dp *intel_dp)
4480{ 4537{
4481 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 4538 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4482 u8 sink_irq_vector = 0;
4483 u8 old_sink_count = intel_dp->sink_count; 4539 u8 old_sink_count = intel_dp->sink_count;
4484 bool ret; 4540 bool ret;
4485 4541
@@ -4502,20 +4558,7 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
4502 return false; 4558 return false;
4503 } 4559 }
4504 4560
4505 /* Try to read the source of the interrupt */ 4561 intel_dp_check_service_irq(intel_dp);
4506 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4507 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4508 sink_irq_vector != 0) {
4509 /* Clear interrupt source */
4510 drm_dp_dpcd_writeb(&intel_dp->aux,
4511 DP_DEVICE_SERVICE_IRQ_VECTOR,
4512 sink_irq_vector);
4513
4514 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4515 intel_dp_handle_test_request(intel_dp);
4516 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4517 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4518 }
4519 4562
4520 /* Handle CEC interrupts, if any */ 4563 /* Handle CEC interrupts, if any */
4521 drm_dp_cec_irq(&intel_dp->aux); 4564 drm_dp_cec_irq(&intel_dp->aux);
@@ -4810,6 +4853,9 @@ static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
4810 type_str); 4853 type_str);
4811} 4854}
4812 4855
4856static void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
4857 struct intel_digital_port *dig_port);
4858
4813/* 4859/*
4814 * This function implements the first part of the Connect Flow described by our 4860 * This function implements the first part of the Connect Flow described by our
4815 * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading 4861 * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
@@ -4864,9 +4910,7 @@ static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
4864 if (dig_port->tc_type == TC_PORT_TYPEC && 4910 if (dig_port->tc_type == TC_PORT_TYPEC &&
4865 !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) { 4911 !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
4866 DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port); 4912 DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
4867 val = I915_READ(PORT_TX_DFLEXDPCSSS); 4913 icl_tc_phy_disconnect(dev_priv, dig_port);
4868 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
4869 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
4870 return false; 4914 return false;
4871 } 4915 }
4872 4916
@@ -4881,21 +4925,24 @@ static void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
4881 struct intel_digital_port *dig_port) 4925 struct intel_digital_port *dig_port)
4882{ 4926{
4883 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 4927 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
4884 u32 val;
4885 4928
4886 if (dig_port->tc_type != TC_PORT_LEGACY && 4929 if (dig_port->tc_type == TC_PORT_UNKNOWN)
4887 dig_port->tc_type != TC_PORT_TYPEC)
4888 return; 4930 return;
4889 4931
4890 /* 4932 /*
4891 * This function may be called many times in a row without an HPD event 4933 * TBT disconnection flow is read the live status, what was done in
4892 * in between, so try to avoid the write when we can. 4934 * caller.
4893 */ 4935 */
4894 val = I915_READ(PORT_TX_DFLEXDPCSSS); 4936 if (dig_port->tc_type == TC_PORT_TYPEC ||
4895 if (val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)) { 4937 dig_port->tc_type == TC_PORT_LEGACY) {
4938 u32 val;
4939
4940 val = I915_READ(PORT_TX_DFLEXDPCSSS);
4896 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port); 4941 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
4897 I915_WRITE(PORT_TX_DFLEXDPCSSS, val); 4942 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
4898 } 4943 }
4944
4945 dig_port->tc_type = TC_PORT_UNKNOWN;
4899} 4946}
4900 4947
4901/* 4948/*
@@ -4945,19 +4992,14 @@ static bool icl_digital_port_connected(struct intel_encoder *encoder)
4945 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4992 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4946 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 4993 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4947 4994
4948 switch (encoder->hpd_pin) { 4995 if (intel_port_is_combophy(dev_priv, encoder->port))
4949 case HPD_PORT_A:
4950 case HPD_PORT_B:
4951 return icl_combo_port_connected(dev_priv, dig_port); 4996 return icl_combo_port_connected(dev_priv, dig_port);
4952 case HPD_PORT_C: 4997 else if (intel_port_is_tc(dev_priv, encoder->port))
4953 case HPD_PORT_D:
4954 case HPD_PORT_E:
4955 case HPD_PORT_F:
4956 return icl_tc_port_connected(dev_priv, dig_port); 4998 return icl_tc_port_connected(dev_priv, dig_port);
4957 default: 4999 else
4958 MISSING_CASE(encoder->hpd_pin); 5000 MISSING_CASE(encoder->hpd_pin);
4959 return false; 5001
4960 } 5002 return false;
4961} 5003}
4962 5004
4963/* 5005/*
@@ -4982,20 +5024,23 @@ bool intel_digital_port_connected(struct intel_encoder *encoder)
4982 return g4x_digital_port_connected(encoder); 5024 return g4x_digital_port_connected(encoder);
4983 } 5025 }
4984 5026
4985 if (IS_GEN5(dev_priv)) 5027 if (INTEL_GEN(dev_priv) >= 11)
4986 return ilk_digital_port_connected(encoder); 5028 return icl_digital_port_connected(encoder);
4987 else if (IS_GEN6(dev_priv)) 5029 else if (IS_GEN10(dev_priv) || IS_GEN9_BC(dev_priv))
4988 return snb_digital_port_connected(encoder); 5030 return spt_digital_port_connected(encoder);
4989 else if (IS_GEN7(dev_priv))
4990 return ivb_digital_port_connected(encoder);
4991 else if (IS_GEN8(dev_priv))
4992 return bdw_digital_port_connected(encoder);
4993 else if (IS_GEN9_LP(dev_priv)) 5031 else if (IS_GEN9_LP(dev_priv))
4994 return bxt_digital_port_connected(encoder); 5032 return bxt_digital_port_connected(encoder);
4995 else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv)) 5033 else if (IS_GEN8(dev_priv))
4996 return spt_digital_port_connected(encoder); 5034 return bdw_digital_port_connected(encoder);
4997 else 5035 else if (IS_GEN7(dev_priv))
4998 return icl_digital_port_connected(encoder); 5036 return ivb_digital_port_connected(encoder);
5037 else if (IS_GEN6(dev_priv))
5038 return snb_digital_port_connected(encoder);
5039 else if (IS_GEN5(dev_priv))
5040 return ilk_digital_port_connected(encoder);
5041
5042 MISSING_CASE(INTEL_GEN(dev_priv));
5043 return false;
4999} 5044}
5000 5045
5001static struct edid * 5046static struct edid *
@@ -5042,28 +5087,35 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
5042} 5087}
5043 5088
5044static int 5089static int
5045intel_dp_long_pulse(struct intel_connector *connector, 5090intel_dp_detect(struct drm_connector *connector,
5046 struct drm_modeset_acquire_ctx *ctx) 5091 struct drm_modeset_acquire_ctx *ctx,
5092 bool force)
5047{ 5093{
5048 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 5094 struct drm_i915_private *dev_priv = to_i915(connector->dev);
5049 struct intel_dp *intel_dp = intel_attached_dp(&connector->base); 5095 struct intel_dp *intel_dp = intel_attached_dp(connector);
5096 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5097 struct intel_encoder *encoder = &dig_port->base;
5050 enum drm_connector_status status; 5098 enum drm_connector_status status;
5051 u8 sink_irq_vector = 0; 5099 enum intel_display_power_domain aux_domain =
5100 intel_aux_power_domain(dig_port);
5052 5101
5102 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5103 connector->base.id, connector->name);
5053 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 5104 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5054 5105
5055 intel_display_power_get(dev_priv, intel_dp->aux_power_domain); 5106 intel_display_power_get(dev_priv, aux_domain);
5056 5107
5057 /* Can't disconnect eDP */ 5108 /* Can't disconnect eDP */
5058 if (intel_dp_is_edp(intel_dp)) 5109 if (intel_dp_is_edp(intel_dp))
5059 status = edp_detect(intel_dp); 5110 status = edp_detect(intel_dp);
5060 else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) 5111 else if (intel_digital_port_connected(encoder))
5061 status = intel_dp_detect_dpcd(intel_dp); 5112 status = intel_dp_detect_dpcd(intel_dp);
5062 else 5113 else
5063 status = connector_status_disconnected; 5114 status = connector_status_disconnected;
5064 5115
5065 if (status == connector_status_disconnected) { 5116 if (status == connector_status_disconnected) {
5066 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); 5117 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5118 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5067 5119
5068 if (intel_dp->is_mst) { 5120 if (intel_dp->is_mst) {
5069 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", 5121 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
@@ -5089,6 +5141,10 @@ intel_dp_long_pulse(struct intel_connector *connector,
5089 5141
5090 intel_dp_print_rates(intel_dp); 5142 intel_dp_print_rates(intel_dp);
5091 5143
5144 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5145 if (INTEL_GEN(dev_priv) >= 11)
5146 intel_dp_get_dsc_sink_cap(intel_dp);
5147
5092 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 5148 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
5093 drm_dp_is_branch(intel_dp->dpcd)); 5149 drm_dp_is_branch(intel_dp->dpcd));
5094 5150
@@ -5109,9 +5165,13 @@ intel_dp_long_pulse(struct intel_connector *connector,
5109 * with an IRQ_HPD, so force a link status check. 5165 * with an IRQ_HPD, so force a link status check.
5110 */ 5166 */
5111 if (!intel_dp_is_edp(intel_dp)) { 5167 if (!intel_dp_is_edp(intel_dp)) {
5112 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 5168 int ret;
5113 5169
5114 intel_dp_retrain_link(encoder, ctx); 5170 ret = intel_dp_retrain_link(encoder, ctx);
5171 if (ret) {
5172 intel_display_power_put(dev_priv, aux_domain);
5173 return ret;
5174 }
5115 } 5175 }
5116 5176
5117 /* 5177 /*
@@ -5123,61 +5183,17 @@ intel_dp_long_pulse(struct intel_connector *connector,
5123 intel_dp->aux.i2c_defer_count = 0; 5183 intel_dp->aux.i2c_defer_count = 0;
5124 5184
5125 intel_dp_set_edid(intel_dp); 5185 intel_dp_set_edid(intel_dp);
5126 if (intel_dp_is_edp(intel_dp) || connector->detect_edid) 5186 if (intel_dp_is_edp(intel_dp) ||
5187 to_intel_connector(connector)->detect_edid)
5127 status = connector_status_connected; 5188 status = connector_status_connected;
5128 intel_dp->detect_done = true;
5129 5189
5130 /* Try to read the source of the interrupt */ 5190 intel_dp_check_service_irq(intel_dp);
5131 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
5132 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
5133 sink_irq_vector != 0) {
5134 /* Clear interrupt source */
5135 drm_dp_dpcd_writeb(&intel_dp->aux,
5136 DP_DEVICE_SERVICE_IRQ_VECTOR,
5137 sink_irq_vector);
5138
5139 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
5140 intel_dp_handle_test_request(intel_dp);
5141 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
5142 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
5143 }
5144 5191
5145out: 5192out:
5146 if (status != connector_status_connected && !intel_dp->is_mst) 5193 if (status != connector_status_connected && !intel_dp->is_mst)
5147 intel_dp_unset_edid(intel_dp); 5194 intel_dp_unset_edid(intel_dp);
5148 5195
5149 intel_display_power_put(dev_priv, intel_dp->aux_power_domain); 5196 intel_display_power_put(dev_priv, aux_domain);
5150 return status;
5151}
5152
5153static int
5154intel_dp_detect(struct drm_connector *connector,
5155 struct drm_modeset_acquire_ctx *ctx,
5156 bool force)
5157{
5158 struct intel_dp *intel_dp = intel_attached_dp(connector);
5159 int status = connector->status;
5160
5161 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5162 connector->base.id, connector->name);
5163
5164 /* If full detect is not performed yet, do a full detect */
5165 if (!intel_dp->detect_done) {
5166 struct drm_crtc *crtc;
5167 int ret;
5168
5169 crtc = connector->state->crtc;
5170 if (crtc) {
5171 ret = drm_modeset_lock(&crtc->mutex, ctx);
5172 if (ret)
5173 return ret;
5174 }
5175
5176 status = intel_dp_long_pulse(intel_dp->attached_connector, ctx);
5177 }
5178
5179 intel_dp->detect_done = false;
5180
5181 return status; 5197 return status;
5182} 5198}
5183 5199
@@ -5185,8 +5201,11 @@ static void
5185intel_dp_force(struct drm_connector *connector) 5201intel_dp_force(struct drm_connector *connector)
5186{ 5202{
5187 struct intel_dp *intel_dp = intel_attached_dp(connector); 5203 struct intel_dp *intel_dp = intel_attached_dp(connector);
5188 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 5204 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5205 struct intel_encoder *intel_encoder = &dig_port->base;
5189 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 5206 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5207 enum intel_display_power_domain aux_domain =
5208 intel_aux_power_domain(dig_port);
5190 5209
5191 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 5210 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5192 connector->base.id, connector->name); 5211 connector->base.id, connector->name);
@@ -5195,11 +5214,11 @@ intel_dp_force(struct drm_connector *connector)
5195 if (connector->status != connector_status_connected) 5214 if (connector->status != connector_status_connected)
5196 return; 5215 return;
5197 5216
5198 intel_display_power_get(dev_priv, intel_dp->aux_power_domain); 5217 intel_display_power_get(dev_priv, aux_domain);
5199 5218
5200 intel_dp_set_edid(intel_dp); 5219 intel_dp_set_edid(intel_dp);
5201 5220
5202 intel_display_power_put(dev_priv, intel_dp->aux_power_domain); 5221 intel_display_power_put(dev_priv, aux_domain);
5203} 5222}
5204 5223
5205static int intel_dp_get_modes(struct drm_connector *connector) 5224static int intel_dp_get_modes(struct drm_connector *connector)
@@ -5264,27 +5283,6 @@ intel_dp_connector_unregister(struct drm_connector *connector)
5264 intel_connector_unregister(connector); 5283 intel_connector_unregister(connector);
5265} 5284}
5266 5285
5267static void
5268intel_dp_connector_destroy(struct drm_connector *connector)
5269{
5270 struct intel_connector *intel_connector = to_intel_connector(connector);
5271
5272 kfree(intel_connector->detect_edid);
5273
5274 if (!IS_ERR_OR_NULL(intel_connector->edid))
5275 kfree(intel_connector->edid);
5276
5277 /*
5278 * Can't call intel_dp_is_edp() since the encoder may have been
5279 * destroyed already.
5280 */
5281 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5282 intel_panel_fini(&intel_connector->panel);
5283
5284 drm_connector_cleanup(connector);
5285 kfree(connector);
5286}
5287
5288void intel_dp_encoder_destroy(struct drm_encoder *encoder) 5286void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5289{ 5287{
5290 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 5288 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
@@ -5348,7 +5346,8 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5348 dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN, 5346 dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5349 an, DRM_HDCP_AN_LEN); 5347 an, DRM_HDCP_AN_LEN);
5350 if (dpcd_ret != DRM_HDCP_AN_LEN) { 5348 if (dpcd_ret != DRM_HDCP_AN_LEN) {
5351 DRM_ERROR("Failed to write An over DP/AUX (%zd)\n", dpcd_ret); 5349 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
5350 dpcd_ret);
5352 return dpcd_ret >= 0 ? -EIO : dpcd_ret; 5351 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5353 } 5352 }
5354 5353
@@ -5364,10 +5363,10 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5364 rxbuf, sizeof(rxbuf), 5363 rxbuf, sizeof(rxbuf),
5365 DP_AUX_CH_CTL_AUX_AKSV_SELECT); 5364 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5366 if (ret < 0) { 5365 if (ret < 0) {
5367 DRM_ERROR("Write Aksv over DP/AUX failed (%d)\n", ret); 5366 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret);
5368 return ret; 5367 return ret;
5369 } else if (ret == 0) { 5368 } else if (ret == 0) {
5370 DRM_ERROR("Aksv write over DP/AUX was empty\n"); 5369 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5371 return -EIO; 5370 return -EIO;
5372 } 5371 }
5373 5372
@@ -5382,7 +5381,7 @@ static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5382 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, 5381 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5383 DRM_HDCP_KSV_LEN); 5382 DRM_HDCP_KSV_LEN);
5384 if (ret != DRM_HDCP_KSV_LEN) { 5383 if (ret != DRM_HDCP_KSV_LEN) {
5385 DRM_ERROR("Read Bksv from DP/AUX failed (%zd)\n", ret); 5384 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret);
5386 return ret >= 0 ? -EIO : ret; 5385 return ret >= 0 ? -EIO : ret;
5387 } 5386 }
5388 return 0; 5387 return 0;
@@ -5400,7 +5399,7 @@ static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5400 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO, 5399 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5401 bstatus, DRM_HDCP_BSTATUS_LEN); 5400 bstatus, DRM_HDCP_BSTATUS_LEN);
5402 if (ret != DRM_HDCP_BSTATUS_LEN) { 5401 if (ret != DRM_HDCP_BSTATUS_LEN) {
5403 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret); 5402 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5404 return ret >= 0 ? -EIO : ret; 5403 return ret >= 0 ? -EIO : ret;
5405 } 5404 }
5406 return 0; 5405 return 0;
@@ -5415,7 +5414,7 @@ int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5415 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS, 5414 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5416 bcaps, 1); 5415 bcaps, 1);
5417 if (ret != 1) { 5416 if (ret != 1) {
5418 DRM_ERROR("Read bcaps from DP/AUX failed (%zd)\n", ret); 5417 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret);
5419 return ret >= 0 ? -EIO : ret; 5418 return ret >= 0 ? -EIO : ret;
5420 } 5419 }
5421 5420
@@ -5445,7 +5444,7 @@ int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5445 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, 5444 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5446 ri_prime, DRM_HDCP_RI_LEN); 5445 ri_prime, DRM_HDCP_RI_LEN);
5447 if (ret != DRM_HDCP_RI_LEN) { 5446 if (ret != DRM_HDCP_RI_LEN) {
5448 DRM_ERROR("Read Ri' from DP/AUX failed (%zd)\n", ret); 5447 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret);
5449 return ret >= 0 ? -EIO : ret; 5448 return ret >= 0 ? -EIO : ret;
5450 } 5449 }
5451 return 0; 5450 return 0;
@@ -5460,7 +5459,7 @@ int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5460 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, 5459 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5461 &bstatus, 1); 5460 &bstatus, 1);
5462 if (ret != 1) { 5461 if (ret != 1) {
5463 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret); 5462 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5464 return ret >= 0 ? -EIO : ret; 5463 return ret >= 0 ? -EIO : ret;
5465 } 5464 }
5466 *ksv_ready = bstatus & DP_BSTATUS_READY; 5465 *ksv_ready = bstatus & DP_BSTATUS_READY;
@@ -5482,8 +5481,8 @@ int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5482 ksv_fifo + i * DRM_HDCP_KSV_LEN, 5481 ksv_fifo + i * DRM_HDCP_KSV_LEN,
5483 len); 5482 len);
5484 if (ret != len) { 5483 if (ret != len) {
5485 DRM_ERROR("Read ksv[%d] from DP/AUX failed (%zd)\n", i, 5484 DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
5486 ret); 5485 i, ret);
5487 return ret >= 0 ? -EIO : ret; 5486 return ret >= 0 ? -EIO : ret;
5488 } 5487 }
5489 } 5488 }
@@ -5503,7 +5502,7 @@ int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5503 DP_AUX_HDCP_V_PRIME(i), part, 5502 DP_AUX_HDCP_V_PRIME(i), part,
5504 DRM_HDCP_V_PRIME_PART_LEN); 5503 DRM_HDCP_V_PRIME_PART_LEN);
5505 if (ret != DRM_HDCP_V_PRIME_PART_LEN) { 5504 if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5506 DRM_ERROR("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret); 5505 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5507 return ret >= 0 ? -EIO : ret; 5506 return ret >= 0 ? -EIO : ret;
5508 } 5507 }
5509 return 0; 5508 return 0;
@@ -5526,7 +5525,7 @@ bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5526 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, 5525 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5527 &bstatus, 1); 5526 &bstatus, 1);
5528 if (ret != 1) { 5527 if (ret != 1) {
5529 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret); 5528 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5530 return false; 5529 return false;
5531 } 5530 }
5532 5531
@@ -5565,6 +5564,7 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
5565static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) 5564static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5566{ 5565{
5567 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 5566 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5567 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5568 5568
5569 lockdep_assert_held(&dev_priv->pps_mutex); 5569 lockdep_assert_held(&dev_priv->pps_mutex);
5570 5570
@@ -5578,7 +5578,7 @@ static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5578 * indefinitely. 5578 * indefinitely.
5579 */ 5579 */
5580 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); 5580 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5581 intel_display_power_get(dev_priv, intel_dp->aux_power_domain); 5581 intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
5582 5582
5583 edp_panel_vdd_schedule_off(intel_dp); 5583 edp_panel_vdd_schedule_off(intel_dp);
5584} 5584}
@@ -5631,7 +5631,7 @@ static const struct drm_connector_funcs intel_dp_connector_funcs = {
5631 .atomic_set_property = intel_digital_connector_atomic_set_property, 5631 .atomic_set_property = intel_digital_connector_atomic_set_property,
5632 .late_register = intel_dp_connector_register, 5632 .late_register = intel_dp_connector_register,
5633 .early_unregister = intel_dp_connector_unregister, 5633 .early_unregister = intel_dp_connector_unregister,
5634 .destroy = intel_dp_connector_destroy, 5634 .destroy = intel_connector_destroy,
5635 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 5635 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5636 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 5636 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5637}; 5637};
@@ -5673,11 +5673,11 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5673 5673
5674 if (long_hpd) { 5674 if (long_hpd) {
5675 intel_dp->reset_link_params = true; 5675 intel_dp->reset_link_params = true;
5676 intel_dp->detect_done = false;
5677 return IRQ_NONE; 5676 return IRQ_NONE;
5678 } 5677 }
5679 5678
5680 intel_display_power_get(dev_priv, intel_dp->aux_power_domain); 5679 intel_display_power_get(dev_priv,
5680 intel_aux_power_domain(intel_dig_port));
5681 5681
5682 if (intel_dp->is_mst) { 5682 if (intel_dp->is_mst) {
5683 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { 5683 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
@@ -5690,7 +5690,6 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5690 intel_dp->is_mst = false; 5690 intel_dp->is_mst = false;
5691 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 5691 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5692 intel_dp->is_mst); 5692 intel_dp->is_mst);
5693 intel_dp->detect_done = false;
5694 goto put_power; 5693 goto put_power;
5695 } 5694 }
5696 } 5695 }
@@ -5700,19 +5699,15 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5700 5699
5701 handled = intel_dp_short_pulse(intel_dp); 5700 handled = intel_dp_short_pulse(intel_dp);
5702 5701
5703 /* Short pulse can signify loss of hdcp authentication */ 5702 if (!handled)
5704 intel_hdcp_check_link(intel_dp->attached_connector);
5705
5706 if (!handled) {
5707 intel_dp->detect_done = false;
5708 goto put_power; 5703 goto put_power;
5709 }
5710 } 5704 }
5711 5705
5712 ret = IRQ_HANDLED; 5706 ret = IRQ_HANDLED;
5713 5707
5714put_power: 5708put_power:
5715 intel_display_power_put(dev_priv, intel_dp->aux_power_domain); 5709 intel_display_power_put(dev_priv,
5710 intel_aux_power_domain(intel_dig_port));
5716 5711
5717 return ret; 5712 return ret;
5718} 5713}
@@ -5743,6 +5738,10 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
5743 intel_attach_force_audio_property(connector); 5738 intel_attach_force_audio_property(connector);
5744 5739
5745 intel_attach_broadcast_rgb_property(connector); 5740 intel_attach_broadcast_rgb_property(connector);
5741 if (HAS_GMCH_DISPLAY(dev_priv))
5742 drm_connector_attach_max_bpc_property(connector, 6, 10);
5743 else if (INTEL_GEN(dev_priv) >= 5)
5744 drm_connector_attach_max_bpc_property(connector, 6, 12);
5746 5745
5747 if (intel_dp_is_edp(intel_dp)) { 5746 if (intel_dp_is_edp(intel_dp)) {
5748 u32 allowed_scalers; 5747 u32 allowed_scalers;
@@ -6099,10 +6098,10 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6099 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { 6098 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6100 switch (index) { 6099 switch (index) {
6101 case DRRS_HIGH_RR: 6100 case DRRS_HIGH_RR:
6102 intel_dp_set_m_n(intel_crtc, M1_N1); 6101 intel_dp_set_m_n(crtc_state, M1_N1);
6103 break; 6102 break;
6104 case DRRS_LOW_RR: 6103 case DRRS_LOW_RR:
6105 intel_dp_set_m_n(intel_crtc, M2_N2); 6104 intel_dp_set_m_n(crtc_state, M2_N2);
6106 break; 6105 break;
6107 case DRRS_MAX_RR: 6106 case DRRS_MAX_RR:
6108 default: 6107 default:
@@ -6422,6 +6421,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6422 if (!intel_dp_is_edp(intel_dp)) 6421 if (!intel_dp_is_edp(intel_dp))
6423 return true; 6422 return true;
6424 6423
6424 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
6425
6425 /* 6426 /*
6426 * On IBX/CPT we may get here with LVDS already registered. Since the 6427 * On IBX/CPT we may get here with LVDS already registered. Since the
6427 * driver uses the only internal power sequencer available for both 6428 * driver uses the only internal power sequencer available for both
@@ -6514,6 +6515,10 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6514 intel_connector->panel.backlight.power = intel_edp_backlight_power; 6515 intel_connector->panel.backlight.power = intel_edp_backlight_power;
6515 intel_panel_setup_backlight(connector, pipe); 6516 intel_panel_setup_backlight(connector, pipe);
6516 6517
6518 if (fixed_mode)
6519 drm_connector_init_panel_orientation_property(
6520 connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
6521
6517 return true; 6522 return true;
6518 6523
6519out_vdd_off: 6524out_vdd_off:
@@ -6624,9 +6629,6 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6624 6629
6625 intel_dp_aux_init(intel_dp); 6630 intel_dp_aux_init(intel_dp);
6626 6631
6627 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6628 edp_panel_vdd_work);
6629
6630 intel_connector_attach_encoder(intel_connector, intel_encoder); 6632 intel_connector_attach_encoder(intel_connector, intel_encoder);
6631 6633
6632 if (HAS_DDI(dev_priv)) 6634 if (HAS_DDI(dev_priv))
@@ -6743,6 +6745,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
6743 if (port != PORT_A) 6745 if (port != PORT_A)
6744 intel_infoframe_init(intel_dig_port); 6746 intel_infoframe_init(intel_dig_port);
6745 6747
6748 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
6746 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) 6749 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6747 goto err_init_connector; 6750 goto err_init_connector;
6748 6751
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-23 16:38:22 -0400