1 files changed, 77 insertions, 434 deletions

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f192f58708c2..ffa43eca14d3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -131,11 +131,6 @@ static void vlv_steal_power_sequencer(struct drm_device *dev,
                                       enum pipe pipe);
 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 
-static unsigned int intel_dp_unused_lane_mask(int lane_count)
-{
-        return ~((1 << lane_count) - 1) & 0xf;
-}
-
 static int
 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
 {
@@ -775,6 +770,7 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
                DP_AUX_CH_CTL_TIME_OUT_1600us |
                DP_AUX_CH_CTL_RECEIVE_ERROR |
                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
+               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 }
 
@@ -1181,7 +1177,6 @@ static void intel_aux_reg_init(struct intel_dp *intel_dp)
 static void
 intel_dp_aux_fini(struct intel_dp *intel_dp)
 {
-        drm_dp_aux_unregister(&intel_dp->aux);
         kfree(intel_dp->aux.name);
 }
 
@@ -1216,15 +1211,6 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
         return 0;
 }
 
-static void
-intel_dp_connector_unregister(struct intel_connector *intel_connector)
-{
-        struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
-
-        intel_dp_aux_fini(intel_dp);
-        intel_connector_unregister(intel_connector);
-}
-
 static int
 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
 {
@@ -1582,6 +1568,27 @@ found:
                                 &pipe_config->dp_m2_n2);
         }
 
+        /*
+         * DPLL0 VCO may need to be adjusted to get the correct
+         * clock for eDP. This will affect cdclk as well.
+         */
+        if (is_edp(intel_dp) &&
+            (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
+                int vco;
+
+                switch (pipe_config->port_clock / 2) {
+                case 108000:
+                case 216000:
+                        vco = 8640000;
+                        break;
+                default:
+                        vco = 8100000;
+                        break;
+                }
+
+                to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
+        }
+
         if (!HAS_DDI(dev))
                 intel_dp_set_clock(encoder, pipe_config);
 
@@ -2460,50 +2467,6 @@ static void vlv_post_disable_dp(struct intel_encoder *encoder)
         intel_dp_link_down(intel_dp);
 }
 
-static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
-                                     bool reset)
-{
-        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-        enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
-        struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
-        enum pipe pipe = crtc->pipe;
-        uint32_t val;
-
-        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
-        if (reset)
-                val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-        else
-                val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
-
-        if (crtc->config->lane_count > 2) {
-                val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
-                if (reset)
-                        val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-                else
-                        val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
-                vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
-        }
-
-        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
-        val |= CHV_PCS_REQ_SOFTRESET_EN;
-        if (reset)
-                val &= ~DPIO_PCS_CLK_SOFT_RESET;
-        else
-                val |= DPIO_PCS_CLK_SOFT_RESET;
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
-
-        if (crtc->config->lane_count > 2) {
-                val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
-                val |= CHV_PCS_REQ_SOFTRESET_EN;
-                if (reset)
-                        val &= ~DPIO_PCS_CLK_SOFT_RESET;
-                else
-                        val |= DPIO_PCS_CLK_SOFT_RESET;
-                vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
-        }
-}
-
 static void chv_post_disable_dp(struct intel_encoder *encoder)
 {
         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
@@ -2811,266 +2774,38 @@ static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
 
 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
 {
-        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-        struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
-        struct drm_device *dev = encoder->base.dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
-        enum dpio_channel port = vlv_dport_to_channel(dport);
-        int pipe = intel_crtc->pipe;
-        u32 val;
-
-        mutex_lock(&dev_priv->sb_lock);
-
-        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
-        val = 0;
-        if (pipe)
-                val |= (1<<21);
-        else
-                val &= ~(1<<21);
-        val |= 0x001000c4;
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
-
-        mutex_unlock(&dev_priv->sb_lock);
+        vlv_phy_pre_encoder_enable(encoder);
 
         intel_enable_dp(encoder);
 }
 
 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
 {
-        struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
-        struct drm_device *dev = encoder->base.dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        struct intel_crtc *intel_crtc =
-                to_intel_crtc(encoder->base.crtc);
-        enum dpio_channel port = vlv_dport_to_channel(dport);
-        int pipe = intel_crtc->pipe;
-
         intel_dp_prepare(encoder);
 
-        /* Program Tx lane resets to default */
-        mutex_lock(&dev_priv->sb_lock);
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
-                         DPIO_PCS_TX_LANE2_RESET |
-                         DPIO_PCS_TX_LANE1_RESET);
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
-                         DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
-                         DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
-                         (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
-                                 DPIO_PCS_CLK_SOFT_RESET);
-
-        /* Fix up inter-pair skew failure */
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
-        vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
-        vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
-        mutex_unlock(&dev_priv->sb_lock);
+        vlv_phy_pre_pll_enable(encoder);
 }
 
 static void chv_pre_enable_dp(struct intel_encoder *encoder)
 {
-        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-        struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
-        struct drm_device *dev = encoder->base.dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        struct intel_crtc *intel_crtc =
-                to_intel_crtc(encoder->base.crtc);
-        enum dpio_channel ch = vlv_dport_to_channel(dport);
-        int pipe = intel_crtc->pipe;
-        int data, i, stagger;
-        u32 val;
-
-        mutex_lock(&dev_priv->sb_lock);
-
-        /* allow hardware to manage TX FIFO reset source */
-        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
-        val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
-
-        if (intel_crtc->config->lane_count > 2) {
-                val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
-                val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
-                vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
-        }
-
-        /* Program Tx lane latency optimal setting*/
-        for (i = 0; i < intel_crtc->config->lane_count; i++) {
-                /* Set the upar bit */
-                if (intel_crtc->config->lane_count == 1)
-                        data = 0x0;
-                else
-                        data = (i == 1) ? 0x0 : 0x1;
-                vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
-                                data << DPIO_UPAR_SHIFT);
-        }
-
-        /* Data lane stagger programming */
-        if (intel_crtc->config->port_clock > 270000)
-                stagger = 0x18;
-        else if (intel_crtc->config->port_clock > 135000)
-                stagger = 0xd;
-        else if (intel_crtc->config->port_clock > 67500)
-                stagger = 0x7;
-        else if (intel_crtc->config->port_clock > 33750)
-                stagger = 0x4;
-        else
-                stagger = 0x2;
-
-        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
-        val |= DPIO_TX2_STAGGER_MASK(0x1f);
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
-
-        if (intel_crtc->config->lane_count > 2) {
-                val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
-                val |= DPIO_TX2_STAGGER_MASK(0x1f);
-                vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
-        }
-
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
-                       DPIO_LANESTAGGER_STRAP(stagger) |
-                       DPIO_LANESTAGGER_STRAP_OVRD |
-                       DPIO_TX1_STAGGER_MASK(0x1f) |
-                       DPIO_TX1_STAGGER_MULT(6) |
-                       DPIO_TX2_STAGGER_MULT(0));
-
-        if (intel_crtc->config->lane_count > 2) {
-                vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
-                               DPIO_LANESTAGGER_STRAP(stagger) |
-                               DPIO_LANESTAGGER_STRAP_OVRD |
-                               DPIO_TX1_STAGGER_MASK(0x1f) |
-                               DPIO_TX1_STAGGER_MULT(7) |
-                               DPIO_TX2_STAGGER_MULT(5));
-        }
-
-        /* Deassert data lane reset */
-        chv_data_lane_soft_reset(encoder, false);
-
-        mutex_unlock(&dev_priv->sb_lock);
+        chv_phy_pre_encoder_enable(encoder);
 
         intel_enable_dp(encoder);
 
         /* Second common lane will stay alive on its own now */
-        if (dport->release_cl2_override) {
-                chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
-                dport->release_cl2_override = false;
-        }
+        chv_phy_release_cl2_override(encoder);
 }
 
 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
 {
-        struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
-        struct drm_device *dev = encoder->base.dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        struct intel_crtc *intel_crtc =
-                to_intel_crtc(encoder->base.crtc);
-        enum dpio_channel ch = vlv_dport_to_channel(dport);
-        enum pipe pipe = intel_crtc->pipe;
-        unsigned int lane_mask =
-                intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
-        u32 val;
-
         intel_dp_prepare(encoder);
 
-        /*
-         * Must trick the second common lane into life.
-         * Otherwise we can't even access the PLL.
-         */
-        if (ch == DPIO_CH0 && pipe == PIPE_B)
-                dport->release_cl2_override =
-                        !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
-
-        chv_phy_powergate_lanes(encoder, true, lane_mask);
-
-        mutex_lock(&dev_priv->sb_lock);
-
-        /* Assert data lane reset */
-        chv_data_lane_soft_reset(encoder, true);
-
-        /* program left/right clock distribution */
-        if (pipe != PIPE_B) {
-                val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
-                val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
-                if (ch == DPIO_CH0)
-                        val |= CHV_BUFLEFTENA1_FORCE;
-                if (ch == DPIO_CH1)
-                        val |= CHV_BUFRIGHTENA1_FORCE;
-                vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
-        } else {
-                val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
-                val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
-                if (ch == DPIO_CH0)
-                        val |= CHV_BUFLEFTENA2_FORCE;
-                if (ch == DPIO_CH1)
-                        val |= CHV_BUFRIGHTENA2_FORCE;
-                vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
-        }
-
-        /* program clock channel usage */
-        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
-        val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
-        if (pipe != PIPE_B)
-                val &= ~CHV_PCS_USEDCLKCHANNEL;
-        else
-                val |= CHV_PCS_USEDCLKCHANNEL;
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
-
-        if (intel_crtc->config->lane_count > 2) {
-                val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
-                val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
-                if (pipe != PIPE_B)
-                        val &= ~CHV_PCS_USEDCLKCHANNEL;
-                else
-                        val |= CHV_PCS_USEDCLKCHANNEL;
-                vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
-        }
-
-        /*
-         * This a a bit weird since generally CL
-         * matches the pipe, but here we need to
-         * pick the CL based on the port.
-         */
-        val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
-        if (pipe != PIPE_B)
-                val &= ~CHV_CMN_USEDCLKCHANNEL;
-        else
-                val |= CHV_CMN_USEDCLKCHANNEL;
-        vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
-
-        mutex_unlock(&dev_priv->sb_lock);
+        chv_phy_pre_pll_enable(encoder);
 }
 
 static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
 {
-        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-        enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
-        u32 val;
-
-        mutex_lock(&dev_priv->sb_lock);
-
-        /* disable left/right clock distribution */
-        if (pipe != PIPE_B) {
-                val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
-                val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
-                vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
-        } else {
-                val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
-                val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
-                vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
-        }
-
-        mutex_unlock(&dev_priv->sb_lock);
-
-        /*
-         * Leave the power down bit cleared for at least one
-         * lane so that chv_powergate_phy_ch() will power
-         * on something when the channel is otherwise unused.
-         * When the port is off and the override is removed
-         * the lanes power down anyway, so otherwise it doesn't
-         * really matter what the state of power down bits is
-         * after this.
-         */
-        chv_phy_powergate_lanes(encoder, false, 0x0);
+        chv_phy_post_pll_disable(encoder);
 }
 
 /*
@@ -3178,16 +2913,10 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 
 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
 {
-        struct drm_device *dev = intel_dp_to_dev(intel_dp);
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
-        struct intel_crtc *intel_crtc =
-                to_intel_crtc(dport->base.base.crtc);
+        struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
         unsigned long demph_reg_value, preemph_reg_value,
                 uniqtranscale_reg_value;
         uint8_t train_set = intel_dp->train_set[0];
-        enum dpio_channel port = vlv_dport_to_channel(dport);
-        int pipe = intel_crtc->pipe;
 
         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
         case DP_TRAIN_PRE_EMPH_LEVEL_0:
@@ -3262,37 +2991,18 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
                 return 0;
         }
 
-        mutex_lock(&dev_priv->sb_lock);
-        vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
-        vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
-        vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
-                         uniqtranscale_reg_value);
-        vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
-        vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
-        mutex_unlock(&dev_priv->sb_lock);
+        vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
+                                 uniqtranscale_reg_value, 0);
 
         return 0;
 }
 
-static bool chv_need_uniq_trans_scale(uint8_t train_set)
-{
-        return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
-                (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
-}
-
 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
 {
-        struct drm_device *dev = intel_dp_to_dev(intel_dp);
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
-        struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
-        u32 deemph_reg_value, margin_reg_value, val;
+        struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+        u32 deemph_reg_value, margin_reg_value;
+        bool uniq_trans_scale = false;
         uint8_t train_set = intel_dp->train_set[0];
-        enum dpio_channel ch = vlv_dport_to_channel(dport);
-        enum pipe pipe = intel_crtc->pipe;
-        int i;
 
         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
         case DP_TRAIN_PRE_EMPH_LEVEL_0:
@@ -3312,7 +3022,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
                         deemph_reg_value = 128;
                         margin_reg_value = 154;
-                        /* FIXME extra to set for 1200 */
+                        uniq_trans_scale = true;
                         break;
                 default:
                         return 0;
@@ -3364,88 +3074,8 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
                 return 0;
         }
 
-        mutex_lock(&dev_priv->sb_lock);
-
-        /* Clear calc init */
-        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
-        val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
-        val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
-        val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
-
-        if (intel_crtc->config->lane_count > 2) {
-                val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
-                val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
-                val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
-                val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
-                vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
-        }
-
-        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
-        val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
-        val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
-
-        if (intel_crtc->config->lane_count > 2) {
-                val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
-                val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
-                val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
-                vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
-        }
-
-        /* Program swing deemph */
-        for (i = 0; i < intel_crtc->config->lane_count; i++) {
-                val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
-                val &= ~DPIO_SWING_DEEMPH9P5_MASK;
-                val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
-                vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
-        }
-
-        /* Program swing margin */
-        for (i = 0; i < intel_crtc->config->lane_count; i++) {
-                val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
-
-                val &= ~DPIO_SWING_MARGIN000_MASK;
-                val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
-
-                /*
-                 * Supposedly this value shouldn't matter when unique transition
-                 * scale is disabled, but in fact it does matter. Let's just
-                 * always program the same value and hope it's OK.
-                 */
-                val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
-                val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
-
-                vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
-        }
-
-        /*
-         * The document said it needs to set bit 27 for ch0 and bit 26
-         * for ch1. Might be a typo in the doc.
-         * For now, for this unique transition scale selection, set bit
-         * 27 for ch0 and ch1.
-         */
-        for (i = 0; i < intel_crtc->config->lane_count; i++) {
-                val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
-                if (chv_need_uniq_trans_scale(train_set))
-                        val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
-                else
-                        val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
-                vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
-        }
-
-        /* Start swing calculation */
-        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
-        val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
-
-        if (intel_crtc->config->lane_count > 2) {
-                val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
-                val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
-                vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
-        }
-
-        mutex_unlock(&dev_priv->sb_lock);
+        chv_set_phy_signal_level(encoder, deemph_reg_value,
+                                 margin_reg_value, uniq_trans_scale);
 
         return 0;
 }
@@ -3714,7 +3344,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
         struct drm_device *dev = dig_port->base.base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
-        uint8_t rev;
 
         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
                              sizeof(intel_dp->dpcd)) < 0)
@@ -3771,6 +3400,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
                         DRM_DEBUG_KMS("PSR2 %s on sink",
                                 dev_priv->psr.psr2_support ? "supported" : "not supported");
                 }
+
+                /* Read the eDP Display control capabilities registers */
+                memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
+                if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+                                (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
+                                                intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
+                                                                sizeof(intel_dp->edp_dpcd)))
+                        DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
+                                        intel_dp->edp_dpcd);
         }
 
         DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
@@ -3778,10 +3416,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
                       yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
 
         /* Intermediate frequency support */
-        if (is_edp(intel_dp) &&
-            (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
-            (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
-            (rev >= 0x03)) { /* eDp v1.4 or higher */
+        if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */
                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
                 int i;
 
@@ -4812,6 +4447,13 @@ done:
 }
 
 static void
+intel_dp_connector_unregister(struct drm_connector *connector)
+{
+        drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
+        intel_connector_unregister(connector);
+}
+
+static void
 intel_dp_connector_destroy(struct drm_connector *connector)
 {
         struct intel_connector *intel_connector = to_intel_connector(connector);
@@ -4851,6 +4493,9 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder)
                         intel_dp->edp_notifier.notifier_call = NULL;
                 }
         }
+
+        intel_dp_aux_fini(intel_dp);
+
         drm_encoder_cleanup(encoder);
         kfree(intel_dig_port);
 }
@@ -4927,6 +4572,7 @@ static const struct drm_connector_funcs intel_dp_connector_funcs = {
         .fill_modes = drm_helper_probe_single_connector_modes,
         .set_property = intel_dp_set_property,
         .atomic_get_property = intel_connector_atomic_get_property,
+        .early_unregister = intel_dp_connector_unregister,
         .destroy = intel_dp_connector_destroy,
         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
@@ -4935,7 +4581,6 @@ static const struct drm_connector_funcs intel_dp_connector_funcs = {
 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
         .get_modes = intel_dp_get_modes,
         .mode_valid = intel_dp_mode_valid,
-        .best_encoder = intel_best_encoder,
 };
 
 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
@@ -4977,9 +4622,6 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
         intel_display_power_get(dev_priv, power_domain);
 
         if (long_hpd) {
-                /* indicate that we need to restart link training */
-                intel_dp->train_set_valid = false;
-
                 intel_dp_long_pulse(intel_dp->attached_connector);
                 if (intel_dp->is_mst)
                         ret = IRQ_HANDLED;
@@ -5590,14 +5232,14 @@ void intel_edp_drrs_flush(struct drm_device *dev,
  *
  * DRRS saves power by switching to low RR based on usage scenarios.
  *
- * eDP DRRS:-
- *        The implementation is based on frontbuffer tracking implementation.
- * When there is a disturbance on the screen triggered by user activity or a
- * periodic system activity, DRRS is disabled (RR is changed to high RR).
- * When there is no movement on screen, after a timeout of 1 second, a switch
- * to low RR is made.
- *        For integration with frontbuffer tracking code,
- * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
+ * The implementation is based on frontbuffer tracking implementation.  When
+ * there is a disturbance on the screen triggered by user activity or a periodic
+ * system activity, DRRS is disabled (RR is changed to high RR).  When there is
+ * no movement on screen, after a timeout of 1 second, a switch to low RR is
+ * made.
+ *
+ * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
+ * and intel_edp_drrs_flush() are called.
  *
  * DRRS can be further extended to support other internal panels and also
  * the scenario of video playback wherein RR is set based on the rate
@@ -5725,8 +5367,11 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
                 fixed_mode = drm_mode_duplicate(dev,
                                         dev_priv->vbt.lfp_lvds_vbt_mode);
-                if (fixed_mode)
+                if (fixed_mode) {
                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
+                        connector->display_info.width_mm = fixed_mode->width_mm;
+                        connector->display_info.height_mm = fixed_mode->height_mm;
+                }
         }
         mutex_unlock(&dev->mode_config.mutex);
 
@@ -5840,7 +5485,6 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
         else
                 intel_connector->get_hw_state = intel_connector_get_hw_state;
-        intel_connector->unregister = intel_dp_connector_unregister;
 
         /* Set up the hotplug pin. */
         switch (port) {
@@ -5923,9 +5567,9 @@ fail:
         return false;
 }
 
-void
-intel_dp_init(struct drm_device *dev,
-              i915_reg_t output_reg, enum port port)
+bool intel_dp_init(struct drm_device *dev,
+                   i915_reg_t output_reg,
+                   enum port port)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_digital_port *intel_dig_port;
@@ -5935,7 +5579,7 @@ intel_dp_init(struct drm_device *dev,
 
         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
         if (!intel_dig_port)
-                return;
+                return false;
 
         intel_connector = intel_connector_alloc();
         if (!intel_connector)
@@ -5945,7 +5589,7 @@ intel_dp_init(struct drm_device *dev,
         encoder = &intel_encoder->base;
 
         if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
-                             DRM_MODE_ENCODER_TMDS, NULL))
+                             DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port)))
                 goto err_encoder_init;
 
         intel_encoder->compute_config = intel_dp_compute_config;
@@ -5992,7 +5636,7 @@ intel_dp_init(struct drm_device *dev,
         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
                 goto err_init_connector;
 
-        return;
+        return true;
 
 err_init_connector:
         drm_encoder_cleanup(encoder);
@@ -6000,8 +5644,7 @@ err_encoder_init:
         kfree(intel_connector);
 err_connector_alloc:
         kfree(intel_dig_port);
-
-        return;
+        return false;
 }
 
 void intel_dp_mst_suspend(struct drm_device *dev)