diff options
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.h')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.h | 37 |
1 files changed, 29 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h index 9fac67e31205..5f2955b944da 100644 --- a/drivers/gpu/drm/i915/intel_display.h +++ b/drivers/gpu/drm/i915/intel_display.h | |||
@@ -43,6 +43,11 @@ enum i915_gpio { | |||
43 | GPIOM, | 43 | GPIOM, |
44 | }; | 44 | }; |
45 | 45 | ||
46 | /* | ||
47 | * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the | ||
48 | * rest have consecutive values and match the enum values of transcoders | ||
49 | * with a 1:1 transcoder -> pipe mapping. | ||
50 | */ | ||
46 | enum pipe { | 51 | enum pipe { |
47 | INVALID_PIPE = -1, | 52 | INVALID_PIPE = -1, |
48 | 53 | ||
@@ -57,12 +62,25 @@ enum pipe { | |||
57 | #define pipe_name(p) ((p) + 'A') | 62 | #define pipe_name(p) ((p) + 'A') |
58 | 63 | ||
59 | enum transcoder { | 64 | enum transcoder { |
60 | TRANSCODER_A = 0, | 65 | /* |
61 | TRANSCODER_B, | 66 | * The following transcoders have a 1:1 transcoder -> pipe mapping, |
62 | TRANSCODER_C, | 67 | * keep their values fixed: the code assumes that TRANSCODER_A=0, the |
68 | * rest have consecutive values and match the enum values of the pipes | ||
69 | * they map to. | ||
70 | */ | ||
71 | TRANSCODER_A = PIPE_A, | ||
72 | TRANSCODER_B = PIPE_B, | ||
73 | TRANSCODER_C = PIPE_C, | ||
74 | |||
75 | /* | ||
76 | * The following transcoders can map to any pipe, their enum value | ||
77 | * doesn't need to stay fixed. | ||
78 | */ | ||
63 | TRANSCODER_EDP, | 79 | TRANSCODER_EDP, |
64 | TRANSCODER_DSI_A, | 80 | TRANSCODER_DSI_0, |
65 | TRANSCODER_DSI_C, | 81 | TRANSCODER_DSI_1, |
82 | TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ | ||
83 | TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ | ||
66 | 84 | ||
67 | I915_MAX_TRANSCODERS | 85 | I915_MAX_TRANSCODERS |
68 | }; | 86 | }; |
@@ -120,6 +138,9 @@ enum plane_id { | |||
120 | PLANE_SPRITE0, | 138 | PLANE_SPRITE0, |
121 | PLANE_SPRITE1, | 139 | PLANE_SPRITE1, |
122 | PLANE_SPRITE2, | 140 | PLANE_SPRITE2, |
141 | PLANE_SPRITE3, | ||
142 | PLANE_SPRITE4, | ||
143 | PLANE_SPRITE5, | ||
123 | PLANE_CURSOR, | 144 | PLANE_CURSOR, |
124 | 145 | ||
125 | I915_MAX_PLANES, | 146 | I915_MAX_PLANES, |
@@ -363,7 +384,7 @@ struct intel_link_m_n { | |||
363 | (__dev_priv)->power_domains.power_well_count; \ | 384 | (__dev_priv)->power_domains.power_well_count; \ |
364 | (__power_well)++) | 385 | (__power_well)++) |
365 | 386 | ||
366 | #define for_each_power_well_rev(__dev_priv, __power_well) \ | 387 | #define for_each_power_well_reverse(__dev_priv, __power_well) \ |
367 | for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ | 388 | for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ |
368 | (__dev_priv)->power_domains.power_well_count - 1; \ | 389 | (__dev_priv)->power_domains.power_well_count - 1; \ |
369 | (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ | 390 | (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ |
@@ -373,8 +394,8 @@ struct intel_link_m_n { | |||
373 | for_each_power_well(__dev_priv, __power_well) \ | 394 | for_each_power_well(__dev_priv, __power_well) \ |
374 | for_each_if((__power_well)->desc->domains & (__domain_mask)) | 395 | for_each_if((__power_well)->desc->domains & (__domain_mask)) |
375 | 396 | ||
376 | #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \ | 397 | #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \ |
377 | for_each_power_well_rev(__dev_priv, __power_well) \ | 398 | for_each_power_well_reverse(__dev_priv, __power_well) \ |
378 | for_each_if((__power_well)->desc->domains & (__domain_mask)) | 399 | for_each_if((__power_well)->desc->domains & (__domain_mask)) |
379 | 400 | ||
380 | #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ | 401 | #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ |