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path: root/drivers/gpu/drm/i915/intel_display.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c1986
1 files changed, 926 insertions, 1060 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9741cc419e1b..812ec5ae5c7b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -24,7 +24,6 @@
24 * Eric Anholt <eric@anholt.net> 24 * Eric Anholt <eric@anholt.net>
25 */ 25 */
26 26
27#include <linux/dmi.h>
28#include <linux/module.h> 27#include <linux/module.h>
29#include <linux/input.h> 28#include <linux/input.h>
30#include <linux/i2c.h> 29#include <linux/i2c.h>
@@ -74,55 +73,6 @@ static const uint64_t i9xx_format_modifiers[] = {
74 DRM_FORMAT_MOD_INVALID 73 DRM_FORMAT_MOD_INVALID
75}; 74};
76 75
77static const uint32_t skl_primary_formats[] = {
78 DRM_FORMAT_C8,
79 DRM_FORMAT_RGB565,
80 DRM_FORMAT_XRGB8888,
81 DRM_FORMAT_XBGR8888,
82 DRM_FORMAT_ARGB8888,
83 DRM_FORMAT_ABGR8888,
84 DRM_FORMAT_XRGB2101010,
85 DRM_FORMAT_XBGR2101010,
86 DRM_FORMAT_YUYV,
87 DRM_FORMAT_YVYU,
88 DRM_FORMAT_UYVY,
89 DRM_FORMAT_VYUY,
90};
91
92static const uint32_t skl_pri_planar_formats[] = {
93 DRM_FORMAT_C8,
94 DRM_FORMAT_RGB565,
95 DRM_FORMAT_XRGB8888,
96 DRM_FORMAT_XBGR8888,
97 DRM_FORMAT_ARGB8888,
98 DRM_FORMAT_ABGR8888,
99 DRM_FORMAT_XRGB2101010,
100 DRM_FORMAT_XBGR2101010,
101 DRM_FORMAT_YUYV,
102 DRM_FORMAT_YVYU,
103 DRM_FORMAT_UYVY,
104 DRM_FORMAT_VYUY,
105 DRM_FORMAT_NV12,
106};
107
108static const uint64_t skl_format_modifiers_noccs[] = {
109 I915_FORMAT_MOD_Yf_TILED,
110 I915_FORMAT_MOD_Y_TILED,
111 I915_FORMAT_MOD_X_TILED,
112 DRM_FORMAT_MOD_LINEAR,
113 DRM_FORMAT_MOD_INVALID
114};
115
116static const uint64_t skl_format_modifiers_ccs[] = {
117 I915_FORMAT_MOD_Yf_TILED_CCS,
118 I915_FORMAT_MOD_Y_TILED_CCS,
119 I915_FORMAT_MOD_Yf_TILED,
120 I915_FORMAT_MOD_Y_TILED,
121 I915_FORMAT_MOD_X_TILED,
122 DRM_FORMAT_MOD_LINEAR,
123 DRM_FORMAT_MOD_INVALID
124};
125
126/* Cursor formats */ 76/* Cursor formats */
127static const uint32_t intel_cursor_formats[] = { 77static const uint32_t intel_cursor_formats[] = {
128 DRM_FORMAT_ARGB8888, 78 DRM_FORMAT_ARGB8888,
@@ -141,15 +91,15 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
141static int intel_framebuffer_init(struct intel_framebuffer *ifb, 91static int intel_framebuffer_init(struct intel_framebuffer *ifb,
142 struct drm_i915_gem_object *obj, 92 struct drm_i915_gem_object *obj,
143 struct drm_mode_fb_cmd2 *mode_cmd); 93 struct drm_mode_fb_cmd2 *mode_cmd);
144static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); 94static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
145static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); 95static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
146static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); 96static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
147static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, 97 const struct intel_link_m_n *m_n,
148 struct intel_link_m_n *m_n, 98 const struct intel_link_m_n *m2_n2);
149 struct intel_link_m_n *m2_n2); 99static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
150static void ironlake_set_pipeconf(struct drm_crtc *crtc); 100static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
151static void haswell_set_pipeconf(struct drm_crtc *crtc); 101static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
152static void haswell_set_pipemisc(struct drm_crtc *crtc); 102static void haswell_set_pipemisc(const struct intel_crtc_state *crtc_state);
153static void vlv_prepare_pll(struct intel_crtc *crtc, 103static void vlv_prepare_pll(struct intel_crtc *crtc,
154 const struct intel_crtc_state *pipe_config); 104 const struct intel_crtc_state *pipe_config);
155static void chv_prepare_pll(struct intel_crtc *crtc, 105static void chv_prepare_pll(struct intel_crtc *crtc,
@@ -158,9 +108,9 @@ static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
158static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); 108static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
159static void intel_crtc_init_scalers(struct intel_crtc *crtc, 109static void intel_crtc_init_scalers(struct intel_crtc *crtc,
160 struct intel_crtc_state *crtc_state); 110 struct intel_crtc_state *crtc_state);
161static void skylake_pfit_enable(struct intel_crtc *crtc); 111static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
162static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); 112static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
163static void ironlake_pfit_enable(struct intel_crtc *crtc); 113static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
164static void intel_modeset_setup_hw_state(struct drm_device *dev, 114static void intel_modeset_setup_hw_state(struct drm_device *dev,
165 struct drm_modeset_acquire_ctx *ctx); 115 struct drm_modeset_acquire_ctx *ctx);
166static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); 116static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
@@ -506,23 +456,8 @@ static const struct intel_limit intel_limits_bxt = {
506}; 456};
507 457
508static void 458static void
509skl_wa_528(struct drm_i915_private *dev_priv, int pipe, bool enable)
510{
511 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
512 return;
513
514 if (enable)
515 I915_WRITE(CHICKEN_PIPESL_1(pipe), HSW_FBCQ_DIS);
516 else
517 I915_WRITE(CHICKEN_PIPESL_1(pipe), 0);
518}
519
520static void
521skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable) 459skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
522{ 460{
523 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
524 return;
525
526 if (enable) 461 if (enable)
527 I915_WRITE(CLKGATE_DIS_PSL(pipe), 462 I915_WRITE(CLKGATE_DIS_PSL(pipe),
528 DUPS1_GATING_DIS | DUPS2_GATING_DIS); 463 DUPS1_GATING_DIS | DUPS2_GATING_DIS);
@@ -1381,6 +1316,7 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1381 "PCH LVDS enabled on transcoder %c, should be disabled\n", 1316 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1382 pipe_name(pipe)); 1317 pipe_name(pipe));
1383 1318
1319 /* PCH SDVOB multiplex with HDMIB */
1384 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB); 1320 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1385 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC); 1321 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1386 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID); 1322 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
@@ -1565,14 +1501,15 @@ static void i9xx_enable_pll(struct intel_crtc *crtc,
1565 } 1501 }
1566} 1502}
1567 1503
1568static void i9xx_disable_pll(struct intel_crtc *crtc) 1504static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1569{ 1505{
1506 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1570 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1507 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1571 enum pipe pipe = crtc->pipe; 1508 enum pipe pipe = crtc->pipe;
1572 1509
1573 /* Disable DVO 2x clock on both PLLs if necessary */ 1510 /* Disable DVO 2x clock on both PLLs if necessary */
1574 if (IS_I830(dev_priv) && 1511 if (IS_I830(dev_priv) &&
1575 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && 1512 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO) &&
1576 !intel_num_dvo_pipes(dev_priv)) { 1513 !intel_num_dvo_pipes(dev_priv)) {
1577 I915_WRITE(DPLL(PIPE_B), 1514 I915_WRITE(DPLL(PIPE_B),
1578 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); 1515 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
@@ -1666,16 +1603,16 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1666 I915_READ(dpll_reg) & port_mask, expected_mask); 1603 I915_READ(dpll_reg) & port_mask, expected_mask);
1667} 1604}
1668 1605
1669static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, 1606static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1670 enum pipe pipe)
1671{ 1607{
1672 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, 1608 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1673 pipe); 1609 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1610 enum pipe pipe = crtc->pipe;
1674 i915_reg_t reg; 1611 i915_reg_t reg;
1675 uint32_t val, pipeconf_val; 1612 uint32_t val, pipeconf_val;
1676 1613
1677 /* Make sure PCH DPLL is enabled */ 1614 /* Make sure PCH DPLL is enabled */
1678 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); 1615 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1679 1616
1680 /* FDI must be feeding us bits for PCH ports */ 1617 /* FDI must be feeding us bits for PCH ports */
1681 assert_fdi_tx_enabled(dev_priv, pipe); 1618 assert_fdi_tx_enabled(dev_priv, pipe);
@@ -1701,7 +1638,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1701 * here for both 8bpc and 12bpc. 1638 * here for both 8bpc and 12bpc.
1702 */ 1639 */
1703 val &= ~PIPECONF_BPC_MASK; 1640 val &= ~PIPECONF_BPC_MASK;
1704 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) 1641 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1705 val |= PIPECONF_8BPC; 1642 val |= PIPECONF_8BPC;
1706 else 1643 else
1707 val |= pipeconf_val & PIPECONF_BPC_MASK; 1644 val |= pipeconf_val & PIPECONF_BPC_MASK;
@@ -1710,7 +1647,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1710 val &= ~TRANS_INTERLACE_MASK; 1647 val &= ~TRANS_INTERLACE_MASK;
1711 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) 1648 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1712 if (HAS_PCH_IBX(dev_priv) && 1649 if (HAS_PCH_IBX(dev_priv) &&
1713 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) 1650 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1714 val |= TRANS_LEGACY_INTERLACED_ILK; 1651 val |= TRANS_LEGACY_INTERLACED_ILK;
1715 else 1652 else
1716 val |= TRANS_INTERLACED; 1653 val |= TRANS_INTERLACED;
@@ -2254,6 +2191,11 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
2254 return new_offset; 2191 return new_offset;
2255} 2192}
2256 2193
2194static bool is_surface_linear(u64 modifier, int color_plane)
2195{
2196 return modifier == DRM_FORMAT_MOD_LINEAR;
2197}
2198
2257static u32 intel_adjust_aligned_offset(int *x, int *y, 2199static u32 intel_adjust_aligned_offset(int *x, int *y,
2258 const struct drm_framebuffer *fb, 2200 const struct drm_framebuffer *fb,
2259 int color_plane, 2201 int color_plane,
@@ -2266,7 +2208,7 @@ static u32 intel_adjust_aligned_offset(int *x, int *y,
2266 2208
2267 WARN_ON(new_offset > old_offset); 2209 WARN_ON(new_offset > old_offset);
2268 2210
2269 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { 2211 if (!is_surface_linear(fb->modifier, color_plane)) {
2270 unsigned int tile_size, tile_width, tile_height; 2212 unsigned int tile_size, tile_width, tile_height;
2271 unsigned int pitch_tiles; 2213 unsigned int pitch_tiles;
2272 2214
@@ -2330,14 +2272,13 @@ static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2330 unsigned int rotation, 2272 unsigned int rotation,
2331 u32 alignment) 2273 u32 alignment)
2332{ 2274{
2333 uint64_t fb_modifier = fb->modifier;
2334 unsigned int cpp = fb->format->cpp[color_plane]; 2275 unsigned int cpp = fb->format->cpp[color_plane];
2335 u32 offset, offset_aligned; 2276 u32 offset, offset_aligned;
2336 2277
2337 if (alignment) 2278 if (alignment)
2338 alignment--; 2279 alignment--;
2339 2280
2340 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) { 2281 if (!is_surface_linear(fb->modifier, color_plane)) {
2341 unsigned int tile_size, tile_width, tile_height; 2282 unsigned int tile_size, tile_width, tile_height;
2342 unsigned int tile_rows, tiles, pitch_tiles; 2283 unsigned int tile_rows, tiles, pitch_tiles;
2343 2284
@@ -2574,7 +2515,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
2574 tile_size); 2515 tile_size);
2575 offset /= tile_size; 2516 offset /= tile_size;
2576 2517
2577 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { 2518 if (!is_surface_linear(fb->modifier, i)) {
2578 unsigned int tile_width, tile_height; 2519 unsigned int tile_width, tile_height;
2579 unsigned int pitch_tiles; 2520 unsigned int pitch_tiles;
2580 struct drm_rect r; 2521 struct drm_rect r;
@@ -2788,10 +2729,6 @@ intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2788 crtc_state->base.plane_mask |= drm_plane_mask(&plane->base); 2729 crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
2789 else 2730 else
2790 crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base); 2731 crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
2791
2792 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2793 crtc_state->base.crtc->name,
2794 crtc_state->active_planes);
2795} 2732}
2796 2733
2797static void fixup_active_planes(struct intel_crtc_state *crtc_state) 2734static void fixup_active_planes(struct intel_crtc_state *crtc_state)
@@ -2819,6 +2756,10 @@ static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
2819 struct intel_plane_state *plane_state = 2756 struct intel_plane_state *plane_state =
2820 to_intel_plane_state(plane->base.state); 2757 to_intel_plane_state(plane->base.state);
2821 2758
2759 DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
2760 plane->base.base.id, plane->base.name,
2761 crtc->base.base.id, crtc->base.name);
2762
2822 intel_set_plane_visible(crtc_state, plane_state, false); 2763 intel_set_plane_visible(crtc_state, plane_state, false);
2823 fixup_active_planes(crtc_state); 2764 fixup_active_planes(crtc_state);
2824 2765
@@ -2890,6 +2831,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2890 return; 2831 return;
2891 2832
2892valid_fb: 2833valid_fb:
2834 intel_state->base.rotation = plane_config->rotation;
2893 intel_fill_fb_ggtt_view(&intel_state->view, fb, 2835 intel_fill_fb_ggtt_view(&intel_state->view, fb,
2894 intel_state->base.rotation); 2836 intel_state->base.rotation);
2895 intel_state->color_plane[0].stride = 2837 intel_state->color_plane[0].stride =
@@ -3098,28 +3040,6 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
3098 return 0; 3040 return 0;
3099} 3041}
3100 3042
3101static int
3102skl_check_nv12_surface(struct intel_plane_state *plane_state)
3103{
3104 /* Display WA #1106 */
3105 if (plane_state->base.rotation !=
3106 (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90) &&
3107 plane_state->base.rotation != DRM_MODE_ROTATE_270)
3108 return 0;
3109
3110 /*
3111 * src coordinates are rotated here.
3112 * We check height but report it as width
3113 */
3114 if (((drm_rect_height(&plane_state->base.src) >> 16) % 4) != 0) {
3115 DRM_DEBUG_KMS("src width must be multiple "
3116 "of 4 for rotated NV12\n");
3117 return -EINVAL;
3118 }
3119
3120 return 0;
3121}
3122
3123static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) 3043static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3124{ 3044{
3125 const struct drm_framebuffer *fb = plane_state->base.fb; 3045 const struct drm_framebuffer *fb = plane_state->base.fb;
@@ -3198,9 +3118,6 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
3198 * the main surface setup depends on it. 3118 * the main surface setup depends on it.
3199 */ 3119 */
3200 if (fb->format->format == DRM_FORMAT_NV12) { 3120 if (fb->format->format == DRM_FORMAT_NV12) {
3201 ret = skl_check_nv12_surface(plane_state);
3202 if (ret)
3203 return ret;
3204 ret = skl_check_nv12_aux_surface(plane_state); 3121 ret = skl_check_nv12_aux_surface(plane_state);
3205 if (ret) 3122 if (ret)
3206 return ret; 3123 return ret;
@@ -3448,7 +3365,6 @@ static void i9xx_update_plane(struct intel_plane *plane,
3448 intel_plane_ggtt_offset(plane_state) + 3365 intel_plane_ggtt_offset(plane_state) +
3449 dspaddr_offset); 3366 dspaddr_offset);
3450 } 3367 }
3451 POSTING_READ_FW(reg);
3452 3368
3453 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 3369 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3454} 3370}
@@ -3467,7 +3383,6 @@ static void i9xx_disable_plane(struct intel_plane *plane,
3467 I915_WRITE_FW(DSPSURF(i9xx_plane), 0); 3383 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
3468 else 3384 else
3469 I915_WRITE_FW(DSPADDR(i9xx_plane), 0); 3385 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
3470 POSTING_READ_FW(DSPCNTR(i9xx_plane));
3471 3386
3472 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 3387 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3473} 3388}
@@ -3527,13 +3442,13 @@ static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3527/* 3442/*
3528 * This function detaches (aka. unbinds) unused scalers in hardware 3443 * This function detaches (aka. unbinds) unused scalers in hardware
3529 */ 3444 */
3530static void skl_detach_scalers(struct intel_crtc *intel_crtc) 3445static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
3531{ 3446{
3532 struct intel_crtc_scaler_state *scaler_state; 3447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3448 const struct intel_crtc_scaler_state *scaler_state =
3449 &crtc_state->scaler_state;
3533 int i; 3450 int i;
3534 3451
3535 scaler_state = &intel_crtc->config->scaler_state;
3536
3537 /* loop through and disable scalers that aren't in use */ 3452 /* loop through and disable scalers that aren't in use */
3538 for (i = 0; i < intel_crtc->num_scalers; i++) { 3453 for (i = 0; i < intel_crtc->num_scalers; i++) {
3539 if (!scaler_state->scalers[i].in_use) 3454 if (!scaler_state->scalers[i].in_use)
@@ -3597,29 +3512,38 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
3597 return 0; 3512 return 0;
3598} 3513}
3599 3514
3600/* 3515static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
3601 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3602 * to be already pre-multiplied. We need to add a knob (or a different
3603 * DRM_FORMAT) for user-space to configure that.
3604 */
3605static u32 skl_plane_ctl_alpha(uint32_t pixel_format)
3606{ 3516{
3607 switch (pixel_format) { 3517 if (!plane_state->base.fb->format->has_alpha)
3608 case DRM_FORMAT_ABGR8888: 3518 return PLANE_CTL_ALPHA_DISABLE;
3609 case DRM_FORMAT_ARGB8888: 3519
3520 switch (plane_state->base.pixel_blend_mode) {
3521 case DRM_MODE_BLEND_PIXEL_NONE:
3522 return PLANE_CTL_ALPHA_DISABLE;
3523 case DRM_MODE_BLEND_PREMULTI:
3610 return PLANE_CTL_ALPHA_SW_PREMULTIPLY; 3524 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3525 case DRM_MODE_BLEND_COVERAGE:
3526 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
3611 default: 3527 default:
3528 MISSING_CASE(plane_state->base.pixel_blend_mode);
3612 return PLANE_CTL_ALPHA_DISABLE; 3529 return PLANE_CTL_ALPHA_DISABLE;
3613 } 3530 }
3614} 3531}
3615 3532
3616static u32 glk_plane_color_ctl_alpha(uint32_t pixel_format) 3533static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
3617{ 3534{
3618 switch (pixel_format) { 3535 if (!plane_state->base.fb->format->has_alpha)
3619 case DRM_FORMAT_ABGR8888: 3536 return PLANE_COLOR_ALPHA_DISABLE;
3620 case DRM_FORMAT_ARGB8888: 3537
3538 switch (plane_state->base.pixel_blend_mode) {
3539 case DRM_MODE_BLEND_PIXEL_NONE:
3540 return PLANE_COLOR_ALPHA_DISABLE;
3541 case DRM_MODE_BLEND_PREMULTI:
3621 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY; 3542 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
3543 case DRM_MODE_BLEND_COVERAGE:
3544 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
3622 default: 3545 default:
3546 MISSING_CASE(plane_state->base.pixel_blend_mode);
3623 return PLANE_COLOR_ALPHA_DISABLE; 3547 return PLANE_COLOR_ALPHA_DISABLE;
3624 } 3548 }
3625} 3549}
@@ -3696,7 +3620,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3696 plane_ctl = PLANE_CTL_ENABLE; 3620 plane_ctl = PLANE_CTL_ENABLE;
3697 3621
3698 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) { 3622 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
3699 plane_ctl |= skl_plane_ctl_alpha(fb->format->format); 3623 plane_ctl |= skl_plane_ctl_alpha(plane_state);
3700 plane_ctl |= 3624 plane_ctl |=
3701 PLANE_CTL_PIPE_GAMMA_ENABLE | 3625 PLANE_CTL_PIPE_GAMMA_ENABLE |
3702 PLANE_CTL_PIPE_CSC_ENABLE | 3626 PLANE_CTL_PIPE_CSC_ENABLE |
@@ -3731,6 +3655,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
3731 struct drm_i915_private *dev_priv = 3655 struct drm_i915_private *dev_priv =
3732 to_i915(plane_state->base.plane->dev); 3656 to_i915(plane_state->base.plane->dev);
3733 const struct drm_framebuffer *fb = plane_state->base.fb; 3657 const struct drm_framebuffer *fb = plane_state->base.fb;
3658 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3734 u32 plane_color_ctl = 0; 3659 u32 plane_color_ctl = 0;
3735 3660
3736 if (INTEL_GEN(dev_priv) < 11) { 3661 if (INTEL_GEN(dev_priv) < 11) {
@@ -3738,9 +3663,9 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
3738 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE; 3663 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
3739 } 3664 }
3740 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; 3665 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
3741 plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format); 3666 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
3742 3667
3743 if (fb->format->is_yuv) { 3668 if (fb->format->is_yuv && !icl_is_hdr_plane(plane)) {
3744 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709) 3669 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3745 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; 3670 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
3746 else 3671 else
@@ -3748,6 +3673,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
3748 3673
3749 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 3674 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3750 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; 3675 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
3676 } else if (fb->format->is_yuv) {
3677 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
3751 } 3678 }
3752 3679
3753 return plane_color_ctl; 3680 return plane_color_ctl;
@@ -3932,15 +3859,15 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta
3932 3859
3933 /* on skylake this is done by detaching scalers */ 3860 /* on skylake this is done by detaching scalers */
3934 if (INTEL_GEN(dev_priv) >= 9) { 3861 if (INTEL_GEN(dev_priv) >= 9) {
3935 skl_detach_scalers(crtc); 3862 skl_detach_scalers(new_crtc_state);
3936 3863
3937 if (new_crtc_state->pch_pfit.enabled) 3864 if (new_crtc_state->pch_pfit.enabled)
3938 skylake_pfit_enable(crtc); 3865 skylake_pfit_enable(new_crtc_state);
3939 } else if (HAS_PCH_SPLIT(dev_priv)) { 3866 } else if (HAS_PCH_SPLIT(dev_priv)) {
3940 if (new_crtc_state->pch_pfit.enabled) 3867 if (new_crtc_state->pch_pfit.enabled)
3941 ironlake_pfit_enable(crtc); 3868 ironlake_pfit_enable(new_crtc_state);
3942 else if (old_crtc_state->pch_pfit.enabled) 3869 else if (old_crtc_state->pch_pfit.enabled)
3943 ironlake_pfit_disable(crtc, true); 3870 ironlake_pfit_disable(old_crtc_state);
3944 } 3871 }
3945} 3872}
3946 3873
@@ -4339,10 +4266,10 @@ train_done:
4339 DRM_DEBUG_KMS("FDI train done.\n"); 4266 DRM_DEBUG_KMS("FDI train done.\n");
4340} 4267}
4341 4268
4342static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) 4269static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
4343{ 4270{
4344 struct drm_device *dev = intel_crtc->base.dev; 4271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4345 struct drm_i915_private *dev_priv = to_i915(dev); 4272 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4346 int pipe = intel_crtc->pipe; 4273 int pipe = intel_crtc->pipe;
4347 i915_reg_t reg; 4274 i915_reg_t reg;
4348 u32 temp; 4275 u32 temp;
@@ -4351,7 +4278,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4351 reg = FDI_RX_CTL(pipe); 4278 reg = FDI_RX_CTL(pipe);
4352 temp = I915_READ(reg); 4279 temp = I915_READ(reg);
4353 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); 4280 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4354 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); 4281 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4355 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; 4282 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4356 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); 4283 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4357 4284
@@ -4500,10 +4427,11 @@ void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4500} 4427}
4501 4428
4502/* Program iCLKIP clock to the desired frequency */ 4429/* Program iCLKIP clock to the desired frequency */
4503static void lpt_program_iclkip(struct intel_crtc *crtc) 4430static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
4504{ 4431{
4432 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4505 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4433 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4506 int clock = crtc->config->base.adjusted_mode.crtc_clock; 4434 int clock = crtc_state->base.adjusted_mode.crtc_clock;
4507 u32 divsel, phaseinc, auxdiv, phasedir = 0; 4435 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4508 u32 temp; 4436 u32 temp;
4509 4437
@@ -4614,12 +4542,12 @@ int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4614 desired_divisor << auxdiv); 4542 desired_divisor << auxdiv);
4615} 4543}
4616 4544
4617static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, 4545static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
4618 enum pipe pch_transcoder) 4546 enum pipe pch_transcoder)
4619{ 4547{
4620 struct drm_device *dev = crtc->base.dev; 4548 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4621 struct drm_i915_private *dev_priv = to_i915(dev); 4549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4622 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; 4550 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4623 4551
4624 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), 4552 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4625 I915_READ(HTOTAL(cpu_transcoder))); 4553 I915_READ(HTOTAL(cpu_transcoder)));
@@ -4638,9 +4566,8 @@ static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4638 I915_READ(VSYNCSHIFT(cpu_transcoder))); 4566 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4639} 4567}
4640 4568
4641static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) 4569static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
4642{ 4570{
4643 struct drm_i915_private *dev_priv = to_i915(dev);
4644 uint32_t temp; 4571 uint32_t temp;
4645 4572
4646 temp = I915_READ(SOUTH_CHICKEN1); 4573 temp = I915_READ(SOUTH_CHICKEN1);
@@ -4659,22 +4586,23 @@ static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4659 POSTING_READ(SOUTH_CHICKEN1); 4586 POSTING_READ(SOUTH_CHICKEN1);
4660} 4587}
4661 4588
4662static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) 4589static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
4663{ 4590{
4664 struct drm_device *dev = intel_crtc->base.dev; 4591 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4592 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4665 4593
4666 switch (intel_crtc->pipe) { 4594 switch (crtc->pipe) {
4667 case PIPE_A: 4595 case PIPE_A:
4668 break; 4596 break;
4669 case PIPE_B: 4597 case PIPE_B:
4670 if (intel_crtc->config->fdi_lanes > 2) 4598 if (crtc_state->fdi_lanes > 2)
4671 cpt_set_fdi_bc_bifurcation(dev, false); 4599 cpt_set_fdi_bc_bifurcation(dev_priv, false);
4672 else 4600 else
4673 cpt_set_fdi_bc_bifurcation(dev, true); 4601 cpt_set_fdi_bc_bifurcation(dev_priv, true);
4674 4602
4675 break; 4603 break;
4676 case PIPE_C: 4604 case PIPE_C:
4677 cpt_set_fdi_bc_bifurcation(dev, true); 4605 cpt_set_fdi_bc_bifurcation(dev_priv, true);
4678 4606
4679 break; 4607 break;
4680 default: 4608 default:
@@ -4731,7 +4659,7 @@ static void ironlake_pch_enable(const struct intel_atomic_state *state,
4731 assert_pch_transcoder_disabled(dev_priv, pipe); 4659 assert_pch_transcoder_disabled(dev_priv, pipe);
4732 4660
4733 if (IS_IVYBRIDGE(dev_priv)) 4661 if (IS_IVYBRIDGE(dev_priv))
4734 ivybridge_update_fdi_bc_bifurcation(crtc); 4662 ivybridge_update_fdi_bc_bifurcation(crtc_state);
4735 4663
4736 /* Write the TU size bits before fdi link training, so that error 4664 /* Write the TU size bits before fdi link training, so that error
4737 * detection works. */ 4665 * detection works. */
@@ -4764,11 +4692,11 @@ static void ironlake_pch_enable(const struct intel_atomic_state *state,
4764 * Note that enable_shared_dpll tries to do the right thing, but 4692 * Note that enable_shared_dpll tries to do the right thing, but
4765 * get_shared_dpll unconditionally resets the pll - we need that to have 4693 * get_shared_dpll unconditionally resets the pll - we need that to have
4766 * the right LVDS enable sequence. */ 4694 * the right LVDS enable sequence. */
4767 intel_enable_shared_dpll(crtc); 4695 intel_enable_shared_dpll(crtc_state);
4768 4696
4769 /* set transcoder timing, panel must allow it */ 4697 /* set transcoder timing, panel must allow it */
4770 assert_panel_unlocked(dev_priv, pipe); 4698 assert_panel_unlocked(dev_priv, pipe);
4771 ironlake_pch_transcoder_set_timings(crtc, pipe); 4699 ironlake_pch_transcoder_set_timings(crtc_state, pipe);
4772 4700
4773 intel_fdi_normal_train(crtc); 4701 intel_fdi_normal_train(crtc);
4774 4702
@@ -4800,7 +4728,7 @@ static void ironlake_pch_enable(const struct intel_atomic_state *state,
4800 I915_WRITE(reg, temp); 4728 I915_WRITE(reg, temp);
4801 } 4729 }
4802 4730
4803 ironlake_enable_pch_transcoder(dev_priv, pipe); 4731 ironlake_enable_pch_transcoder(crtc_state);
4804} 4732}
4805 4733
4806static void lpt_pch_enable(const struct intel_atomic_state *state, 4734static void lpt_pch_enable(const struct intel_atomic_state *state,
@@ -4812,10 +4740,10 @@ static void lpt_pch_enable(const struct intel_atomic_state *state,
4812 4740
4813 assert_pch_transcoder_disabled(dev_priv, PIPE_A); 4741 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4814 4742
4815 lpt_program_iclkip(crtc); 4743 lpt_program_iclkip(crtc_state);
4816 4744
4817 /* Set transcoder timing. */ 4745 /* Set transcoder timing. */
4818 ironlake_pch_transcoder_set_timings(crtc, PIPE_A); 4746 ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A);
4819 4747
4820 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); 4748 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4821} 4749}
@@ -4850,8 +4778,31 @@ static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4850 * chroma samples for both of the luma samples, and thus we don't 4778 * chroma samples for both of the luma samples, and thus we don't
4851 * actually get the expected MPEG2 chroma siting convention :( 4779 * actually get the expected MPEG2 chroma siting convention :(
4852 * The same behaviour is observed on pre-SKL platforms as well. 4780 * The same behaviour is observed on pre-SKL platforms as well.
4781 *
4782 * Theory behind the formula (note that we ignore sub-pixel
4783 * source coordinates):
4784 * s = source sample position
4785 * d = destination sample position
4786 *
4787 * Downscaling 4:1:
4788 * -0.5
4789 * | 0.0
4790 * | | 1.5 (initial phase)
4791 * | | |
4792 * v v v
4793 * | s | s | s | s |
4794 * | d |
4795 *
4796 * Upscaling 1:4:
4797 * -0.5
4798 * | -0.375 (initial phase)
4799 * | | 0.0
4800 * | | |
4801 * v v v
4802 * | s |
4803 * | d | d | d | d |
4853 */ 4804 */
4854u16 skl_scaler_calc_phase(int sub, bool chroma_cosited) 4805u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
4855{ 4806{
4856 int phase = -0x8000; 4807 int phase = -0x8000;
4857 u16 trip = 0; 4808 u16 trip = 0;
@@ -4859,6 +4810,15 @@ u16 skl_scaler_calc_phase(int sub, bool chroma_cosited)
4859 if (chroma_cosited) 4810 if (chroma_cosited)
4860 phase += (sub - 1) * 0x8000 / sub; 4811 phase += (sub - 1) * 0x8000 / sub;
4861 4812
4813 phase += scale / (2 * sub);
4814
4815 /*
4816 * Hardware initial phase limited to [-0.5:1.5].
4817 * Since the max hardware scale factor is 3.0, we
4818 * should never actually excdeed 1.0 here.
4819 */
4820 WARN_ON(phase < -0x8000 || phase > 0x18000);
4821
4862 if (phase < 0) 4822 if (phase < 0)
4863 phase = 0x10000 + phase; 4823 phase = 0x10000 + phase;
4864 else 4824 else
@@ -4871,8 +4831,7 @@ static int
4871skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, 4831skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4872 unsigned int scaler_user, int *scaler_id, 4832 unsigned int scaler_user, int *scaler_id,
4873 int src_w, int src_h, int dst_w, int dst_h, 4833 int src_w, int src_h, int dst_w, int dst_h,
4874 bool plane_scaler_check, 4834 const struct drm_format_info *format, bool need_scaler)
4875 uint32_t pixel_format)
4876{ 4835{
4877 struct intel_crtc_scaler_state *scaler_state = 4836 struct intel_crtc_scaler_state *scaler_state =
4878 &crtc_state->scaler_state; 4837 &crtc_state->scaler_state;
@@ -4881,21 +4840,14 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4881 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); 4840 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4882 const struct drm_display_mode *adjusted_mode = 4841 const struct drm_display_mode *adjusted_mode =
4883 &crtc_state->base.adjusted_mode; 4842 &crtc_state->base.adjusted_mode;
4884 int need_scaling;
4885 4843
4886 /* 4844 /*
4887 * Src coordinates are already rotated by 270 degrees for 4845 * Src coordinates are already rotated by 270 degrees for
4888 * the 90/270 degree plane rotation cases (to match the 4846 * the 90/270 degree plane rotation cases (to match the
4889 * GTT mapping), hence no need to account for rotation here. 4847 * GTT mapping), hence no need to account for rotation here.
4890 */ 4848 */
4891 need_scaling = src_w != dst_w || src_h != dst_h; 4849 if (src_w != dst_w || src_h != dst_h)
4892 4850 need_scaler = true;
4893 if (plane_scaler_check)
4894 if (pixel_format == DRM_FORMAT_NV12)
4895 need_scaling = true;
4896
4897 if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4898 need_scaling = true;
4899 4851
4900 /* 4852 /*
4901 * Scaling/fitting not supported in IF-ID mode in GEN9+ 4853 * Scaling/fitting not supported in IF-ID mode in GEN9+
@@ -4904,7 +4856,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4904 * for NV12. 4856 * for NV12.
4905 */ 4857 */
4906 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable && 4858 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4907 need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 4859 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4908 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n"); 4860 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4909 return -EINVAL; 4861 return -EINVAL;
4910 } 4862 }
@@ -4919,7 +4871,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4919 * update to free the scaler is done in plane/panel-fit programming. 4871 * update to free the scaler is done in plane/panel-fit programming.
4920 * For this purpose crtc/plane_state->scaler_id isn't reset here. 4872 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4921 */ 4873 */
4922 if (force_detach || !need_scaling) { 4874 if (force_detach || !need_scaler) {
4923 if (*scaler_id >= 0) { 4875 if (*scaler_id >= 0) {
4924 scaler_state->scaler_users &= ~(1 << scaler_user); 4876 scaler_state->scaler_users &= ~(1 << scaler_user);
4925 scaler_state->scalers[*scaler_id].in_use = 0; 4877 scaler_state->scalers[*scaler_id].in_use = 0;
@@ -4933,7 +4885,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4933 return 0; 4885 return 0;
4934 } 4886 }
4935 4887
4936 if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 && 4888 if (format && format->format == DRM_FORMAT_NV12 &&
4937 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) { 4889 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
4938 DRM_DEBUG_KMS("NV12: src dimensions not met\n"); 4890 DRM_DEBUG_KMS("NV12: src dimensions not met\n");
4939 return -EINVAL; 4891 return -EINVAL;
@@ -4976,12 +4928,16 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4976int skl_update_scaler_crtc(struct intel_crtc_state *state) 4928int skl_update_scaler_crtc(struct intel_crtc_state *state)
4977{ 4929{
4978 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; 4930 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4931 bool need_scaler = false;
4932
4933 if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4934 need_scaler = true;
4979 4935
4980 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, 4936 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4981 &state->scaler_state.scaler_id, 4937 &state->scaler_state.scaler_id,
4982 state->pipe_src_w, state->pipe_src_h, 4938 state->pipe_src_w, state->pipe_src_h,
4983 adjusted_mode->crtc_hdisplay, 4939 adjusted_mode->crtc_hdisplay,
4984 adjusted_mode->crtc_vdisplay, false, 0); 4940 adjusted_mode->crtc_vdisplay, NULL, need_scaler);
4985} 4941}
4986 4942
4987/** 4943/**
@@ -4996,13 +4952,17 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
4996static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, 4952static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4997 struct intel_plane_state *plane_state) 4953 struct intel_plane_state *plane_state)
4998{ 4954{
4999
5000 struct intel_plane *intel_plane = 4955 struct intel_plane *intel_plane =
5001 to_intel_plane(plane_state->base.plane); 4956 to_intel_plane(plane_state->base.plane);
5002 struct drm_framebuffer *fb = plane_state->base.fb; 4957 struct drm_framebuffer *fb = plane_state->base.fb;
5003 int ret; 4958 int ret;
5004
5005 bool force_detach = !fb || !plane_state->base.visible; 4959 bool force_detach = !fb || !plane_state->base.visible;
4960 bool need_scaler = false;
4961
4962 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
4963 if (!icl_is_hdr_plane(intel_plane) &&
4964 fb && fb->format->format == DRM_FORMAT_NV12)
4965 need_scaler = true;
5006 4966
5007 ret = skl_update_scaler(crtc_state, force_detach, 4967 ret = skl_update_scaler(crtc_state, force_detach,
5008 drm_plane_index(&intel_plane->base), 4968 drm_plane_index(&intel_plane->base),
@@ -5011,7 +4971,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
5011 drm_rect_height(&plane_state->base.src) >> 16, 4971 drm_rect_height(&plane_state->base.src) >> 16,
5012 drm_rect_width(&plane_state->base.dst), 4972 drm_rect_width(&plane_state->base.dst),
5013 drm_rect_height(&plane_state->base.dst), 4973 drm_rect_height(&plane_state->base.dst),
5014 fb ? true : false, fb ? fb->format->format : 0); 4974 fb ? fb->format : NULL, need_scaler);
5015 4975
5016 if (ret || plane_state->scaler_id < 0) 4976 if (ret || plane_state->scaler_id < 0)
5017 return ret; 4977 return ret;
@@ -5057,23 +5017,30 @@ static void skylake_scaler_disable(struct intel_crtc *crtc)
5057 skl_detach_scaler(crtc, i); 5017 skl_detach_scaler(crtc, i);
5058} 5018}
5059 5019
5060static void skylake_pfit_enable(struct intel_crtc *crtc) 5020static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
5061{ 5021{
5062 struct drm_device *dev = crtc->base.dev; 5022 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5063 struct drm_i915_private *dev_priv = to_i915(dev); 5023 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5064 int pipe = crtc->pipe; 5024 enum pipe pipe = crtc->pipe;
5065 struct intel_crtc_scaler_state *scaler_state = 5025 const struct intel_crtc_scaler_state *scaler_state =
5066 &crtc->config->scaler_state; 5026 &crtc_state->scaler_state;
5067 5027
5068 if (crtc->config->pch_pfit.enabled) { 5028 if (crtc_state->pch_pfit.enabled) {
5069 u16 uv_rgb_hphase, uv_rgb_vphase; 5029 u16 uv_rgb_hphase, uv_rgb_vphase;
5030 int pfit_w, pfit_h, hscale, vscale;
5070 int id; 5031 int id;
5071 5032
5072 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) 5033 if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
5073 return; 5034 return;
5074 5035
5075 uv_rgb_hphase = skl_scaler_calc_phase(1, false); 5036 pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
5076 uv_rgb_vphase = skl_scaler_calc_phase(1, false); 5037 pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
5038
5039 hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
5040 vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
5041
5042 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
5043 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
5077 5044
5078 id = scaler_state->scaler_id; 5045 id = scaler_state->scaler_id;
5079 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | 5046 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
@@ -5082,18 +5049,18 @@ static void skylake_pfit_enable(struct intel_crtc *crtc)
5082 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase)); 5049 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
5083 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id), 5050 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
5084 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase)); 5051 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
5085 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); 5052 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
5086 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); 5053 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
5087 } 5054 }
5088} 5055}
5089 5056
5090static void ironlake_pfit_enable(struct intel_crtc *crtc) 5057static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
5091{ 5058{
5092 struct drm_device *dev = crtc->base.dev; 5059 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5093 struct drm_i915_private *dev_priv = to_i915(dev); 5060 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5094 int pipe = crtc->pipe; 5061 int pipe = crtc->pipe;
5095 5062
5096 if (crtc->config->pch_pfit.enabled) { 5063 if (crtc_state->pch_pfit.enabled) {
5097 /* Force use of hard-coded filter coefficients 5064 /* Force use of hard-coded filter coefficients
5098 * as some pre-programmed values are broken, 5065 * as some pre-programmed values are broken,
5099 * e.g. x201. 5066 * e.g. x201.
@@ -5103,8 +5070,8 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
5103 PF_PIPE_SEL_IVB(pipe)); 5070 PF_PIPE_SEL_IVB(pipe));
5104 else 5071 else
5105 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); 5072 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5106 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); 5073 I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
5107 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); 5074 I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
5108 } 5075 }
5109} 5076}
5110 5077
@@ -5299,11 +5266,8 @@ static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
5299 if (!crtc_state->nv12_planes) 5266 if (!crtc_state->nv12_planes)
5300 return false; 5267 return false;
5301 5268
5302 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) 5269 /* WA Display #0827: Gen9:all */
5303 return false; 5270 if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
5304
5305 if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
5306 IS_CANNONLAKE(dev_priv))
5307 return true; 5271 return true;
5308 5272
5309 return false; 5273 return false;
@@ -5346,7 +5310,6 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5346 if (needs_nv12_wa(dev_priv, old_crtc_state) && 5310 if (needs_nv12_wa(dev_priv, old_crtc_state) &&
5347 !needs_nv12_wa(dev_priv, pipe_config)) { 5311 !needs_nv12_wa(dev_priv, pipe_config)) {
5348 skl_wa_clkgate(dev_priv, crtc->pipe, false); 5312 skl_wa_clkgate(dev_priv, crtc->pipe, false);
5349 skl_wa_528(dev_priv, crtc->pipe, false);
5350 } 5313 }
5351} 5314}
5352 5315
@@ -5386,7 +5349,6 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5386 if (!needs_nv12_wa(dev_priv, old_crtc_state) && 5349 if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
5387 needs_nv12_wa(dev_priv, pipe_config)) { 5350 needs_nv12_wa(dev_priv, pipe_config)) {
5388 skl_wa_clkgate(dev_priv, crtc->pipe, true); 5351 skl_wa_clkgate(dev_priv, crtc->pipe, true);
5389 skl_wa_528(dev_priv, crtc->pipe, true);
5390 } 5352 }
5391 5353
5392 /* 5354 /*
@@ -5409,7 +5371,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5409 * 5371 *
5410 * WaCxSRDisabledForSpriteScaling:ivb 5372 * WaCxSRDisabledForSpriteScaling:ivb
5411 */ 5373 */
5412 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev)) 5374 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
5375 old_crtc_state->base.active)
5413 intel_wait_for_vblank(dev_priv, crtc->pipe); 5376 intel_wait_for_vblank(dev_priv, crtc->pipe);
5414 5377
5415 /* 5378 /*
@@ -5440,24 +5403,23 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5440 intel_update_watermarks(crtc); 5403 intel_update_watermarks(crtc);
5441} 5404}
5442 5405
5443static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) 5406static void intel_crtc_disable_planes(struct intel_crtc *crtc, unsigned plane_mask)
5444{ 5407{
5445 struct drm_device *dev = crtc->dev; 5408 struct drm_device *dev = crtc->base.dev;
5446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5409 struct intel_plane *plane;
5447 struct drm_plane *p; 5410 unsigned fb_bits = 0;
5448 int pipe = intel_crtc->pipe;
5449 5411
5450 intel_crtc_dpms_overlay_disable(intel_crtc); 5412 intel_crtc_dpms_overlay_disable(crtc);
5451 5413
5452 drm_for_each_plane_mask(p, dev, plane_mask) 5414 for_each_intel_plane_on_crtc(dev, crtc, plane) {
5453 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc); 5415 if (plane_mask & BIT(plane->id)) {
5416 plane->disable_plane(plane, crtc);
5454 5417
5455 /* 5418 fb_bits |= plane->frontbuffer_bit;
5456 * FIXME: Once we grow proper nuclear flip support out of this we need 5419 }
5457 * to compute the mask of flip planes precisely. For the time being 5420 }
5458 * consider this a flip to a NULL plane. 5421
5459 */ 5422 intel_frontbuffer_flip(to_i915(dev), fb_bits);
5460 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5461} 5423}
5462 5424
5463static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, 5425static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
@@ -5515,7 +5477,8 @@ static void intel_encoders_enable(struct drm_crtc *crtc,
5515 if (conn_state->crtc != crtc) 5477 if (conn_state->crtc != crtc)
5516 continue; 5478 continue;
5517 5479
5518 encoder->enable(encoder, crtc_state, conn_state); 5480 if (encoder->enable)
5481 encoder->enable(encoder, crtc_state, conn_state);
5519 intel_opregion_notify_encoder(encoder, true); 5482 intel_opregion_notify_encoder(encoder, true);
5520 } 5483 }
5521} 5484}
@@ -5536,7 +5499,8 @@ static void intel_encoders_disable(struct drm_crtc *crtc,
5536 continue; 5499 continue;
5537 5500
5538 intel_opregion_notify_encoder(encoder, false); 5501 intel_opregion_notify_encoder(encoder, false);
5539 encoder->disable(encoder, old_crtc_state, old_conn_state); 5502 if (encoder->disable)
5503 encoder->disable(encoder, old_crtc_state, old_conn_state);
5540 } 5504 }
5541} 5505}
5542 5506
@@ -5607,37 +5571,37 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5607 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 5571 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5608 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 5572 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5609 5573
5610 if (intel_crtc->config->has_pch_encoder) 5574 if (pipe_config->has_pch_encoder)
5611 intel_prepare_shared_dpll(intel_crtc); 5575 intel_prepare_shared_dpll(pipe_config);
5612 5576
5613 if (intel_crtc_has_dp_encoder(intel_crtc->config)) 5577 if (intel_crtc_has_dp_encoder(pipe_config))
5614 intel_dp_set_m_n(intel_crtc, M1_N1); 5578 intel_dp_set_m_n(pipe_config, M1_N1);
5615 5579
5616 intel_set_pipe_timings(intel_crtc); 5580 intel_set_pipe_timings(pipe_config);
5617 intel_set_pipe_src_size(intel_crtc); 5581 intel_set_pipe_src_size(pipe_config);
5618 5582
5619 if (intel_crtc->config->has_pch_encoder) { 5583 if (pipe_config->has_pch_encoder) {
5620 intel_cpu_transcoder_set_m_n(intel_crtc, 5584 intel_cpu_transcoder_set_m_n(pipe_config,
5621 &intel_crtc->config->fdi_m_n, NULL); 5585 &pipe_config->fdi_m_n, NULL);
5622 } 5586 }
5623 5587
5624 ironlake_set_pipeconf(crtc); 5588 ironlake_set_pipeconf(pipe_config);
5625 5589
5626 intel_crtc->active = true; 5590 intel_crtc->active = true;
5627 5591
5628 intel_encoders_pre_enable(crtc, pipe_config, old_state); 5592 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5629 5593
5630 if (intel_crtc->config->has_pch_encoder) { 5594 if (pipe_config->has_pch_encoder) {
5631 /* Note: FDI PLL enabling _must_ be done before we enable the 5595 /* Note: FDI PLL enabling _must_ be done before we enable the
5632 * cpu pipes, hence this is separate from all the other fdi/pch 5596 * cpu pipes, hence this is separate from all the other fdi/pch
5633 * enabling. */ 5597 * enabling. */
5634 ironlake_fdi_pll_enable(intel_crtc); 5598 ironlake_fdi_pll_enable(pipe_config);
5635 } else { 5599 } else {
5636 assert_fdi_tx_disabled(dev_priv, pipe); 5600 assert_fdi_tx_disabled(dev_priv, pipe);
5637 assert_fdi_rx_disabled(dev_priv, pipe); 5601 assert_fdi_rx_disabled(dev_priv, pipe);
5638 } 5602 }
5639 5603
5640 ironlake_pfit_enable(intel_crtc); 5604 ironlake_pfit_enable(pipe_config);
5641 5605
5642 /* 5606 /*
5643 * On ILK+ LUT must be loaded before the pipe is running but with 5607 * On ILK+ LUT must be loaded before the pipe is running but with
@@ -5646,10 +5610,10 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5646 intel_color_load_luts(&pipe_config->base); 5610 intel_color_load_luts(&pipe_config->base);
5647 5611
5648 if (dev_priv->display.initial_watermarks != NULL) 5612 if (dev_priv->display.initial_watermarks != NULL)
5649 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config); 5613 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5650 intel_enable_pipe(pipe_config); 5614 intel_enable_pipe(pipe_config);
5651 5615
5652 if (intel_crtc->config->has_pch_encoder) 5616 if (pipe_config->has_pch_encoder)
5653 ironlake_pch_enable(old_intel_state, pipe_config); 5617 ironlake_pch_enable(old_intel_state, pipe_config);
5654 5618
5655 assert_vblank_disabled(crtc); 5619 assert_vblank_disabled(crtc);
@@ -5666,7 +5630,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5666 * some interlaced HDMI modes. Let's do the double wait always 5630 * some interlaced HDMI modes. Let's do the double wait always
5667 * in case there are more corner cases we don't know about. 5631 * in case there are more corner cases we don't know about.
5668 */ 5632 */
5669 if (intel_crtc->config->has_pch_encoder) { 5633 if (pipe_config->has_pch_encoder) {
5670 intel_wait_for_vblank(dev_priv, pipe); 5634 intel_wait_for_vblank(dev_priv, pipe);
5671 intel_wait_for_vblank(dev_priv, pipe); 5635 intel_wait_for_vblank(dev_priv, pipe);
5672 } 5636 }
@@ -5700,10 +5664,9 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
5700 enum pipe pipe = crtc->pipe; 5664 enum pipe pipe = crtc->pipe;
5701 uint32_t val; 5665 uint32_t val;
5702 5666
5703 val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2); 5667 val = MBUS_DBOX_A_CREDIT(2);
5704 5668 val |= MBUS_DBOX_BW_CREDIT(1);
5705 /* Program B credit equally to all pipes */ 5669 val |= MBUS_DBOX_B_CREDIT(8);
5706 val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
5707 5670
5708 I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val); 5671 I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
5709} 5672}
@@ -5715,7 +5678,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5715 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 5678 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5679 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5717 int pipe = intel_crtc->pipe, hsw_workaround_pipe; 5680 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5718 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 5681 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5719 struct intel_atomic_state *old_intel_state = 5682 struct intel_atomic_state *old_intel_state =
5720 to_intel_atomic_state(old_state); 5683 to_intel_atomic_state(old_state);
5721 bool psl_clkgate_wa; 5684 bool psl_clkgate_wa;
@@ -5726,37 +5689,37 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5726 5689
5727 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); 5690 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5728 5691
5729 if (intel_crtc->config->shared_dpll) 5692 if (pipe_config->shared_dpll)
5730 intel_enable_shared_dpll(intel_crtc); 5693 intel_enable_shared_dpll(pipe_config);
5731 5694
5732 if (INTEL_GEN(dev_priv) >= 11) 5695 if (INTEL_GEN(dev_priv) >= 11)
5733 icl_map_plls_to_ports(crtc, pipe_config, old_state); 5696 icl_map_plls_to_ports(crtc, pipe_config, old_state);
5734 5697
5735 intel_encoders_pre_enable(crtc, pipe_config, old_state); 5698 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5736 5699
5737 if (intel_crtc_has_dp_encoder(intel_crtc->config)) 5700 if (intel_crtc_has_dp_encoder(pipe_config))
5738 intel_dp_set_m_n(intel_crtc, M1_N1); 5701 intel_dp_set_m_n(pipe_config, M1_N1);
5739 5702
5740 if (!transcoder_is_dsi(cpu_transcoder)) 5703 if (!transcoder_is_dsi(cpu_transcoder))
5741 intel_set_pipe_timings(intel_crtc); 5704 intel_set_pipe_timings(pipe_config);
5742 5705
5743 intel_set_pipe_src_size(intel_crtc); 5706 intel_set_pipe_src_size(pipe_config);
5744 5707
5745 if (cpu_transcoder != TRANSCODER_EDP && 5708 if (cpu_transcoder != TRANSCODER_EDP &&
5746 !transcoder_is_dsi(cpu_transcoder)) { 5709 !transcoder_is_dsi(cpu_transcoder)) {
5747 I915_WRITE(PIPE_MULT(cpu_transcoder), 5710 I915_WRITE(PIPE_MULT(cpu_transcoder),
5748 intel_crtc->config->pixel_multiplier - 1); 5711 pipe_config->pixel_multiplier - 1);
5749 } 5712 }
5750 5713
5751 if (intel_crtc->config->has_pch_encoder) { 5714 if (pipe_config->has_pch_encoder) {
5752 intel_cpu_transcoder_set_m_n(intel_crtc, 5715 intel_cpu_transcoder_set_m_n(pipe_config,
5753 &intel_crtc->config->fdi_m_n, NULL); 5716 &pipe_config->fdi_m_n, NULL);
5754 } 5717 }
5755 5718
5756 if (!transcoder_is_dsi(cpu_transcoder)) 5719 if (!transcoder_is_dsi(cpu_transcoder))
5757 haswell_set_pipeconf(crtc); 5720 haswell_set_pipeconf(pipe_config);
5758 5721
5759 haswell_set_pipemisc(crtc); 5722 haswell_set_pipemisc(pipe_config);
5760 5723
5761 intel_color_set_csc(&pipe_config->base); 5724 intel_color_set_csc(&pipe_config->base);
5762 5725
@@ -5764,14 +5727,14 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5764 5727
5765 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */ 5728 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5766 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) && 5729 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5767 intel_crtc->config->pch_pfit.enabled; 5730 pipe_config->pch_pfit.enabled;
5768 if (psl_clkgate_wa) 5731 if (psl_clkgate_wa)
5769 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 5732 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5770 5733
5771 if (INTEL_GEN(dev_priv) >= 9) 5734 if (INTEL_GEN(dev_priv) >= 9)
5772 skylake_pfit_enable(intel_crtc); 5735 skylake_pfit_enable(pipe_config);
5773 else 5736 else
5774 ironlake_pfit_enable(intel_crtc); 5737 ironlake_pfit_enable(pipe_config);
5775 5738
5776 /* 5739 /*
5777 * On ILK+ LUT must be loaded before the pipe is running but with 5740 * On ILK+ LUT must be loaded before the pipe is running but with
@@ -5804,10 +5767,10 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5804 if (!transcoder_is_dsi(cpu_transcoder)) 5767 if (!transcoder_is_dsi(cpu_transcoder))
5805 intel_enable_pipe(pipe_config); 5768 intel_enable_pipe(pipe_config);
5806 5769
5807 if (intel_crtc->config->has_pch_encoder) 5770 if (pipe_config->has_pch_encoder)
5808 lpt_pch_enable(old_intel_state, pipe_config); 5771 lpt_pch_enable(old_intel_state, pipe_config);
5809 5772
5810 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) 5773 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
5811 intel_ddi_set_vc_payload_alloc(pipe_config, true); 5774 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5812 5775
5813 assert_vblank_disabled(crtc); 5776 assert_vblank_disabled(crtc);
@@ -5829,15 +5792,15 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5829 } 5792 }
5830} 5793}
5831 5794
5832static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) 5795static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
5833{ 5796{
5834 struct drm_device *dev = crtc->base.dev; 5797 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5835 struct drm_i915_private *dev_priv = to_i915(dev); 5798 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5836 int pipe = crtc->pipe; 5799 enum pipe pipe = crtc->pipe;
5837 5800
5838 /* To avoid upsetting the power well on haswell only disable the pfit if 5801 /* To avoid upsetting the power well on haswell only disable the pfit if
5839 * it's in use. The hw state code will make sure we get this right. */ 5802 * it's in use. The hw state code will make sure we get this right. */
5840 if (force || crtc->config->pch_pfit.enabled) { 5803 if (old_crtc_state->pch_pfit.enabled) {
5841 I915_WRITE(PF_CTL(pipe), 0); 5804 I915_WRITE(PF_CTL(pipe), 0);
5842 I915_WRITE(PF_WIN_POS(pipe), 0); 5805 I915_WRITE(PF_WIN_POS(pipe), 0);
5843 I915_WRITE(PF_WIN_SZ(pipe), 0); 5806 I915_WRITE(PF_WIN_SZ(pipe), 0);
@@ -5868,14 +5831,14 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5868 5831
5869 intel_disable_pipe(old_crtc_state); 5832 intel_disable_pipe(old_crtc_state);
5870 5833
5871 ironlake_pfit_disable(intel_crtc, false); 5834 ironlake_pfit_disable(old_crtc_state);
5872 5835
5873 if (intel_crtc->config->has_pch_encoder) 5836 if (old_crtc_state->has_pch_encoder)
5874 ironlake_fdi_disable(crtc); 5837 ironlake_fdi_disable(crtc);
5875 5838
5876 intel_encoders_post_disable(crtc, old_crtc_state, old_state); 5839 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5877 5840
5878 if (intel_crtc->config->has_pch_encoder) { 5841 if (old_crtc_state->has_pch_encoder) {
5879 ironlake_disable_pch_transcoder(dev_priv, pipe); 5842 ironlake_disable_pch_transcoder(dev_priv, pipe);
5880 5843
5881 if (HAS_PCH_CPT(dev_priv)) { 5844 if (HAS_PCH_CPT(dev_priv)) {
@@ -5929,21 +5892,22 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5929 if (INTEL_GEN(dev_priv) >= 9) 5892 if (INTEL_GEN(dev_priv) >= 9)
5930 skylake_scaler_disable(intel_crtc); 5893 skylake_scaler_disable(intel_crtc);
5931 else 5894 else
5932 ironlake_pfit_disable(intel_crtc, false); 5895 ironlake_pfit_disable(old_crtc_state);
5933 5896
5934 intel_encoders_post_disable(crtc, old_crtc_state, old_state); 5897 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5935 5898
5936 if (INTEL_GEN(dev_priv) >= 11) 5899 if (INTEL_GEN(dev_priv) >= 11)
5937 icl_unmap_plls_to_ports(crtc, old_crtc_state, old_state); 5900 icl_unmap_plls_to_ports(crtc, old_crtc_state, old_state);
5901
5902 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5938} 5903}
5939 5904
5940static void i9xx_pfit_enable(struct intel_crtc *crtc) 5905static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
5941{ 5906{
5942 struct drm_device *dev = crtc->base.dev; 5907 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5943 struct drm_i915_private *dev_priv = to_i915(dev); 5908 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5944 struct intel_crtc_state *pipe_config = crtc->config;
5945 5909
5946 if (!pipe_config->gmch_pfit.control) 5910 if (!crtc_state->gmch_pfit.control)
5947 return; 5911 return;
5948 5912
5949 /* 5913 /*
@@ -5953,8 +5917,8 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
5953 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); 5917 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5954 assert_pipe_disabled(dev_priv, crtc->pipe); 5918 assert_pipe_disabled(dev_priv, crtc->pipe);
5955 5919
5956 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); 5920 I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios);
5957 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); 5921 I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control);
5958 5922
5959 /* Border color in case we don't scale up to the full screen. Black by 5923 /* Border color in case we don't scale up to the full screen. Black by
5960 * default, change to something else for debugging. */ 5924 * default, change to something else for debugging. */
@@ -6009,6 +5973,28 @@ enum intel_display_power_domain intel_port_to_power_domain(enum port port)
6009 } 5973 }
6010} 5974}
6011 5975
5976enum intel_display_power_domain
5977intel_aux_power_domain(struct intel_digital_port *dig_port)
5978{
5979 switch (dig_port->aux_ch) {
5980 case AUX_CH_A:
5981 return POWER_DOMAIN_AUX_A;
5982 case AUX_CH_B:
5983 return POWER_DOMAIN_AUX_B;
5984 case AUX_CH_C:
5985 return POWER_DOMAIN_AUX_C;
5986 case AUX_CH_D:
5987 return POWER_DOMAIN_AUX_D;
5988 case AUX_CH_E:
5989 return POWER_DOMAIN_AUX_E;
5990 case AUX_CH_F:
5991 return POWER_DOMAIN_AUX_F;
5992 default:
5993 MISSING_CASE(dig_port->aux_ch);
5994 return POWER_DOMAIN_AUX_A;
5995 }
5996}
5997
6012static u64 get_crtc_power_domains(struct drm_crtc *crtc, 5998static u64 get_crtc_power_domains(struct drm_crtc *crtc,
6013 struct intel_crtc_state *crtc_state) 5999 struct intel_crtc_state *crtc_state)
6014{ 6000{
@@ -6088,20 +6074,18 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6088 if (WARN_ON(intel_crtc->active)) 6074 if (WARN_ON(intel_crtc->active))
6089 return; 6075 return;
6090 6076
6091 if (intel_crtc_has_dp_encoder(intel_crtc->config)) 6077 if (intel_crtc_has_dp_encoder(pipe_config))
6092 intel_dp_set_m_n(intel_crtc, M1_N1); 6078 intel_dp_set_m_n(pipe_config, M1_N1);
6093 6079
6094 intel_set_pipe_timings(intel_crtc); 6080 intel_set_pipe_timings(pipe_config);
6095 intel_set_pipe_src_size(intel_crtc); 6081 intel_set_pipe_src_size(pipe_config);
6096 6082
6097 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 6083 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6098 struct drm_i915_private *dev_priv = to_i915(dev);
6099
6100 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); 6084 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6101 I915_WRITE(CHV_CANVAS(pipe), 0); 6085 I915_WRITE(CHV_CANVAS(pipe), 0);
6102 } 6086 }
6103 6087
6104 i9xx_set_pipeconf(intel_crtc); 6088 i9xx_set_pipeconf(pipe_config);
6105 6089
6106 intel_color_set_csc(&pipe_config->base); 6090 intel_color_set_csc(&pipe_config->base);
6107 6091
@@ -6112,16 +6096,16 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6112 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); 6096 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6113 6097
6114 if (IS_CHERRYVIEW(dev_priv)) { 6098 if (IS_CHERRYVIEW(dev_priv)) {
6115 chv_prepare_pll(intel_crtc, intel_crtc->config); 6099 chv_prepare_pll(intel_crtc, pipe_config);
6116 chv_enable_pll(intel_crtc, intel_crtc->config); 6100 chv_enable_pll(intel_crtc, pipe_config);
6117 } else { 6101 } else {
6118 vlv_prepare_pll(intel_crtc, intel_crtc->config); 6102 vlv_prepare_pll(intel_crtc, pipe_config);
6119 vlv_enable_pll(intel_crtc, intel_crtc->config); 6103 vlv_enable_pll(intel_crtc, pipe_config);
6120 } 6104 }
6121 6105
6122 intel_encoders_pre_enable(crtc, pipe_config, old_state); 6106 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6123 6107
6124 i9xx_pfit_enable(intel_crtc); 6108 i9xx_pfit_enable(pipe_config);
6125 6109
6126 intel_color_load_luts(&pipe_config->base); 6110 intel_color_load_luts(&pipe_config->base);
6127 6111
@@ -6135,13 +6119,13 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6135 intel_encoders_enable(crtc, pipe_config, old_state); 6119 intel_encoders_enable(crtc, pipe_config, old_state);
6136} 6120}
6137 6121
6138static void i9xx_set_pll_dividers(struct intel_crtc *crtc) 6122static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
6139{ 6123{
6140 struct drm_device *dev = crtc->base.dev; 6124 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6141 struct drm_i915_private *dev_priv = to_i915(dev); 6125 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6142 6126
6143 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); 6127 I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
6144 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); 6128 I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
6145} 6129}
6146 6130
6147static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, 6131static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
@@ -6158,15 +6142,15 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6158 if (WARN_ON(intel_crtc->active)) 6142 if (WARN_ON(intel_crtc->active))
6159 return; 6143 return;
6160 6144
6161 i9xx_set_pll_dividers(intel_crtc); 6145 i9xx_set_pll_dividers(pipe_config);
6162 6146
6163 if (intel_crtc_has_dp_encoder(intel_crtc->config)) 6147 if (intel_crtc_has_dp_encoder(pipe_config))
6164 intel_dp_set_m_n(intel_crtc, M1_N1); 6148 intel_dp_set_m_n(pipe_config, M1_N1);
6165 6149
6166 intel_set_pipe_timings(intel_crtc); 6150 intel_set_pipe_timings(pipe_config);
6167 intel_set_pipe_src_size(intel_crtc); 6151 intel_set_pipe_src_size(pipe_config);
6168 6152
6169 i9xx_set_pipeconf(intel_crtc); 6153 i9xx_set_pipeconf(pipe_config);
6170 6154
6171 intel_crtc->active = true; 6155 intel_crtc->active = true;
6172 6156
@@ -6177,13 +6161,13 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6177 6161
6178 i9xx_enable_pll(intel_crtc, pipe_config); 6162 i9xx_enable_pll(intel_crtc, pipe_config);
6179 6163
6180 i9xx_pfit_enable(intel_crtc); 6164 i9xx_pfit_enable(pipe_config);
6181 6165
6182 intel_color_load_luts(&pipe_config->base); 6166 intel_color_load_luts(&pipe_config->base);
6183 6167
6184 if (dev_priv->display.initial_watermarks != NULL) 6168 if (dev_priv->display.initial_watermarks != NULL)
6185 dev_priv->display.initial_watermarks(old_intel_state, 6169 dev_priv->display.initial_watermarks(old_intel_state,
6186 intel_crtc->config); 6170 pipe_config);
6187 else 6171 else
6188 intel_update_watermarks(intel_crtc); 6172 intel_update_watermarks(intel_crtc);
6189 intel_enable_pipe(pipe_config); 6173 intel_enable_pipe(pipe_config);
@@ -6194,12 +6178,12 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6194 intel_encoders_enable(crtc, pipe_config, old_state); 6178 intel_encoders_enable(crtc, pipe_config, old_state);
6195} 6179}
6196 6180
6197static void i9xx_pfit_disable(struct intel_crtc *crtc) 6181static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6198{ 6182{
6199 struct drm_device *dev = crtc->base.dev; 6183 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
6200 struct drm_i915_private *dev_priv = to_i915(dev); 6184 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6201 6185
6202 if (!crtc->config->gmch_pfit.control) 6186 if (!old_crtc_state->gmch_pfit.control)
6203 return; 6187 return;
6204 6188
6205 assert_pipe_disabled(dev_priv, crtc->pipe); 6189 assert_pipe_disabled(dev_priv, crtc->pipe);
@@ -6232,17 +6216,17 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6232 6216
6233 intel_disable_pipe(old_crtc_state); 6217 intel_disable_pipe(old_crtc_state);
6234 6218
6235 i9xx_pfit_disable(intel_crtc); 6219 i9xx_pfit_disable(old_crtc_state);
6236 6220
6237 intel_encoders_post_disable(crtc, old_crtc_state, old_state); 6221 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6238 6222
6239 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { 6223 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
6240 if (IS_CHERRYVIEW(dev_priv)) 6224 if (IS_CHERRYVIEW(dev_priv))
6241 chv_disable_pll(dev_priv, pipe); 6225 chv_disable_pll(dev_priv, pipe);
6242 else if (IS_VALLEYVIEW(dev_priv)) 6226 else if (IS_VALLEYVIEW(dev_priv))
6243 vlv_disable_pll(dev_priv, pipe); 6227 vlv_disable_pll(dev_priv, pipe);
6244 else 6228 else
6245 i9xx_disable_pll(intel_crtc); 6229 i9xx_disable_pll(old_crtc_state);
6246 } 6230 }
6247 6231
6248 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); 6232 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
@@ -6316,7 +6300,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
6316 6300
6317 intel_fbc_disable(intel_crtc); 6301 intel_fbc_disable(intel_crtc);
6318 intel_update_watermarks(intel_crtc); 6302 intel_update_watermarks(intel_crtc);
6319 intel_disable_shared_dpll(intel_crtc); 6303 intel_disable_shared_dpll(to_intel_crtc_state(crtc->state));
6320 6304
6321 domains = intel_crtc->enabled_power_domains; 6305 domains = intel_crtc->enabled_power_domains;
6322 for_each_power_domain(domain, domains) 6306 for_each_power_domain(domain, domains)
@@ -6394,66 +6378,6 @@ static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
6394 } 6378 }
6395} 6379}
6396 6380
6397int intel_connector_init(struct intel_connector *connector)
6398{
6399 struct intel_digital_connector_state *conn_state;
6400
6401 /*
6402 * Allocate enough memory to hold intel_digital_connector_state,
6403 * This might be a few bytes too many, but for connectors that don't
6404 * need it we'll free the state and allocate a smaller one on the first
6405 * succesful commit anyway.
6406 */
6407 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6408 if (!conn_state)
6409 return -ENOMEM;
6410
6411 __drm_atomic_helper_connector_reset(&connector->base,
6412 &conn_state->base);
6413
6414 return 0;
6415}
6416
6417struct intel_connector *intel_connector_alloc(void)
6418{
6419 struct intel_connector *connector;
6420
6421 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6422 if (!connector)
6423 return NULL;
6424
6425 if (intel_connector_init(connector) < 0) {
6426 kfree(connector);
6427 return NULL;
6428 }
6429
6430 return connector;
6431}
6432
6433/*
6434 * Free the bits allocated by intel_connector_alloc.
6435 * This should only be used after intel_connector_alloc has returned
6436 * successfully, and before drm_connector_init returns successfully.
6437 * Otherwise the destroy callbacks for the connector and the state should
6438 * take care of proper cleanup/free
6439 */
6440void intel_connector_free(struct intel_connector *connector)
6441{
6442 kfree(to_intel_digital_connector_state(connector->base.state));
6443 kfree(connector);
6444}
6445
6446/* Simple connector->get_hw_state implementation for encoders that support only
6447 * one connector and no cloning and hence the encoder state determines the state
6448 * of the connector. */
6449bool intel_connector_get_hw_state(struct intel_connector *connector)
6450{
6451 enum pipe pipe = 0;
6452 struct intel_encoder *encoder = connector->encoder;
6453
6454 return encoder->get_hw_state(encoder, &pipe);
6455}
6456
6457static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) 6381static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6458{ 6382{
6459 if (crtc_state->base.enable && crtc_state->has_pch_encoder) 6383 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
@@ -6564,6 +6488,9 @@ retry:
6564 link_bw, &pipe_config->fdi_m_n, false); 6488 link_bw, &pipe_config->fdi_m_n, false);
6565 6489
6566 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); 6490 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6491 if (ret == -EDEADLK)
6492 return ret;
6493
6567 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { 6494 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6568 pipe_config->pipe_bpp -= 2*3; 6495 pipe_config->pipe_bpp -= 2*3;
6569 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", 6496 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
@@ -6720,7 +6647,9 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
6720 return -EINVAL; 6647 return -EINVAL;
6721 } 6648 }
6722 6649
6723 if (pipe_config->ycbcr420 && pipe_config->base.ctm) { 6650 if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
6651 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
6652 pipe_config->base.ctm) {
6724 /* 6653 /*
6725 * There is only one pipe CSC unit per pipe, and we need that 6654 * There is only one pipe CSC unit per pipe, and we need that
6726 * for output conversion from RGB->YCBCR. So if CTM is already 6655 * for output conversion from RGB->YCBCR. So if CTM is already
@@ -6886,12 +6815,12 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6886 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); 6815 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6887} 6816}
6888 6817
6889static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, 6818static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
6890 struct intel_link_m_n *m_n) 6819 const struct intel_link_m_n *m_n)
6891{ 6820{
6892 struct drm_device *dev = crtc->base.dev; 6821 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6893 struct drm_i915_private *dev_priv = to_i915(dev); 6822 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6894 int pipe = crtc->pipe; 6823 enum pipe pipe = crtc->pipe;
6895 6824
6896 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); 6825 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6897 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); 6826 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
@@ -6899,25 +6828,39 @@ static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6899 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); 6828 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6900} 6829}
6901 6830
6902static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, 6831static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
6903 struct intel_link_m_n *m_n, 6832 enum transcoder transcoder)
6904 struct intel_link_m_n *m2_n2)
6905{ 6833{
6834 if (IS_HASWELL(dev_priv))
6835 return transcoder == TRANSCODER_EDP;
6836
6837 /*
6838 * Strictly speaking some registers are available before
6839 * gen7, but we only support DRRS on gen7+
6840 */
6841 return IS_GEN7(dev_priv) || IS_CHERRYVIEW(dev_priv);
6842}
6843
6844static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
6845 const struct intel_link_m_n *m_n,
6846 const struct intel_link_m_n *m2_n2)
6847{
6848 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6906 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6849 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6907 int pipe = crtc->pipe; 6850 enum pipe pipe = crtc->pipe;
6908 enum transcoder transcoder = crtc->config->cpu_transcoder; 6851 enum transcoder transcoder = crtc_state->cpu_transcoder;
6909 6852
6910 if (INTEL_GEN(dev_priv) >= 5) { 6853 if (INTEL_GEN(dev_priv) >= 5) {
6911 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); 6854 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6912 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); 6855 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6913 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); 6856 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6914 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); 6857 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6915 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available 6858 /*
6916 * for gen < 8) and if DRRS is supported (to make sure the 6859 * M2_N2 registers are set only if DRRS is supported
6917 * registers are not unnecessarily accessed). 6860 * (to make sure the registers are not unnecessarily accessed).
6918 */ 6861 */
6919 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) || 6862 if (m2_n2 && crtc_state->has_drrs &&
6920 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { 6863 transcoder_has_m2_n2(dev_priv, transcoder)) {
6921 I915_WRITE(PIPE_DATA_M2(transcoder), 6864 I915_WRITE(PIPE_DATA_M2(transcoder),
6922 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); 6865 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6923 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); 6866 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
@@ -6932,29 +6875,29 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6932 } 6875 }
6933} 6876}
6934 6877
6935void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) 6878void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
6936{ 6879{
6937 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; 6880 const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6938 6881
6939 if (m_n == M1_N1) { 6882 if (m_n == M1_N1) {
6940 dp_m_n = &crtc->config->dp_m_n; 6883 dp_m_n = &crtc_state->dp_m_n;
6941 dp_m2_n2 = &crtc->config->dp_m2_n2; 6884 dp_m2_n2 = &crtc_state->dp_m2_n2;
6942 } else if (m_n == M2_N2) { 6885 } else if (m_n == M2_N2) {
6943 6886
6944 /* 6887 /*
6945 * M2_N2 registers are not supported. Hence m2_n2 divider value 6888 * M2_N2 registers are not supported. Hence m2_n2 divider value
6946 * needs to be programmed into M1_N1. 6889 * needs to be programmed into M1_N1.
6947 */ 6890 */
6948 dp_m_n = &crtc->config->dp_m2_n2; 6891 dp_m_n = &crtc_state->dp_m2_n2;
6949 } else { 6892 } else {
6950 DRM_ERROR("Unsupported divider value\n"); 6893 DRM_ERROR("Unsupported divider value\n");
6951 return; 6894 return;
6952 } 6895 }
6953 6896
6954 if (crtc->config->has_pch_encoder) 6897 if (crtc_state->has_pch_encoder)
6955 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); 6898 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
6956 else 6899 else
6957 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); 6900 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
6958} 6901}
6959 6902
6960static void vlv_compute_dpll(struct intel_crtc *crtc, 6903static void vlv_compute_dpll(struct intel_crtc *crtc,
@@ -7053,8 +6996,8 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
7053 6996
7054 /* Set HBR and RBR LPF coefficients */ 6997 /* Set HBR and RBR LPF coefficients */
7055 if (pipe_config->port_clock == 162000 || 6998 if (pipe_config->port_clock == 162000 ||
7056 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || 6999 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
7057 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) 7000 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
7058 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 7001 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7059 0x009f0003); 7002 0x009f0003);
7060 else 7003 else
@@ -7081,7 +7024,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
7081 7024
7082 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); 7025 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7083 coreclk = (coreclk & 0x0000ff00) | 0x01c00000; 7026 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7084 if (intel_crtc_has_dp_encoder(crtc->config)) 7027 if (intel_crtc_has_dp_encoder(pipe_config))
7085 coreclk |= 0x01000000; 7028 coreclk |= 0x01000000;
7086 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); 7029 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7087 7030
@@ -7360,12 +7303,13 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
7360 crtc_state->dpll_hw_state.dpll = dpll; 7303 crtc_state->dpll_hw_state.dpll = dpll;
7361} 7304}
7362 7305
7363static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) 7306static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
7364{ 7307{
7365 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); 7308 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7366 enum pipe pipe = intel_crtc->pipe; 7309 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7367 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 7310 enum pipe pipe = crtc->pipe;
7368 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 7311 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
7312 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
7369 uint32_t crtc_vtotal, crtc_vblank_end; 7313 uint32_t crtc_vtotal, crtc_vblank_end;
7370 int vsyncshift = 0; 7314 int vsyncshift = 0;
7371 7315
@@ -7379,7 +7323,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7379 crtc_vtotal -= 1; 7323 crtc_vtotal -= 1;
7380 crtc_vblank_end -= 1; 7324 crtc_vblank_end -= 1;
7381 7325
7382 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) 7326 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
7383 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 7327 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7384 else 7328 else
7385 vsyncshift = adjusted_mode->crtc_hsync_start - 7329 vsyncshift = adjusted_mode->crtc_hsync_start -
@@ -7421,18 +7365,18 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7421 7365
7422} 7366}
7423 7367
7424static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) 7368static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
7425{ 7369{
7426 struct drm_device *dev = intel_crtc->base.dev; 7370 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7427 struct drm_i915_private *dev_priv = to_i915(dev); 7371 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7428 enum pipe pipe = intel_crtc->pipe; 7372 enum pipe pipe = crtc->pipe;
7429 7373
7430 /* pipesrc controls the size that is scaled from, which should 7374 /* pipesrc controls the size that is scaled from, which should
7431 * always be the user's requested size. 7375 * always be the user's requested size.
7432 */ 7376 */
7433 I915_WRITE(PIPESRC(pipe), 7377 I915_WRITE(PIPESRC(pipe),
7434 ((intel_crtc->config->pipe_src_w - 1) << 16) | 7378 ((crtc_state->pipe_src_w - 1) << 16) |
7435 (intel_crtc->config->pipe_src_h - 1)); 7379 (crtc_state->pipe_src_h - 1));
7436} 7380}
7437 7381
7438static void intel_get_pipe_timings(struct intel_crtc *crtc, 7382static void intel_get_pipe_timings(struct intel_crtc *crtc,
@@ -7508,29 +7452,30 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7508 drm_mode_set_name(mode); 7452 drm_mode_set_name(mode);
7509} 7453}
7510 7454
7511static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) 7455static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
7512{ 7456{
7513 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); 7457 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7458 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7514 uint32_t pipeconf; 7459 uint32_t pipeconf;
7515 7460
7516 pipeconf = 0; 7461 pipeconf = 0;
7517 7462
7518 /* we keep both pipes enabled on 830 */ 7463 /* we keep both pipes enabled on 830 */
7519 if (IS_I830(dev_priv)) 7464 if (IS_I830(dev_priv))
7520 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; 7465 pipeconf |= I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
7521 7466
7522 if (intel_crtc->config->double_wide) 7467 if (crtc_state->double_wide)
7523 pipeconf |= PIPECONF_DOUBLE_WIDE; 7468 pipeconf |= PIPECONF_DOUBLE_WIDE;
7524 7469
7525 /* only g4x and later have fancy bpc/dither controls */ 7470 /* only g4x and later have fancy bpc/dither controls */
7526 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 7471 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7527 IS_CHERRYVIEW(dev_priv)) { 7472 IS_CHERRYVIEW(dev_priv)) {
7528 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 7473 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7529 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) 7474 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
7530 pipeconf |= PIPECONF_DITHER_EN | 7475 pipeconf |= PIPECONF_DITHER_EN |
7531 PIPECONF_DITHER_TYPE_SP; 7476 PIPECONF_DITHER_TYPE_SP;
7532 7477
7533 switch (intel_crtc->config->pipe_bpp) { 7478 switch (crtc_state->pipe_bpp) {
7534 case 18: 7479 case 18:
7535 pipeconf |= PIPECONF_6BPC; 7480 pipeconf |= PIPECONF_6BPC;
7536 break; 7481 break;
@@ -7546,9 +7491,9 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7546 } 7491 }
7547 } 7492 }
7548 7493
7549 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 7494 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7550 if (INTEL_GEN(dev_priv) < 4 || 7495 if (INTEL_GEN(dev_priv) < 4 ||
7551 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) 7496 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
7552 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 7497 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7553 else 7498 else
7554 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; 7499 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
@@ -7556,11 +7501,11 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7556 pipeconf |= PIPECONF_PROGRESSIVE; 7501 pipeconf |= PIPECONF_PROGRESSIVE;
7557 7502
7558 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 7503 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7559 intel_crtc->config->limited_color_range) 7504 crtc_state->limited_color_range)
7560 pipeconf |= PIPECONF_COLOR_RANGE_SELECT; 7505 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7561 7506
7562 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); 7507 I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
7563 POSTING_READ(PIPECONF(intel_crtc->pipe)); 7508 POSTING_READ(PIPECONF(crtc->pipe));
7564} 7509}
7565 7510
7566static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, 7511static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
@@ -7843,8 +7788,15 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7843 plane_config->tiling = I915_TILING_X; 7788 plane_config->tiling = I915_TILING_X;
7844 fb->modifier = I915_FORMAT_MOD_X_TILED; 7789 fb->modifier = I915_FORMAT_MOD_X_TILED;
7845 } 7790 }
7791
7792 if (val & DISPPLANE_ROTATE_180)
7793 plane_config->rotation = DRM_MODE_ROTATE_180;
7846 } 7794 }
7847 7795
7796 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
7797 val & DISPPLANE_MIRROR)
7798 plane_config->rotation |= DRM_MODE_REFLECT_X;
7799
7848 pixel_format = val & DISPPLANE_PIXFORMAT_MASK; 7800 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7849 fourcc = i9xx_format_to_fourcc(pixel_format); 7801 fourcc = i9xx_format_to_fourcc(pixel_format);
7850 fb->format = drm_format_info(fourcc); 7802 fb->format = drm_format_info(fourcc);
@@ -7916,6 +7868,49 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
7916 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 7868 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7917} 7869}
7918 7870
7871static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc,
7872 struct intel_crtc_state *pipe_config)
7873{
7874 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7875 enum intel_output_format output = INTEL_OUTPUT_FORMAT_RGB;
7876
7877 pipe_config->lspcon_downsampling = false;
7878
7879 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
7880 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
7881
7882 if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
7883 bool ycbcr420_enabled = tmp & PIPEMISC_YUV420_ENABLE;
7884 bool blend = tmp & PIPEMISC_YUV420_MODE_FULL_BLEND;
7885
7886 if (ycbcr420_enabled) {
7887 /* We support 4:2:0 in full blend mode only */
7888 if (!blend)
7889 output = INTEL_OUTPUT_FORMAT_INVALID;
7890 else if (!(IS_GEMINILAKE(dev_priv) ||
7891 INTEL_GEN(dev_priv) >= 10))
7892 output = INTEL_OUTPUT_FORMAT_INVALID;
7893 else
7894 output = INTEL_OUTPUT_FORMAT_YCBCR420;
7895 } else {
7896 /*
7897 * Currently there is no interface defined to
7898 * check user preference between RGB/YCBCR444
7899 * or YCBCR420. So the only possible case for
7900 * YCBCR444 usage is driving YCBCR420 output
7901 * with LSPCON, when pipe is configured for
7902 * YCBCR444 output and LSPCON takes care of
7903 * downsampling it.
7904 */
7905 pipe_config->lspcon_downsampling = true;
7906 output = INTEL_OUTPUT_FORMAT_YCBCR444;
7907 }
7908 }
7909 }
7910
7911 pipe_config->output_format = output;
7912}
7913
7919static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 7914static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7920 struct intel_crtc_state *pipe_config) 7915 struct intel_crtc_state *pipe_config)
7921{ 7916{
@@ -7928,6 +7923,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7928 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 7923 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7929 return false; 7924 return false;
7930 7925
7926 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
7931 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 7927 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7932 pipe_config->shared_dpll = NULL; 7928 pipe_config->shared_dpll = NULL;
7933 7929
@@ -8459,16 +8455,16 @@ void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8459 lpt_init_pch_refclk(dev_priv); 8455 lpt_init_pch_refclk(dev_priv);
8460} 8456}
8461 8457
8462static void ironlake_set_pipeconf(struct drm_crtc *crtc) 8458static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
8463{ 8459{
8464 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 8460 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 8461 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8466 int pipe = intel_crtc->pipe; 8462 enum pipe pipe = crtc->pipe;
8467 uint32_t val; 8463 uint32_t val;
8468 8464
8469 val = 0; 8465 val = 0;
8470 8466
8471 switch (intel_crtc->config->pipe_bpp) { 8467 switch (crtc_state->pipe_bpp) {
8472 case 18: 8468 case 18:
8473 val |= PIPECONF_6BPC; 8469 val |= PIPECONF_6BPC;
8474 break; 8470 break;
@@ -8486,32 +8482,32 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8486 BUG(); 8482 BUG();
8487 } 8483 }
8488 8484
8489 if (intel_crtc->config->dither) 8485 if (crtc_state->dither)
8490 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); 8486 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8491 8487
8492 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 8488 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8493 val |= PIPECONF_INTERLACED_ILK; 8489 val |= PIPECONF_INTERLACED_ILK;
8494 else 8490 else
8495 val |= PIPECONF_PROGRESSIVE; 8491 val |= PIPECONF_PROGRESSIVE;
8496 8492
8497 if (intel_crtc->config->limited_color_range) 8493 if (crtc_state->limited_color_range)
8498 val |= PIPECONF_COLOR_RANGE_SELECT; 8494 val |= PIPECONF_COLOR_RANGE_SELECT;
8499 8495
8500 I915_WRITE(PIPECONF(pipe), val); 8496 I915_WRITE(PIPECONF(pipe), val);
8501 POSTING_READ(PIPECONF(pipe)); 8497 POSTING_READ(PIPECONF(pipe));
8502} 8498}
8503 8499
8504static void haswell_set_pipeconf(struct drm_crtc *crtc) 8500static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
8505{ 8501{
8506 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 8502 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 8503 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8508 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 8504 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8509 u32 val = 0; 8505 u32 val = 0;
8510 8506
8511 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) 8507 if (IS_HASWELL(dev_priv) && crtc_state->dither)
8512 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); 8508 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8513 8509
8514 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 8510 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8515 val |= PIPECONF_INTERLACED_ILK; 8511 val |= PIPECONF_INTERLACED_ILK;
8516 else 8512 else
8517 val |= PIPECONF_PROGRESSIVE; 8513 val |= PIPECONF_PROGRESSIVE;
@@ -8520,16 +8516,15 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
8520 POSTING_READ(PIPECONF(cpu_transcoder)); 8516 POSTING_READ(PIPECONF(cpu_transcoder));
8521} 8517}
8522 8518
8523static void haswell_set_pipemisc(struct drm_crtc *crtc) 8519static void haswell_set_pipemisc(const struct intel_crtc_state *crtc_state)
8524{ 8520{
8525 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 8521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
8526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 8522 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8527 struct intel_crtc_state *config = intel_crtc->config;
8528 8523
8529 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) { 8524 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
8530 u32 val = 0; 8525 u32 val = 0;
8531 8526
8532 switch (intel_crtc->config->pipe_bpp) { 8527 switch (crtc_state->pipe_bpp) {
8533 case 18: 8528 case 18:
8534 val |= PIPEMISC_DITHER_6_BPC; 8529 val |= PIPEMISC_DITHER_6_BPC;
8535 break; 8530 break;
@@ -8547,14 +8542,16 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc)
8547 BUG(); 8542 BUG();
8548 } 8543 }
8549 8544
8550 if (intel_crtc->config->dither) 8545 if (crtc_state->dither)
8551 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; 8546 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8552 8547
8553 if (config->ycbcr420) { 8548 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
8554 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV | 8549 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
8555 PIPEMISC_YUV420_ENABLE | 8550 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
8551
8552 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
8553 val |= PIPEMISC_YUV420_ENABLE |
8556 PIPEMISC_YUV420_MODE_FULL_BLEND; 8554 PIPEMISC_YUV420_MODE_FULL_BLEND;
8557 }
8558 8555
8559 I915_WRITE(PIPEMISC(intel_crtc->pipe), val); 8556 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8560 } 8557 }
@@ -8765,12 +8762,8 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8765 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); 8762 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8766 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) 8763 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8767 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; 8764 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8768 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for 8765
8769 * gen < 8) and if DRRS is supported (to make sure the 8766 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
8770 * registers are not unnecessarily read).
8771 */
8772 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8773 crtc->config->has_drrs) {
8774 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); 8767 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8775 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); 8768 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8776 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) 8769 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
@@ -8913,6 +8906,29 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
8913 goto error; 8906 goto error;
8914 } 8907 }
8915 8908
8909 /*
8910 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
8911 * while i915 HW rotation is clockwise, thats why this swapping.
8912 */
8913 switch (val & PLANE_CTL_ROTATE_MASK) {
8914 case PLANE_CTL_ROTATE_0:
8915 plane_config->rotation = DRM_MODE_ROTATE_0;
8916 break;
8917 case PLANE_CTL_ROTATE_90:
8918 plane_config->rotation = DRM_MODE_ROTATE_270;
8919 break;
8920 case PLANE_CTL_ROTATE_180:
8921 plane_config->rotation = DRM_MODE_ROTATE_180;
8922 break;
8923 case PLANE_CTL_ROTATE_270:
8924 plane_config->rotation = DRM_MODE_ROTATE_90;
8925 break;
8926 }
8927
8928 if (INTEL_GEN(dev_priv) >= 10 &&
8929 val & PLANE_CTL_FLIP_HORIZONTAL)
8930 plane_config->rotation |= DRM_MODE_REFLECT_X;
8931
8916 base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000; 8932 base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
8917 plane_config->base = base; 8933 plane_config->base = base;
8918 8934
@@ -8979,6 +8995,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8979 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 8995 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8980 return false; 8996 return false;
8981 8997
8998 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
8982 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 8999 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8983 pipe_config->shared_dpll = NULL; 9000 pipe_config->shared_dpll = NULL;
8984 9001
@@ -9327,30 +9344,17 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
9327 u32 temp; 9344 u32 temp;
9328 9345
9329 /* TODO: TBT pll not implemented. */ 9346 /* TODO: TBT pll not implemented. */
9330 switch (port) { 9347 if (intel_port_is_combophy(dev_priv, port)) {
9331 case PORT_A:
9332 case PORT_B:
9333 temp = I915_READ(DPCLKA_CFGCR0_ICL) & 9348 temp = I915_READ(DPCLKA_CFGCR0_ICL) &
9334 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); 9349 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9335 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port); 9350 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9336 9351
9337 if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1)) 9352 if (WARN_ON(!intel_dpll_is_combophy(id)))
9338 return; 9353 return;
9339 break; 9354 } else if (intel_port_is_tc(dev_priv, port)) {
9340 case PORT_C: 9355 id = icl_port_to_mg_pll_id(port);
9341 id = DPLL_ID_ICL_MGPLL1; 9356 } else {
9342 break; 9357 WARN(1, "Invalid port %x\n", port);
9343 case PORT_D:
9344 id = DPLL_ID_ICL_MGPLL2;
9345 break;
9346 case PORT_E:
9347 id = DPLL_ID_ICL_MGPLL3;
9348 break;
9349 case PORT_F:
9350 id = DPLL_ID_ICL_MGPLL4;
9351 break;
9352 default:
9353 MISSING_CASE(port);
9354 return; 9358 return;
9355 } 9359 }
9356 9360
@@ -9613,27 +9617,11 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9613 } 9617 }
9614 9618
9615 intel_get_pipe_src_size(crtc, pipe_config); 9619 intel_get_pipe_src_size(crtc, pipe_config);
9620 intel_get_crtc_ycbcr_config(crtc, pipe_config);
9616 9621
9617 pipe_config->gamma_mode = 9622 pipe_config->gamma_mode =
9618 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; 9623 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9619 9624
9620 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
9621 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9622 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9623
9624 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
9625 bool blend_mode_420 = tmp &
9626 PIPEMISC_YUV420_MODE_FULL_BLEND;
9627
9628 pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9629 if (pipe_config->ycbcr420 != clrspace_yuv ||
9630 pipe_config->ycbcr420 != blend_mode_420)
9631 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9632 } else if (clrspace_yuv) {
9633 DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9634 }
9635 }
9636
9637 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); 9625 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9638 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { 9626 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9639 power_domain_mask |= BIT_ULL(power_domain); 9627 power_domain_mask |= BIT_ULL(power_domain);
@@ -9902,8 +9890,6 @@ static void i845_update_cursor(struct intel_plane *plane,
9902 I915_WRITE_FW(CURPOS(PIPE_A), pos); 9890 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9903 } 9891 }
9904 9892
9905 POSTING_READ_FW(CURCNTR(PIPE_A));
9906
9907 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 9893 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9908} 9894}
9909 9895
@@ -10132,8 +10118,6 @@ static void i9xx_update_cursor(struct intel_plane *plane,
10132 I915_WRITE_FW(CURBASE(pipe), base); 10118 I915_WRITE_FW(CURBASE(pipe), base);
10133 } 10119 }
10134 10120
10135 POSTING_READ_FW(CURBASE(pipe));
10136
10137 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 10121 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
10138} 10122}
10139 10123
@@ -10738,14 +10722,40 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
10738 pipe_config->fb_bits |= plane->frontbuffer_bit; 10722 pipe_config->fb_bits |= plane->frontbuffer_bit;
10739 10723
10740 /* 10724 /*
10725 * ILK/SNB DVSACNTR/Sprite Enable
10726 * IVB SPR_CTL/Sprite Enable
10727 * "When in Self Refresh Big FIFO mode, a write to enable the
10728 * plane will be internally buffered and delayed while Big FIFO
10729 * mode is exiting."
10730 *
10731 * Which means that enabling the sprite can take an extra frame
10732 * when we start in big FIFO mode (LP1+). Thus we need to drop
10733 * down to LP0 and wait for vblank in order to make sure the
10734 * sprite gets enabled on the next vblank after the register write.
10735 * Doing otherwise would risk enabling the sprite one frame after
10736 * we've already signalled flip completion. We can resume LP1+
10737 * once the sprite has been enabled.
10738 *
10739 *
10741 * WaCxSRDisabledForSpriteScaling:ivb 10740 * WaCxSRDisabledForSpriteScaling:ivb
10741 * IVB SPR_SCALE/Scaling Enable
10742 * "Low Power watermarks must be disabled for at least one
10743 * frame before enabling sprite scaling, and kept disabled
10744 * until sprite scaling is disabled."
10742 * 10745 *
10743 * cstate->update_wm was already set above, so this flag will 10746 * ILK/SNB DVSASCALE/Scaling Enable
10744 * take effect when we commit and program watermarks. 10747 * "When in Self Refresh Big FIFO mode, scaling enable will be
10748 * masked off while Big FIFO mode is exiting."
10749 *
10750 * Despite the w/a only being listed for IVB we assume that
10751 * the ILK/SNB note has similar ramifications, hence we apply
10752 * the w/a on all three platforms.
10745 */ 10753 */
10746 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) && 10754 if (plane->id == PLANE_SPRITE0 &&
10747 needs_scaling(to_intel_plane_state(plane_state)) && 10755 (IS_GEN5(dev_priv) || IS_GEN6(dev_priv) ||
10748 !needs_scaling(old_plane_state)) 10756 IS_IVYBRIDGE(dev_priv)) &&
10757 (turn_on || (!needs_scaling(old_plane_state) &&
10758 needs_scaling(to_intel_plane_state(plane_state)))))
10749 pipe_config->disable_lp_wm = true; 10759 pipe_config->disable_lp_wm = true;
10750 10760
10751 return 0; 10761 return 0;
@@ -10781,6 +10791,98 @@ static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10781 return true; 10791 return true;
10782} 10792}
10783 10793
10794static int icl_add_linked_planes(struct intel_atomic_state *state)
10795{
10796 struct intel_plane *plane, *linked;
10797 struct intel_plane_state *plane_state, *linked_plane_state;
10798 int i;
10799
10800 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
10801 linked = plane_state->linked_plane;
10802
10803 if (!linked)
10804 continue;
10805
10806 linked_plane_state = intel_atomic_get_plane_state(state, linked);
10807 if (IS_ERR(linked_plane_state))
10808 return PTR_ERR(linked_plane_state);
10809
10810 WARN_ON(linked_plane_state->linked_plane != plane);
10811 WARN_ON(linked_plane_state->slave == plane_state->slave);
10812 }
10813
10814 return 0;
10815}
10816
10817static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
10818{
10819 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
10820 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10821 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state);
10822 struct intel_plane *plane, *linked;
10823 struct intel_plane_state *plane_state;
10824 int i;
10825
10826 if (INTEL_GEN(dev_priv) < 11)
10827 return 0;
10828
10829 /*
10830 * Destroy all old plane links and make the slave plane invisible
10831 * in the crtc_state->active_planes mask.
10832 */
10833 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
10834 if (plane->pipe != crtc->pipe || !plane_state->linked_plane)
10835 continue;
10836
10837 plane_state->linked_plane = NULL;
10838 if (plane_state->slave && !plane_state->base.visible)
10839 crtc_state->active_planes &= ~BIT(plane->id);
10840
10841 plane_state->slave = false;
10842 }
10843
10844 if (!crtc_state->nv12_planes)
10845 return 0;
10846
10847 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
10848 struct intel_plane_state *linked_state = NULL;
10849
10850 if (plane->pipe != crtc->pipe ||
10851 !(crtc_state->nv12_planes & BIT(plane->id)))
10852 continue;
10853
10854 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
10855 if (!icl_is_nv12_y_plane(linked->id))
10856 continue;
10857
10858 if (crtc_state->active_planes & BIT(linked->id))
10859 continue;
10860
10861 linked_state = intel_atomic_get_plane_state(state, linked);
10862 if (IS_ERR(linked_state))
10863 return PTR_ERR(linked_state);
10864
10865 break;
10866 }
10867
10868 if (!linked_state) {
10869 DRM_DEBUG_KMS("Need %d free Y planes for NV12\n",
10870 hweight8(crtc_state->nv12_planes));
10871
10872 return -EINVAL;
10873 }
10874
10875 plane_state->linked_plane = linked;
10876
10877 linked_state->slave = true;
10878 linked_state->linked_plane = plane;
10879 crtc_state->active_planes |= BIT(linked->id);
10880 DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
10881 }
10882
10883 return 0;
10884}
10885
10784static int intel_crtc_atomic_check(struct drm_crtc *crtc, 10886static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10785 struct drm_crtc_state *crtc_state) 10887 struct drm_crtc_state *crtc_state)
10786{ 10888{
@@ -10789,7 +10891,6 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 10891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10790 struct intel_crtc_state *pipe_config = 10892 struct intel_crtc_state *pipe_config =
10791 to_intel_crtc_state(crtc_state); 10893 to_intel_crtc_state(crtc_state);
10792 struct drm_atomic_state *state = crtc_state->state;
10793 int ret; 10894 int ret;
10794 bool mode_changed = needs_modeset(crtc_state); 10895 bool mode_changed = needs_modeset(crtc_state);
10795 10896
@@ -10826,8 +10927,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10826 } 10927 }
10827 } 10928 }
10828 10929
10829 if (dev_priv->display.compute_intermediate_wm && 10930 if (dev_priv->display.compute_intermediate_wm) {
10830 !to_intel_atomic_state(state)->skip_intermediate_wm) {
10831 if (WARN_ON(!dev_priv->display.compute_pipe_wm)) 10931 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10832 return 0; 10932 return 0;
10833 10933
@@ -10843,9 +10943,6 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10843 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); 10943 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10844 return ret; 10944 return ret;
10845 } 10945 }
10846 } else if (dev_priv->display.compute_intermediate_wm) {
10847 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10848 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10849 } 10946 }
10850 10947
10851 if (INTEL_GEN(dev_priv) >= 9) { 10948 if (INTEL_GEN(dev_priv) >= 9) {
@@ -10853,6 +10950,8 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10853 ret = skl_update_scaler_crtc(pipe_config); 10950 ret = skl_update_scaler_crtc(pipe_config);
10854 10951
10855 if (!ret) 10952 if (!ret)
10953 ret = icl_check_nv12_planes(pipe_config);
10954 if (!ret)
10856 ret = skl_check_pipe_max_pixel_rate(intel_crtc, 10955 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10857 pipe_config); 10956 pipe_config);
10858 if (!ret) 10957 if (!ret)
@@ -10867,8 +10966,6 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10867} 10966}
10868 10967
10869static const struct drm_crtc_helper_funcs intel_helper_funcs = { 10968static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10870 .atomic_begin = intel_begin_crtc_commit,
10871 .atomic_flush = intel_finish_crtc_commit,
10872 .atomic_check = intel_crtc_atomic_check, 10969 .atomic_check = intel_crtc_atomic_check,
10873}; 10970};
10874 10971
@@ -10897,30 +10994,42 @@ static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10897 drm_connector_list_iter_end(&conn_iter); 10994 drm_connector_list_iter_end(&conn_iter);
10898} 10995}
10899 10996
10900static void 10997static int
10901connected_sink_compute_bpp(struct intel_connector *connector, 10998compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
10902 struct intel_crtc_state *pipe_config) 10999 struct intel_crtc_state *pipe_config)
10903{ 11000{
10904 const struct drm_display_info *info = &connector->base.display_info; 11001 struct drm_connector *connector = conn_state->connector;
10905 int bpp = pipe_config->pipe_bpp; 11002 const struct drm_display_info *info = &connector->display_info;
11003 int bpp;
10906 11004
10907 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", 11005 switch (conn_state->max_bpc) {
10908 connector->base.base.id, 11006 case 6 ... 7:
10909 connector->base.name); 11007 bpp = 6 * 3;
10910 11008 break;
10911 /* Don't use an invalid EDID bpc value */ 11009 case 8 ... 9:
10912 if (info->bpc != 0 && info->bpc * 3 < bpp) { 11010 bpp = 8 * 3;
10913 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", 11011 break;
10914 bpp, info->bpc * 3); 11012 case 10 ... 11:
10915 pipe_config->pipe_bpp = info->bpc * 3; 11013 bpp = 10 * 3;
11014 break;
11015 case 12:
11016 bpp = 12 * 3;
11017 break;
11018 default:
11019 return -EINVAL;
10916 } 11020 }
10917 11021
10918 /* Clamp bpp to 8 on screens without EDID 1.4 */ 11022 if (bpp < pipe_config->pipe_bpp) {
10919 if (info->bpc == 0 && bpp > 24) { 11023 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
10920 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", 11024 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
10921 bpp); 11025 connector->base.id, connector->name,
10922 pipe_config->pipe_bpp = 24; 11026 bpp, 3 * info->bpc, 3 * conn_state->max_requested_bpc,
11027 pipe_config->pipe_bpp);
11028
11029 pipe_config->pipe_bpp = bpp;
10923 } 11030 }
11031
11032 return 0;
10924} 11033}
10925 11034
10926static int 11035static int
@@ -10928,7 +11037,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10928 struct intel_crtc_state *pipe_config) 11037 struct intel_crtc_state *pipe_config)
10929{ 11038{
10930 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 11039 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10931 struct drm_atomic_state *state; 11040 struct drm_atomic_state *state = pipe_config->base.state;
10932 struct drm_connector *connector; 11041 struct drm_connector *connector;
10933 struct drm_connector_state *connector_state; 11042 struct drm_connector_state *connector_state;
10934 int bpp, i; 11043 int bpp, i;
@@ -10941,21 +11050,21 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10941 else 11050 else
10942 bpp = 8*3; 11051 bpp = 8*3;
10943 11052
10944
10945 pipe_config->pipe_bpp = bpp; 11053 pipe_config->pipe_bpp = bpp;
10946 11054
10947 state = pipe_config->base.state; 11055 /* Clamp display bpp to connector max bpp */
10948
10949 /* Clamp display bpp to EDID value */
10950 for_each_new_connector_in_state(state, connector, connector_state, i) { 11056 for_each_new_connector_in_state(state, connector, connector_state, i) {
11057 int ret;
11058
10951 if (connector_state->crtc != &crtc->base) 11059 if (connector_state->crtc != &crtc->base)
10952 continue; 11060 continue;
10953 11061
10954 connected_sink_compute_bpp(to_intel_connector(connector), 11062 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
10955 pipe_config); 11063 if (ret)
11064 return ret;
10956 } 11065 }
10957 11066
10958 return bpp; 11067 return 0;
10959} 11068}
10960 11069
10961static void intel_dump_crtc_timings(const struct drm_display_mode *mode) 11070static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
@@ -11025,6 +11134,20 @@ static void snprintf_output_types(char *buf, size_t len,
11025 WARN_ON_ONCE(output_types != 0); 11134 WARN_ON_ONCE(output_types != 0);
11026} 11135}
11027 11136
11137static const char * const output_format_str[] = {
11138 [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
11139 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
11140 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
11141 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
11142};
11143
11144static const char *output_formats(enum intel_output_format format)
11145{
11146 if (format >= ARRAY_SIZE(output_format_str))
11147 format = INTEL_OUTPUT_FORMAT_INVALID;
11148 return output_format_str[format];
11149}
11150
11028static void intel_dump_pipe_config(struct intel_crtc *crtc, 11151static void intel_dump_pipe_config(struct intel_crtc *crtc,
11029 struct intel_crtc_state *pipe_config, 11152 struct intel_crtc_state *pipe_config,
11030 const char *context) 11153 const char *context)
@@ -11044,6 +11167,9 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
11044 DRM_DEBUG_KMS("output_types: %s (0x%x)\n", 11167 DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
11045 buf, pipe_config->output_types); 11168 buf, pipe_config->output_types);
11046 11169
11170 DRM_DEBUG_KMS("output format: %s\n",
11171 output_formats(pipe_config->output_format));
11172
11047 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", 11173 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11048 transcoder_name(pipe_config->cpu_transcoder), 11174 transcoder_name(pipe_config->cpu_transcoder),
11049 pipe_config->pipe_bpp, pipe_config->dither); 11175 pipe_config->pipe_bpp, pipe_config->dither);
@@ -11053,9 +11179,6 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
11053 pipe_config->fdi_lanes, 11179 pipe_config->fdi_lanes,
11054 &pipe_config->fdi_m_n); 11180 &pipe_config->fdi_m_n);
11055 11181
11056 if (pipe_config->ycbcr420)
11057 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
11058
11059 if (intel_crtc_has_dp_encoder(pipe_config)) { 11182 if (intel_crtc_has_dp_encoder(pipe_config)) {
11060 intel_dump_m_n_config(pipe_config, "dp m_n", 11183 intel_dump_m_n_config(pipe_config, "dp m_n",
11061 pipe_config->lane_count, &pipe_config->dp_m_n); 11184 pipe_config->lane_count, &pipe_config->dp_m_n);
@@ -11244,7 +11367,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
11244 struct intel_encoder *encoder; 11367 struct intel_encoder *encoder;
11245 struct drm_connector *connector; 11368 struct drm_connector *connector;
11246 struct drm_connector_state *connector_state; 11369 struct drm_connector_state *connector_state;
11247 int base_bpp, ret = -EINVAL; 11370 int base_bpp, ret;
11248 int i; 11371 int i;
11249 bool retry = true; 11372 bool retry = true;
11250 11373
@@ -11266,10 +11389,12 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
11266 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 11389 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11267 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 11390 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11268 11391
11269 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), 11392 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11270 pipe_config); 11393 pipe_config);
11271 if (base_bpp < 0) 11394 if (ret)
11272 goto fail; 11395 return ret;
11396
11397 base_bpp = pipe_config->pipe_bpp;
11273 11398
11274 /* 11399 /*
11275 * Determine the real pipe dimensions. Note that stereo modes can 11400 * Determine the real pipe dimensions. Note that stereo modes can
@@ -11291,7 +11416,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
11291 11416
11292 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { 11417 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11293 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); 11418 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11294 goto fail; 11419 return -EINVAL;
11295 } 11420 }
11296 11421
11297 /* 11422 /*
@@ -11327,7 +11452,7 @@ encoder_retry:
11327 11452
11328 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { 11453 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11329 DRM_DEBUG_KMS("Encoder config failure\n"); 11454 DRM_DEBUG_KMS("Encoder config failure\n");
11330 goto fail; 11455 return -EINVAL;
11331 } 11456 }
11332 } 11457 }
11333 11458
@@ -11338,16 +11463,16 @@ encoder_retry:
11338 * pipe_config->pixel_multiplier; 11463 * pipe_config->pixel_multiplier;
11339 11464
11340 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); 11465 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11466 if (ret == -EDEADLK)
11467 return ret;
11341 if (ret < 0) { 11468 if (ret < 0) {
11342 DRM_DEBUG_KMS("CRTC fixup failed\n"); 11469 DRM_DEBUG_KMS("CRTC fixup failed\n");
11343 goto fail; 11470 return ret;
11344 } 11471 }
11345 11472
11346 if (ret == RETRY) { 11473 if (ret == RETRY) {
11347 if (WARN(!retry, "loop in pipe configuration computation\n")) { 11474 if (WARN(!retry, "loop in pipe configuration computation\n"))
11348 ret = -EINVAL; 11475 return -EINVAL;
11349 goto fail;
11350 }
11351 11476
11352 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); 11477 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11353 retry = false; 11478 retry = false;
@@ -11363,8 +11488,7 @@ encoder_retry:
11363 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 11488 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11364 base_bpp, pipe_config->pipe_bpp, pipe_config->dither); 11489 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11365 11490
11366fail: 11491 return 0;
11367 return ret;
11368} 11492}
11369 11493
11370static bool intel_fuzzy_clock_check(int clock1, int clock2) 11494static bool intel_fuzzy_clock_check(int clock1, int clock2)
@@ -11633,6 +11757,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11633 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); 11757 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11634 11758
11635 PIPE_CONF_CHECK_I(pixel_multiplier); 11759 PIPE_CONF_CHECK_I(pixel_multiplier);
11760 PIPE_CONF_CHECK_I(output_format);
11636 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 11761 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
11637 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 11762 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11638 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 11763 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
@@ -11641,7 +11766,6 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11641 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 11766 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
11642 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 11767 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
11643 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe); 11768 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe);
11644 PIPE_CONF_CHECK_BOOL(ycbcr420);
11645 11769
11646 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 11770 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
11647 11771
@@ -12150,8 +12274,9 @@ intel_modeset_verify_disabled(struct drm_device *dev,
12150 verify_disabled_dpll_state(dev); 12274 verify_disabled_dpll_state(dev);
12151} 12275}
12152 12276
12153static void update_scanline_offset(struct intel_crtc *crtc) 12277static void update_scanline_offset(const struct intel_crtc_state *crtc_state)
12154{ 12278{
12279 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
12155 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 12280 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12156 12281
12157 /* 12282 /*
@@ -12182,7 +12307,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
12182 * answer that's slightly in the future. 12307 * answer that's slightly in the future.
12183 */ 12308 */
12184 if (IS_GEN2(dev_priv)) { 12309 if (IS_GEN2(dev_priv)) {
12185 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 12310 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
12186 int vtotal; 12311 int vtotal;
12187 12312
12188 vtotal = adjusted_mode->crtc_vtotal; 12313 vtotal = adjusted_mode->crtc_vtotal;
@@ -12191,7 +12316,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
12191 12316
12192 crtc->scanline_offset = vtotal - 1; 12317 crtc->scanline_offset = vtotal - 1;
12193 } else if (HAS_DDI(dev_priv) && 12318 } else if (HAS_DDI(dev_priv) &&
12194 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { 12319 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
12195 crtc->scanline_offset = 2; 12320 crtc->scanline_offset = 2;
12196 } else 12321 } else
12197 crtc->scanline_offset = 1; 12322 crtc->scanline_offset = 1;
@@ -12474,6 +12599,8 @@ static int intel_atomic_check(struct drm_device *dev,
12474 } 12599 }
12475 12600
12476 ret = intel_modeset_pipe_config(crtc, pipe_config); 12601 ret = intel_modeset_pipe_config(crtc, pipe_config);
12602 if (ret == -EDEADLK)
12603 return ret;
12477 if (ret) { 12604 if (ret) {
12478 intel_dump_pipe_config(to_intel_crtc(crtc), 12605 intel_dump_pipe_config(to_intel_crtc(crtc),
12479 pipe_config, "[failed]"); 12606 pipe_config, "[failed]");
@@ -12505,6 +12632,10 @@ static int intel_atomic_check(struct drm_device *dev,
12505 intel_state->cdclk.logical = dev_priv->cdclk.logical; 12632 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12506 } 12633 }
12507 12634
12635 ret = icl_add_linked_planes(intel_state);
12636 if (ret)
12637 return ret;
12638
12508 ret = drm_atomic_helper_check_planes(dev, state); 12639 ret = drm_atomic_helper_check_planes(dev, state);
12509 if (ret) 12640 if (ret)
12510 return ret; 12641 return ret;
@@ -12537,6 +12668,7 @@ static void intel_update_crtc(struct drm_crtc *crtc,
12537 struct drm_device *dev = crtc->dev; 12668 struct drm_device *dev = crtc->dev;
12538 struct drm_i915_private *dev_priv = to_i915(dev); 12669 struct drm_i915_private *dev_priv = to_i915(dev);
12539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 12670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12671 struct intel_crtc_state *old_intel_cstate = to_intel_crtc_state(old_crtc_state);
12540 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state); 12672 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12541 bool modeset = needs_modeset(new_crtc_state); 12673 bool modeset = needs_modeset(new_crtc_state);
12542 struct intel_plane_state *new_plane_state = 12674 struct intel_plane_state *new_plane_state =
@@ -12544,7 +12676,7 @@ static void intel_update_crtc(struct drm_crtc *crtc,
12544 to_intel_plane(crtc->primary)); 12676 to_intel_plane(crtc->primary));
12545 12677
12546 if (modeset) { 12678 if (modeset) {
12547 update_scanline_offset(intel_crtc); 12679 update_scanline_offset(pipe_config);
12548 dev_priv->display.crtc_enable(pipe_config, state); 12680 dev_priv->display.crtc_enable(pipe_config, state);
12549 12681
12550 /* vblanks work again, re-enable pipe CRC. */ 12682 /* vblanks work again, re-enable pipe CRC. */
@@ -12557,7 +12689,12 @@ static void intel_update_crtc(struct drm_crtc *crtc,
12557 if (new_plane_state) 12689 if (new_plane_state)
12558 intel_fbc_enable(intel_crtc, pipe_config, new_plane_state); 12690 intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
12559 12691
12560 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); 12692 intel_begin_crtc_commit(crtc, old_crtc_state);
12693
12694 intel_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc,
12695 old_intel_cstate, pipe_config);
12696
12697 intel_finish_crtc_commit(crtc, old_crtc_state);
12561} 12698}
12562 12699
12563static void intel_update_crtcs(struct drm_atomic_state *state) 12700static void intel_update_crtcs(struct drm_atomic_state *state)
@@ -12589,13 +12726,12 @@ static void skl_update_crtcs(struct drm_atomic_state *state)
12589 int i; 12726 int i;
12590 u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices; 12727 u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
12591 u8 required_slices = intel_state->wm_results.ddb.enabled_slices; 12728 u8 required_slices = intel_state->wm_results.ddb.enabled_slices;
12592 12729 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
12593 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12594 12730
12595 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) 12731 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12596 /* ignore allocations for crtc's that have been turned off. */ 12732 /* ignore allocations for crtc's that have been turned off. */
12597 if (new_crtc_state->active) 12733 if (new_crtc_state->active)
12598 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; 12734 entries[i] = to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12599 12735
12600 /* If 2nd DBuf slice required, enable it here */ 12736 /* If 2nd DBuf slice required, enable it here */
12601 if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices) 12737 if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
@@ -12621,14 +12757,13 @@ static void skl_update_crtcs(struct drm_atomic_state *state)
12621 if (updated & cmask || !cstate->base.active) 12757 if (updated & cmask || !cstate->base.active)
12622 continue; 12758 continue;
12623 12759
12624 if (skl_ddb_allocation_overlaps(dev_priv, 12760 if (skl_ddb_allocation_overlaps(&cstate->wm.skl.ddb,
12625 entries, 12761 entries,
12626 &cstate->wm.skl.ddb, 12762 INTEL_INFO(dev_priv)->num_pipes, i))
12627 i))
12628 continue; 12763 continue;
12629 12764
12630 updated |= cmask; 12765 updated |= cmask;
12631 entries[i] = &cstate->wm.skl.ddb; 12766 entries[i] = cstate->wm.skl.ddb;
12632 12767
12633 /* 12768 /*
12634 * If this is an already active pipe, it's DDB changed, 12769 * If this is an already active pipe, it's DDB changed,
@@ -12718,8 +12853,9 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12718 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 12853 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12719 struct drm_i915_private *dev_priv = to_i915(dev); 12854 struct drm_i915_private *dev_priv = to_i915(dev);
12720 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 12855 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12856 struct intel_crtc_state *new_intel_crtc_state, *old_intel_crtc_state;
12721 struct drm_crtc *crtc; 12857 struct drm_crtc *crtc;
12722 struct intel_crtc_state *intel_cstate; 12858 struct intel_crtc *intel_crtc;
12723 u64 put_domains[I915_MAX_PIPES] = {}; 12859 u64 put_domains[I915_MAX_PIPES] = {};
12724 int i; 12860 int i;
12725 12861
@@ -12731,24 +12867,25 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12731 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); 12867 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12732 12868
12733 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 12869 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 12870 old_intel_crtc_state = to_intel_crtc_state(old_crtc_state);
12871 new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
12872 intel_crtc = to_intel_crtc(crtc);
12735 12873
12736 if (needs_modeset(new_crtc_state) || 12874 if (needs_modeset(new_crtc_state) ||
12737 to_intel_crtc_state(new_crtc_state)->update_pipe) { 12875 to_intel_crtc_state(new_crtc_state)->update_pipe) {
12738 12876
12739 put_domains[to_intel_crtc(crtc)->pipe] = 12877 put_domains[intel_crtc->pipe] =
12740 modeset_get_crtc_power_domains(crtc, 12878 modeset_get_crtc_power_domains(crtc,
12741 to_intel_crtc_state(new_crtc_state)); 12879 new_intel_crtc_state);
12742 } 12880 }
12743 12881
12744 if (!needs_modeset(new_crtc_state)) 12882 if (!needs_modeset(new_crtc_state))
12745 continue; 12883 continue;
12746 12884
12747 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state), 12885 intel_pre_plane_update(old_intel_crtc_state, new_intel_crtc_state);
12748 to_intel_crtc_state(new_crtc_state));
12749 12886
12750 if (old_crtc_state->active) { 12887 if (old_crtc_state->active) {
12751 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); 12888 intel_crtc_disable_planes(intel_crtc, old_intel_crtc_state->active_planes);
12752 12889
12753 /* 12890 /*
12754 * We need to disable pipe CRC before disabling the pipe, 12891 * We need to disable pipe CRC before disabling the pipe,
@@ -12756,10 +12893,10 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12756 */ 12893 */
12757 intel_crtc_disable_pipe_crc(intel_crtc); 12894 intel_crtc_disable_pipe_crc(intel_crtc);
12758 12895
12759 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); 12896 dev_priv->display.crtc_disable(old_intel_crtc_state, state);
12760 intel_crtc->active = false; 12897 intel_crtc->active = false;
12761 intel_fbc_disable(intel_crtc); 12898 intel_fbc_disable(intel_crtc);
12762 intel_disable_shared_dpll(intel_crtc); 12899 intel_disable_shared_dpll(old_intel_crtc_state);
12763 12900
12764 /* 12901 /*
12765 * Underruns don't always raise 12902 * Underruns don't always raise
@@ -12768,17 +12905,12 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12768 intel_check_cpu_fifo_underruns(dev_priv); 12905 intel_check_cpu_fifo_underruns(dev_priv);
12769 intel_check_pch_fifo_underruns(dev_priv); 12906 intel_check_pch_fifo_underruns(dev_priv);
12770 12907
12771 if (!new_crtc_state->active) { 12908 /* FIXME unify this for all platforms */
12772 /* 12909 if (!new_crtc_state->active &&
12773 * Make sure we don't call initial_watermarks 12910 !HAS_GMCH_DISPLAY(dev_priv) &&
12774 * for ILK-style watermark updates. 12911 dev_priv->display.initial_watermarks)
12775 * 12912 dev_priv->display.initial_watermarks(intel_state,
12776 * No clue what this is supposed to achieve. 12913 new_intel_crtc_state);
12777 */
12778 if (INTEL_GEN(dev_priv) >= 9)
12779 dev_priv->display.initial_watermarks(intel_state,
12780 to_intel_crtc_state(new_crtc_state));
12781 }
12782 } 12914 }
12783 } 12915 }
12784 12916
@@ -12837,11 +12969,11 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12837 * TODO: Move this (and other cleanup) to an async worker eventually. 12969 * TODO: Move this (and other cleanup) to an async worker eventually.
12838 */ 12970 */
12839 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 12971 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12840 intel_cstate = to_intel_crtc_state(new_crtc_state); 12972 new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
12841 12973
12842 if (dev_priv->display.optimize_watermarks) 12974 if (dev_priv->display.optimize_watermarks)
12843 dev_priv->display.optimize_watermarks(intel_state, 12975 dev_priv->display.optimize_watermarks(intel_state,
12844 intel_cstate); 12976 new_intel_crtc_state);
12845 } 12977 }
12846 12978
12847 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 12979 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
@@ -13224,13 +13356,12 @@ intel_prepare_plane_fb(struct drm_plane *plane,
13224 13356
13225 ret = intel_plane_pin_fb(to_intel_plane_state(new_state)); 13357 ret = intel_plane_pin_fb(to_intel_plane_state(new_state));
13226 13358
13227 fb_obj_bump_render_priority(obj);
13228
13229 mutex_unlock(&dev_priv->drm.struct_mutex); 13359 mutex_unlock(&dev_priv->drm.struct_mutex);
13230 i915_gem_object_unpin_pages(obj); 13360 i915_gem_object_unpin_pages(obj);
13231 if (ret) 13361 if (ret)
13232 return ret; 13362 return ret;
13233 13363
13364 fb_obj_bump_render_priority(obj);
13234 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); 13365 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13235 13366
13236 if (!new_state->fence) { /* implicit fencing */ 13367 if (!new_state->fence) { /* implicit fencing */
@@ -13361,7 +13492,7 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13361 if (intel_cstate->update_pipe) 13492 if (intel_cstate->update_pipe)
13362 intel_update_pipe_config(old_intel_cstate, intel_cstate); 13493 intel_update_pipe_config(old_intel_cstate, intel_cstate);
13363 else if (INTEL_GEN(dev_priv) >= 9) 13494 else if (INTEL_GEN(dev_priv) >= 9)
13364 skl_detach_scalers(intel_crtc); 13495 skl_detach_scalers(intel_cstate);
13365 13496
13366out: 13497out:
13367 if (dev_priv->display.atomic_update_watermarks) 13498 if (dev_priv->display.atomic_update_watermarks)
@@ -13463,56 +13594,6 @@ static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
13463 } 13594 }
13464} 13595}
13465 13596
13466static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
13467 u32 format, u64 modifier)
13468{
13469 struct intel_plane *plane = to_intel_plane(_plane);
13470
13471 switch (modifier) {
13472 case DRM_FORMAT_MOD_LINEAR:
13473 case I915_FORMAT_MOD_X_TILED:
13474 case I915_FORMAT_MOD_Y_TILED:
13475 case I915_FORMAT_MOD_Yf_TILED:
13476 break;
13477 case I915_FORMAT_MOD_Y_TILED_CCS:
13478 case I915_FORMAT_MOD_Yf_TILED_CCS:
13479 if (!plane->has_ccs)
13480 return false;
13481 break;
13482 default:
13483 return false;
13484 }
13485
13486 switch (format) {
13487 case DRM_FORMAT_XRGB8888:
13488 case DRM_FORMAT_XBGR8888:
13489 case DRM_FORMAT_ARGB8888:
13490 case DRM_FORMAT_ABGR8888:
13491 if (is_ccs_modifier(modifier))
13492 return true;
13493 /* fall through */
13494 case DRM_FORMAT_RGB565:
13495 case DRM_FORMAT_XRGB2101010:
13496 case DRM_FORMAT_XBGR2101010:
13497 case DRM_FORMAT_YUYV:
13498 case DRM_FORMAT_YVYU:
13499 case DRM_FORMAT_UYVY:
13500 case DRM_FORMAT_VYUY:
13501 case DRM_FORMAT_NV12:
13502 if (modifier == I915_FORMAT_MOD_Yf_TILED)
13503 return true;
13504 /* fall through */
13505 case DRM_FORMAT_C8:
13506 if (modifier == DRM_FORMAT_MOD_LINEAR ||
13507 modifier == I915_FORMAT_MOD_X_TILED ||
13508 modifier == I915_FORMAT_MOD_Y_TILED)
13509 return true;
13510 /* fall through */
13511 default:
13512 return false;
13513 }
13514}
13515
13516static bool intel_cursor_format_mod_supported(struct drm_plane *_plane, 13597static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
13517 u32 format, u64 modifier) 13598 u32 format, u64 modifier)
13518{ 13599{
@@ -13520,18 +13601,7 @@ static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
13520 format == DRM_FORMAT_ARGB8888; 13601 format == DRM_FORMAT_ARGB8888;
13521} 13602}
13522 13603
13523static struct drm_plane_funcs skl_plane_funcs = { 13604static const struct drm_plane_funcs i965_plane_funcs = {
13524 .update_plane = drm_atomic_helper_update_plane,
13525 .disable_plane = drm_atomic_helper_disable_plane,
13526 .destroy = intel_plane_destroy,
13527 .atomic_get_property = intel_plane_atomic_get_property,
13528 .atomic_set_property = intel_plane_atomic_set_property,
13529 .atomic_duplicate_state = intel_plane_duplicate_state,
13530 .atomic_destroy_state = intel_plane_destroy_state,
13531 .format_mod_supported = skl_plane_format_mod_supported,
13532};
13533
13534static struct drm_plane_funcs i965_plane_funcs = {
13535 .update_plane = drm_atomic_helper_update_plane, 13605 .update_plane = drm_atomic_helper_update_plane,
13536 .disable_plane = drm_atomic_helper_disable_plane, 13606 .disable_plane = drm_atomic_helper_disable_plane,
13537 .destroy = intel_plane_destroy, 13607 .destroy = intel_plane_destroy,
@@ -13542,7 +13612,7 @@ static struct drm_plane_funcs i965_plane_funcs = {
13542 .format_mod_supported = i965_plane_format_mod_supported, 13612 .format_mod_supported = i965_plane_format_mod_supported,
13543}; 13613};
13544 13614
13545static struct drm_plane_funcs i8xx_plane_funcs = { 13615static const struct drm_plane_funcs i8xx_plane_funcs = {
13546 .update_plane = drm_atomic_helper_update_plane, 13616 .update_plane = drm_atomic_helper_update_plane,
13547 .disable_plane = drm_atomic_helper_disable_plane, 13617 .disable_plane = drm_atomic_helper_disable_plane,
13548 .destroy = intel_plane_destroy, 13618 .destroy = intel_plane_destroy,
@@ -13568,14 +13638,16 @@ intel_legacy_cursor_update(struct drm_plane *plane,
13568 struct drm_plane_state *old_plane_state, *new_plane_state; 13638 struct drm_plane_state *old_plane_state, *new_plane_state;
13569 struct intel_plane *intel_plane = to_intel_plane(plane); 13639 struct intel_plane *intel_plane = to_intel_plane(plane);
13570 struct drm_framebuffer *old_fb; 13640 struct drm_framebuffer *old_fb;
13571 struct drm_crtc_state *crtc_state = crtc->state; 13641 struct intel_crtc_state *crtc_state =
13642 to_intel_crtc_state(crtc->state);
13643 struct intel_crtc_state *new_crtc_state;
13572 13644
13573 /* 13645 /*
13574 * When crtc is inactive or there is a modeset pending, 13646 * When crtc is inactive or there is a modeset pending,
13575 * wait for it to complete in the slowpath 13647 * wait for it to complete in the slowpath
13576 */ 13648 */
13577 if (!crtc_state->active || needs_modeset(crtc_state) || 13649 if (!crtc_state->base.active || needs_modeset(&crtc_state->base) ||
13578 to_intel_crtc_state(crtc_state)->update_pipe) 13650 crtc_state->update_pipe)
13579 goto slow; 13651 goto slow;
13580 13652
13581 old_plane_state = plane->state; 13653 old_plane_state = plane->state;
@@ -13605,6 +13677,12 @@ intel_legacy_cursor_update(struct drm_plane *plane,
13605 if (!new_plane_state) 13677 if (!new_plane_state)
13606 return -ENOMEM; 13678 return -ENOMEM;
13607 13679
13680 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(crtc));
13681 if (!new_crtc_state) {
13682 ret = -ENOMEM;
13683 goto out_free;
13684 }
13685
13608 drm_atomic_set_fb_for_plane(new_plane_state, fb); 13686 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13609 13687
13610 new_plane_state->src_x = src_x; 13688 new_plane_state->src_x = src_x;
@@ -13616,9 +13694,8 @@ intel_legacy_cursor_update(struct drm_plane *plane,
13616 new_plane_state->crtc_w = crtc_w; 13694 new_plane_state->crtc_w = crtc_w;
13617 new_plane_state->crtc_h = crtc_h; 13695 new_plane_state->crtc_h = crtc_h;
13618 13696
13619 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state), 13697 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
13620 to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */ 13698 to_intel_plane_state(old_plane_state),
13621 to_intel_plane_state(plane->state),
13622 to_intel_plane_state(new_plane_state)); 13699 to_intel_plane_state(new_plane_state));
13623 if (ret) 13700 if (ret)
13624 goto out_free; 13701 goto out_free;
@@ -13640,10 +13717,21 @@ intel_legacy_cursor_update(struct drm_plane *plane,
13640 /* Swap plane state */ 13717 /* Swap plane state */
13641 plane->state = new_plane_state; 13718 plane->state = new_plane_state;
13642 13719
13720 /*
13721 * We cannot swap crtc_state as it may be in use by an atomic commit or
13722 * page flip that's running simultaneously. If we swap crtc_state and
13723 * destroy the old state, we will cause a use-after-free there.
13724 *
13725 * Only update active_planes, which is needed for our internal
13726 * bookkeeping. Either value will do the right thing when updating
13727 * planes atomically. If the cursor was part of the atomic update then
13728 * we would have taken the slowpath.
13729 */
13730 crtc_state->active_planes = new_crtc_state->active_planes;
13731
13643 if (plane->state->visible) { 13732 if (plane->state->visible) {
13644 trace_intel_update_plane(plane, to_intel_crtc(crtc)); 13733 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13645 intel_plane->update_plane(intel_plane, 13734 intel_plane->update_plane(intel_plane, crtc_state,
13646 to_intel_crtc_state(crtc->state),
13647 to_intel_plane_state(plane->state)); 13735 to_intel_plane_state(plane->state));
13648 } else { 13736 } else {
13649 trace_intel_disable_plane(plane, to_intel_crtc(crtc)); 13737 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
@@ -13655,6 +13743,8 @@ intel_legacy_cursor_update(struct drm_plane *plane,
13655out_unlock: 13743out_unlock:
13656 mutex_unlock(&dev_priv->drm.struct_mutex); 13744 mutex_unlock(&dev_priv->drm.struct_mutex);
13657out_free: 13745out_free:
13746 if (new_crtc_state)
13747 intel_crtc_destroy_state(crtc, &new_crtc_state->base);
13658 if (ret) 13748 if (ret)
13659 intel_plane_destroy_state(plane, new_plane_state); 13749 intel_plane_destroy_state(plane, new_plane_state);
13660 else 13750 else
@@ -13695,176 +13785,90 @@ static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
13695 return i9xx_plane == PLANE_A; 13785 return i9xx_plane == PLANE_A;
13696} 13786}
13697 13787
13698static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
13699 enum pipe pipe, enum plane_id plane_id)
13700{
13701 if (!HAS_FBC(dev_priv))
13702 return false;
13703
13704 return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
13705}
13706
13707bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
13708 enum pipe pipe, enum plane_id plane_id)
13709{
13710 /*
13711 * FIXME: ICL requires two hardware planes for scanning out NV12
13712 * framebuffers. Do not advertize support until this is implemented.
13713 */
13714 if (INTEL_GEN(dev_priv) >= 11)
13715 return false;
13716
13717 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
13718 return false;
13719
13720 if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
13721 return false;
13722
13723 if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
13724 return false;
13725
13726 return true;
13727}
13728
13729static struct intel_plane * 13788static struct intel_plane *
13730intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 13789intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13731{ 13790{
13732 struct intel_plane *primary = NULL; 13791 struct intel_plane *plane;
13733 struct intel_plane_state *state = NULL;
13734 const struct drm_plane_funcs *plane_funcs; 13792 const struct drm_plane_funcs *plane_funcs;
13735 const uint32_t *intel_primary_formats;
13736 unsigned int supported_rotations; 13793 unsigned int supported_rotations;
13737 unsigned int num_formats; 13794 unsigned int possible_crtcs;
13738 const uint64_t *modifiers; 13795 const u64 *modifiers;
13796 const u32 *formats;
13797 int num_formats;
13739 int ret; 13798 int ret;
13740 13799
13741 primary = kzalloc(sizeof(*primary), GFP_KERNEL); 13800 if (INTEL_GEN(dev_priv) >= 9)
13742 if (!primary) { 13801 return skl_universal_plane_create(dev_priv, pipe,
13743 ret = -ENOMEM; 13802 PLANE_PRIMARY);
13744 goto fail;
13745 }
13746
13747 state = intel_create_plane_state(&primary->base);
13748 if (!state) {
13749 ret = -ENOMEM;
13750 goto fail;
13751 }
13752 13803
13753 primary->base.state = &state->base; 13804 plane = intel_plane_alloc();
13805 if (IS_ERR(plane))
13806 return plane;
13754 13807
13755 if (INTEL_GEN(dev_priv) >= 9) 13808 plane->pipe = pipe;
13756 state->scaler_id = -1;
13757 primary->pipe = pipe;
13758 /* 13809 /*
13759 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS 13810 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13760 * port is hooked to pipe B. Hence we want plane A feeding pipe B. 13811 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13761 */ 13812 */
13762 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) 13813 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13763 primary->i9xx_plane = (enum i9xx_plane_id) !pipe; 13814 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
13764 else 13815 else
13765 primary->i9xx_plane = (enum i9xx_plane_id) pipe; 13816 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
13766 primary->id = PLANE_PRIMARY; 13817 plane->id = PLANE_PRIMARY;
13767 primary->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, primary->id); 13818 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
13768 13819
13769 if (INTEL_GEN(dev_priv) >= 9) 13820 plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
13770 primary->has_fbc = skl_plane_has_fbc(dev_priv, 13821 if (plane->has_fbc) {
13771 primary->pipe,
13772 primary->id);
13773 else
13774 primary->has_fbc = i9xx_plane_has_fbc(dev_priv,
13775 primary->i9xx_plane);
13776
13777 if (primary->has_fbc) {
13778 struct intel_fbc *fbc = &dev_priv->fbc; 13822 struct intel_fbc *fbc = &dev_priv->fbc;
13779 13823
13780 fbc->possible_framebuffer_bits |= primary->frontbuffer_bit; 13824 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
13781 } 13825 }
13782 13826
13783 if (INTEL_GEN(dev_priv) >= 9) { 13827 if (INTEL_GEN(dev_priv) >= 4) {
13784 primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe, 13828 formats = i965_primary_formats;
13785 PLANE_PRIMARY);
13786
13787 if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
13788 intel_primary_formats = skl_pri_planar_formats;
13789 num_formats = ARRAY_SIZE(skl_pri_planar_formats);
13790 } else {
13791 intel_primary_formats = skl_primary_formats;
13792 num_formats = ARRAY_SIZE(skl_primary_formats);
13793 }
13794
13795 if (primary->has_ccs)
13796 modifiers = skl_format_modifiers_ccs;
13797 else
13798 modifiers = skl_format_modifiers_noccs;
13799
13800 primary->max_stride = skl_plane_max_stride;
13801 primary->update_plane = skl_update_plane;
13802 primary->disable_plane = skl_disable_plane;
13803 primary->get_hw_state = skl_plane_get_hw_state;
13804 primary->check_plane = skl_plane_check;
13805
13806 plane_funcs = &skl_plane_funcs;
13807 } else if (INTEL_GEN(dev_priv) >= 4) {
13808 intel_primary_formats = i965_primary_formats;
13809 num_formats = ARRAY_SIZE(i965_primary_formats); 13829 num_formats = ARRAY_SIZE(i965_primary_formats);
13810 modifiers = i9xx_format_modifiers; 13830 modifiers = i9xx_format_modifiers;
13811 13831
13812 primary->max_stride = i9xx_plane_max_stride; 13832 plane->max_stride = i9xx_plane_max_stride;
13813 primary->update_plane = i9xx_update_plane; 13833 plane->update_plane = i9xx_update_plane;
13814 primary->disable_plane = i9xx_disable_plane; 13834 plane->disable_plane = i9xx_disable_plane;
13815 primary->get_hw_state = i9xx_plane_get_hw_state; 13835 plane->get_hw_state = i9xx_plane_get_hw_state;
13816 primary->check_plane = i9xx_plane_check; 13836 plane->check_plane = i9xx_plane_check;
13817 13837
13818 plane_funcs = &i965_plane_funcs; 13838 plane_funcs = &i965_plane_funcs;
13819 } else { 13839 } else {
13820 intel_primary_formats = i8xx_primary_formats; 13840 formats = i8xx_primary_formats;
13821 num_formats = ARRAY_SIZE(i8xx_primary_formats); 13841 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13822 modifiers = i9xx_format_modifiers; 13842 modifiers = i9xx_format_modifiers;
13823 13843
13824 primary->max_stride = i9xx_plane_max_stride; 13844 plane->max_stride = i9xx_plane_max_stride;
13825 primary->update_plane = i9xx_update_plane; 13845 plane->update_plane = i9xx_update_plane;
13826 primary->disable_plane = i9xx_disable_plane; 13846 plane->disable_plane = i9xx_disable_plane;
13827 primary->get_hw_state = i9xx_plane_get_hw_state; 13847 plane->get_hw_state = i9xx_plane_get_hw_state;
13828 primary->check_plane = i9xx_plane_check; 13848 plane->check_plane = i9xx_plane_check;
13829 13849
13830 plane_funcs = &i8xx_plane_funcs; 13850 plane_funcs = &i8xx_plane_funcs;
13831 } 13851 }
13832 13852
13833 if (INTEL_GEN(dev_priv) >= 9) 13853 possible_crtcs = BIT(pipe);
13834 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, 13854
13835 0, plane_funcs, 13855 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13836 intel_primary_formats, num_formats, 13856 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
13837 modifiers, 13857 possible_crtcs, plane_funcs,
13838 DRM_PLANE_TYPE_PRIMARY, 13858 formats, num_formats, modifiers,
13839 "plane 1%c", pipe_name(pipe));
13840 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13841 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13842 0, plane_funcs,
13843 intel_primary_formats, num_formats,
13844 modifiers,
13845 DRM_PLANE_TYPE_PRIMARY, 13859 DRM_PLANE_TYPE_PRIMARY,
13846 "primary %c", pipe_name(pipe)); 13860 "primary %c", pipe_name(pipe));
13847 else 13861 else
13848 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, 13862 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
13849 0, plane_funcs, 13863 possible_crtcs, plane_funcs,
13850 intel_primary_formats, num_formats, 13864 formats, num_formats, modifiers,
13851 modifiers,
13852 DRM_PLANE_TYPE_PRIMARY, 13865 DRM_PLANE_TYPE_PRIMARY,
13853 "plane %c", 13866 "plane %c",
13854 plane_name(primary->i9xx_plane)); 13867 plane_name(plane->i9xx_plane));
13855 if (ret) 13868 if (ret)
13856 goto fail; 13869 goto fail;
13857 13870
13858 if (INTEL_GEN(dev_priv) >= 10) { 13871 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13859 supported_rotations =
13860 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13861 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270 |
13862 DRM_MODE_REFLECT_X;
13863 } else if (INTEL_GEN(dev_priv) >= 9) {
13864 supported_rotations =
13865 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13866 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13867 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13868 supported_rotations = 13872 supported_rotations =
13869 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | 13873 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13870 DRM_MODE_REFLECT_X; 13874 DRM_MODE_REFLECT_X;
@@ -13876,26 +13880,16 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13876 } 13880 }
13877 13881
13878 if (INTEL_GEN(dev_priv) >= 4) 13882 if (INTEL_GEN(dev_priv) >= 4)
13879 drm_plane_create_rotation_property(&primary->base, 13883 drm_plane_create_rotation_property(&plane->base,
13880 DRM_MODE_ROTATE_0, 13884 DRM_MODE_ROTATE_0,
13881 supported_rotations); 13885 supported_rotations);
13882 13886
13883 if (INTEL_GEN(dev_priv) >= 9) 13887 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
13884 drm_plane_create_color_properties(&primary->base,
13885 BIT(DRM_COLOR_YCBCR_BT601) |
13886 BIT(DRM_COLOR_YCBCR_BT709),
13887 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
13888 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
13889 DRM_COLOR_YCBCR_BT709,
13890 DRM_COLOR_YCBCR_LIMITED_RANGE);
13891
13892 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13893 13888
13894 return primary; 13889 return plane;
13895 13890
13896fail: 13891fail:
13897 kfree(state); 13892 intel_plane_free(plane);
13898 kfree(primary);
13899 13893
13900 return ERR_PTR(ret); 13894 return ERR_PTR(ret);
13901} 13895}
@@ -13904,23 +13898,13 @@ static struct intel_plane *
13904intel_cursor_plane_create(struct drm_i915_private *dev_priv, 13898intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13905 enum pipe pipe) 13899 enum pipe pipe)
13906{ 13900{
13907 struct intel_plane *cursor = NULL; 13901 unsigned int possible_crtcs;
13908 struct intel_plane_state *state = NULL; 13902 struct intel_plane *cursor;
13909 int ret; 13903 int ret;
13910 13904
13911 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); 13905 cursor = intel_plane_alloc();
13912 if (!cursor) { 13906 if (IS_ERR(cursor))
13913 ret = -ENOMEM; 13907 return cursor;
13914 goto fail;
13915 }
13916
13917 state = intel_create_plane_state(&cursor->base);
13918 if (!state) {
13919 ret = -ENOMEM;
13920 goto fail;
13921 }
13922
13923 cursor->base.state = &state->base;
13924 13908
13925 cursor->pipe = pipe; 13909 cursor->pipe = pipe;
13926 cursor->i9xx_plane = (enum i9xx_plane_id) pipe; 13910 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
@@ -13947,8 +13931,10 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13947 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) 13931 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13948 cursor->cursor.size = ~0; 13932 cursor->cursor.size = ~0;
13949 13933
13934 possible_crtcs = BIT(pipe);
13935
13950 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, 13936 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13951 0, &intel_cursor_plane_funcs, 13937 possible_crtcs, &intel_cursor_plane_funcs,
13952 intel_cursor_formats, 13938 intel_cursor_formats,
13953 ARRAY_SIZE(intel_cursor_formats), 13939 ARRAY_SIZE(intel_cursor_formats),
13954 cursor_format_modifiers, 13940 cursor_format_modifiers,
@@ -13963,16 +13949,12 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13963 DRM_MODE_ROTATE_0 | 13949 DRM_MODE_ROTATE_0 |
13964 DRM_MODE_ROTATE_180); 13950 DRM_MODE_ROTATE_180);
13965 13951
13966 if (INTEL_GEN(dev_priv) >= 9)
13967 state->scaler_id = -1;
13968
13969 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); 13952 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13970 13953
13971 return cursor; 13954 return cursor;
13972 13955
13973fail: 13956fail:
13974 kfree(state); 13957 intel_plane_free(cursor);
13975 kfree(cursor);
13976 13958
13977 return ERR_PTR(ret); 13959 return ERR_PTR(ret);
13978} 13960}
@@ -13993,7 +13975,7 @@ static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13993 struct intel_scaler *scaler = &scaler_state->scalers[i]; 13975 struct intel_scaler *scaler = &scaler_state->scalers[i];
13994 13976
13995 scaler->in_use = 0; 13977 scaler->in_use = 0;
13996 scaler->mode = PS_SCALER_MODE_DYN; 13978 scaler->mode = 0;
13997 } 13979 }
13998 13980
13999 scaler_state->scaler_id = -1; 13981 scaler_state->scaler_id = -1;
@@ -14088,18 +14070,6 @@ fail:
14088 return ret; 14070 return ret;
14089} 14071}
14090 14072
14091enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14092{
14093 struct drm_device *dev = connector->base.dev;
14094
14095 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14096
14097 if (!connector->base.state->crtc)
14098 return INVALID_PIPE;
14099
14100 return to_intel_crtc(connector->base.state->crtc)->pipe;
14101}
14102
14103int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 14073int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
14104 struct drm_file *file) 14074 struct drm_file *file)
14105{ 14075{
@@ -14236,6 +14206,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14236 intel_ddi_init(dev_priv, PORT_D); 14206 intel_ddi_init(dev_priv, PORT_D);
14237 intel_ddi_init(dev_priv, PORT_E); 14207 intel_ddi_init(dev_priv, PORT_E);
14238 intel_ddi_init(dev_priv, PORT_F); 14208 intel_ddi_init(dev_priv, PORT_F);
14209 icl_dsi_init(dev_priv);
14239 } else if (IS_GEN9_LP(dev_priv)) { 14210 } else if (IS_GEN9_LP(dev_priv)) {
14240 /* 14211 /*
14241 * FIXME: Broxton doesn't support port detection via the 14212 * FIXME: Broxton doesn't support port detection via the
@@ -14458,7 +14429,7 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
14458 14429
14459static 14430static
14460u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv, 14431u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14461 uint64_t fb_modifier, uint32_t pixel_format) 14432 u32 pixel_format, u64 fb_modifier)
14462{ 14433{
14463 struct intel_crtc *crtc; 14434 struct intel_crtc *crtc;
14464 struct intel_plane *plane; 14435 struct intel_plane *plane;
@@ -14526,13 +14497,19 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14526 goto err; 14497 goto err;
14527 } 14498 }
14528 /* fall through */ 14499 /* fall through */
14529 case I915_FORMAT_MOD_Y_TILED:
14530 case I915_FORMAT_MOD_Yf_TILED: 14500 case I915_FORMAT_MOD_Yf_TILED:
14501 if (mode_cmd->pixel_format == DRM_FORMAT_C8) {
14502 DRM_DEBUG_KMS("Indexed format does not support Yf tiling\n");
14503 goto err;
14504 }
14505 /* fall through */
14506 case I915_FORMAT_MOD_Y_TILED:
14531 if (INTEL_GEN(dev_priv) < 9) { 14507 if (INTEL_GEN(dev_priv) < 9) {
14532 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n", 14508 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14533 mode_cmd->modifier[0]); 14509 mode_cmd->modifier[0]);
14534 goto err; 14510 goto err;
14535 } 14511 }
14512 break;
14536 case DRM_FORMAT_MOD_LINEAR: 14513 case DRM_FORMAT_MOD_LINEAR:
14537 case I915_FORMAT_MOD_X_TILED: 14514 case I915_FORMAT_MOD_X_TILED:
14538 break; 14515 break;
@@ -14552,8 +14529,8 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14552 goto err; 14529 goto err;
14553 } 14530 }
14554 14531
14555 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0], 14532 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->pixel_format,
14556 mode_cmd->pixel_format); 14533 mode_cmd->modifier[0]);
14557 if (mode_cmd->pitches[0] > pitch_limit) { 14534 if (mode_cmd->pitches[0] > pitch_limit) {
14558 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n", 14535 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14559 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? 14536 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
@@ -14622,7 +14599,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14622 break; 14599 break;
14623 case DRM_FORMAT_NV12: 14600 case DRM_FORMAT_NV12:
14624 if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) || 14601 if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) ||
14625 IS_BROXTON(dev_priv) || INTEL_GEN(dev_priv) >= 11) { 14602 IS_BROXTON(dev_priv)) {
14626 DRM_DEBUG_KMS("unsupported pixel format: %s\n", 14603 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14627 drm_get_format_name(mode_cmd->pixel_format, 14604 drm_get_format_name(mode_cmd->pixel_format,
14628 &format_name)); 14605 &format_name));
@@ -14646,7 +14623,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14646 fb->height < SKL_MIN_YUV_420_SRC_H || 14623 fb->height < SKL_MIN_YUV_420_SRC_H ||
14647 (fb->width % 4) != 0 || (fb->height % 4) != 0)) { 14624 (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
14648 DRM_DEBUG_KMS("src dimensions not correct for NV12\n"); 14625 DRM_DEBUG_KMS("src dimensions not correct for NV12\n");
14649 return -EINVAL; 14626 goto err;
14650 } 14627 }
14651 14628
14652 for (i = 0; i < fb->format->num_planes; i++) { 14629 for (i = 0; i < fb->format->num_planes; i++) {
@@ -14906,174 +14883,6 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14906 dev_priv->display.update_crtcs = intel_update_crtcs; 14883 dev_priv->display.update_crtcs = intel_update_crtcs;
14907} 14884}
14908 14885
14909/*
14910 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14911 */
14912static void quirk_ssc_force_disable(struct drm_device *dev)
14913{
14914 struct drm_i915_private *dev_priv = to_i915(dev);
14915 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14916 DRM_INFO("applying lvds SSC disable quirk\n");
14917}
14918
14919/*
14920 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14921 * brightness value
14922 */
14923static void quirk_invert_brightness(struct drm_device *dev)
14924{
14925 struct drm_i915_private *dev_priv = to_i915(dev);
14926 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14927 DRM_INFO("applying inverted panel brightness quirk\n");
14928}
14929
14930/* Some VBT's incorrectly indicate no backlight is present */
14931static void quirk_backlight_present(struct drm_device *dev)
14932{
14933 struct drm_i915_private *dev_priv = to_i915(dev);
14934 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14935 DRM_INFO("applying backlight present quirk\n");
14936}
14937
14938/* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14939 * which is 300 ms greater than eDP spec T12 min.
14940 */
14941static void quirk_increase_t12_delay(struct drm_device *dev)
14942{
14943 struct drm_i915_private *dev_priv = to_i915(dev);
14944
14945 dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14946 DRM_INFO("Applying T12 delay quirk\n");
14947}
14948
14949/*
14950 * GeminiLake NUC HDMI outputs require additional off time
14951 * this allows the onboard retimer to correctly sync to signal
14952 */
14953static void quirk_increase_ddi_disabled_time(struct drm_device *dev)
14954{
14955 struct drm_i915_private *dev_priv = to_i915(dev);
14956
14957 dev_priv->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME;
14958 DRM_INFO("Applying Increase DDI Disabled quirk\n");
14959}
14960
14961struct intel_quirk {
14962 int device;
14963 int subsystem_vendor;
14964 int subsystem_device;
14965 void (*hook)(struct drm_device *dev);
14966};
14967
14968/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14969struct intel_dmi_quirk {
14970 void (*hook)(struct drm_device *dev);
14971 const struct dmi_system_id (*dmi_id_list)[];
14972};
14973
14974static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14975{
14976 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14977 return 1;
14978}
14979
14980static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14981 {
14982 .dmi_id_list = &(const struct dmi_system_id[]) {
14983 {
14984 .callback = intel_dmi_reverse_brightness,
14985 .ident = "NCR Corporation",
14986 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14987 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14988 },
14989 },
14990 { } /* terminating entry */
14991 },
14992 .hook = quirk_invert_brightness,
14993 },
14994};
14995
14996static struct intel_quirk intel_quirks[] = {
14997 /* Lenovo U160 cannot use SSC on LVDS */
14998 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14999
15000 /* Sony Vaio Y cannot use SSC on LVDS */
15001 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15002
15003 /* Acer Aspire 5734Z must invert backlight brightness */
15004 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15005
15006 /* Acer/eMachines G725 */
15007 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15008
15009 /* Acer/eMachines e725 */
15010 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15011
15012 /* Acer/Packard Bell NCL20 */
15013 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15014
15015 /* Acer Aspire 4736Z */
15016 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15017
15018 /* Acer Aspire 5336 */
15019 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15020
15021 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15022 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15023
15024 /* Acer C720 Chromebook (Core i3 4005U) */
15025 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15026
15027 /* Apple Macbook 2,1 (Core 2 T7400) */
15028 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15029
15030 /* Apple Macbook 4,1 */
15031 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15032
15033 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15034 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15035
15036 /* HP Chromebook 14 (Celeron 2955U) */
15037 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15038
15039 /* Dell Chromebook 11 */
15040 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15041
15042 /* Dell Chromebook 11 (2015 version) */
15043 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15044
15045 /* Toshiba Satellite P50-C-18C */
15046 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
15047
15048 /* GeminiLake NUC */
15049 { 0x3185, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
15050 { 0x3184, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
15051 /* ASRock ITX*/
15052 { 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
15053 { 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
15054};
15055
15056static void intel_init_quirks(struct drm_device *dev)
15057{
15058 struct pci_dev *d = dev->pdev;
15059 int i;
15060
15061 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15062 struct intel_quirk *q = &intel_quirks[i];
15063
15064 if (d->device == q->device &&
15065 (d->subsystem_vendor == q->subsystem_vendor ||
15066 q->subsystem_vendor == PCI_ANY_ID) &&
15067 (d->subsystem_device == q->subsystem_device ||
15068 q->subsystem_device == PCI_ANY_ID))
15069 q->hook(dev);
15070 }
15071 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15072 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15073 intel_dmi_quirks[i].hook(dev);
15074 }
15075}
15076
15077/* Disable the VGA plane that we never use */ 14886/* Disable the VGA plane that we never use */
15078static void i915_disable_vga(struct drm_i915_private *dev_priv) 14887static void i915_disable_vga(struct drm_i915_private *dev_priv)
15079{ 14888{
@@ -15233,6 +15042,14 @@ retry:
15233 ret = drm_atomic_add_affected_planes(state, crtc); 15042 ret = drm_atomic_add_affected_planes(state, crtc);
15234 if (ret) 15043 if (ret)
15235 goto out; 15044 goto out;
15045
15046 /*
15047 * FIXME hack to force a LUT update to avoid the
15048 * plane update forcing the pipe gamma on without
15049 * having a proper LUT loaded. Remove once we
15050 * have readout for pipe gamma enable.
15051 */
15052 crtc_state->color_mgmt_changed = true;
15236 } 15053 }
15237 } 15054 }
15238 15055
@@ -15279,7 +15096,9 @@ int intel_modeset_init(struct drm_device *dev)
15279 INIT_WORK(&dev_priv->atomic_helper.free_work, 15096 INIT_WORK(&dev_priv->atomic_helper.free_work,
15280 intel_atomic_helper_free_state_worker); 15097 intel_atomic_helper_free_state_worker);
15281 15098
15282 intel_init_quirks(dev); 15099 intel_init_quirks(dev_priv);
15100
15101 intel_fbc_init(dev_priv);
15283 15102
15284 intel_init_pm(dev_priv); 15103 intel_init_pm(dev_priv);
15285 15104
@@ -15511,8 +15330,8 @@ intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
15511 if (pipe == crtc->pipe) 15330 if (pipe == crtc->pipe)
15512 continue; 15331 continue;
15513 15332
15514 DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling plane\n", 15333 DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
15515 plane->base.name); 15334 plane->base.base.id, plane->base.name);
15516 15335
15517 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 15336 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15518 intel_plane_disable_noatomic(plane_crtc, plane); 15337 intel_plane_disable_noatomic(plane_crtc, plane);
@@ -15553,7 +15372,8 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
15553{ 15372{
15554 struct drm_device *dev = crtc->base.dev; 15373 struct drm_device *dev = crtc->base.dev;
15555 struct drm_i915_private *dev_priv = to_i915(dev); 15374 struct drm_i915_private *dev_priv = to_i915(dev);
15556 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; 15375 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
15376 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
15557 15377
15558 /* Clear any frame start delays used for debugging left by the BIOS */ 15378 /* Clear any frame start delays used for debugging left by the BIOS */
15559 if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) { 15379 if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
@@ -15563,7 +15383,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
15563 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); 15383 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15564 } 15384 }
15565 15385
15566 if (crtc->active) { 15386 if (crtc_state->base.active) {
15567 struct intel_plane *plane; 15387 struct intel_plane *plane;
15568 15388
15569 /* Disable everything but the primary plane */ 15389 /* Disable everything but the primary plane */
@@ -15579,10 +15399,10 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
15579 15399
15580 /* Adjust the state of the output pipe according to whether we 15400 /* Adjust the state of the output pipe according to whether we
15581 * have active connectors/encoders. */ 15401 * have active connectors/encoders. */
15582 if (crtc->active && !intel_crtc_has_encoders(crtc)) 15402 if (crtc_state->base.active && !intel_crtc_has_encoders(crtc))
15583 intel_crtc_disable_noatomic(&crtc->base, ctx); 15403 intel_crtc_disable_noatomic(&crtc->base, ctx);
15584 15404
15585 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) { 15405 if (crtc_state->base.active || HAS_GMCH_DISPLAY(dev_priv)) {
15586 /* 15406 /*
15587 * We start out with underrun reporting disabled to avoid races. 15407 * We start out with underrun reporting disabled to avoid races.
15588 * For correct bookkeeping mark this on active crtcs. 15408 * For correct bookkeeping mark this on active crtcs.
@@ -15613,6 +15433,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
15613 15433
15614static void intel_sanitize_encoder(struct intel_encoder *encoder) 15434static void intel_sanitize_encoder(struct intel_encoder *encoder)
15615{ 15435{
15436 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
15616 struct intel_connector *connector; 15437 struct intel_connector *connector;
15617 15438
15618 /* We need to check both for a crtc link (meaning that the 15439 /* We need to check both for a crtc link (meaning that the
@@ -15636,7 +15457,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
15636 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", 15457 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15637 encoder->base.base.id, 15458 encoder->base.base.id,
15638 encoder->base.name); 15459 encoder->base.name);
15639 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); 15460 if (encoder->disable)
15461 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15640 if (encoder->post_disable) 15462 if (encoder->post_disable)
15641 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); 15463 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15642 } 15464 }
@@ -15653,6 +15475,9 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
15653 15475
15654 /* notify opregion of the sanitized encoder state */ 15476 /* notify opregion of the sanitized encoder state */
15655 intel_opregion_notify_encoder(encoder, connector && has_active_crtc); 15477 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
15478
15479 if (INTEL_GEN(dev_priv) >= 11)
15480 icl_sanitize_encoder_pll_mapping(encoder);
15656} 15481}
15657 15482
15658void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) 15483void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
@@ -15701,6 +15526,10 @@ static void readout_plane_state(struct drm_i915_private *dev_priv)
15701 crtc_state = to_intel_crtc_state(crtc->base.state); 15526 crtc_state = to_intel_crtc_state(crtc->base.state);
15702 15527
15703 intel_set_plane_visible(crtc_state, plane_state, visible); 15528 intel_set_plane_visible(crtc_state, plane_state, visible);
15529
15530 DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
15531 plane->base.base.id, plane->base.name,
15532 enableddisabled(visible), pipe_name(pipe));
15704 } 15533 }
15705 15534
15706 for_each_intel_crtc(&dev_priv->drm, crtc) { 15535 for_each_intel_crtc(&dev_priv->drm, crtc) {
@@ -15853,7 +15682,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
15853 15682
15854 drm_calc_timestamping_constants(&crtc->base, 15683 drm_calc_timestamping_constants(&crtc->base,
15855 &crtc_state->base.adjusted_mode); 15684 &crtc_state->base.adjusted_mode);
15856 update_scanline_offset(crtc); 15685 update_scanline_offset(crtc_state);
15857 } 15686 }
15858 15687
15859 dev_priv->min_cdclk[crtc->pipe] = min_cdclk; 15688 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
@@ -15908,6 +15737,65 @@ static void intel_early_display_was(struct drm_i915_private *dev_priv)
15908 } 15737 }
15909} 15738}
15910 15739
15740static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
15741 enum port port, i915_reg_t hdmi_reg)
15742{
15743 u32 val = I915_READ(hdmi_reg);
15744
15745 if (val & SDVO_ENABLE ||
15746 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
15747 return;
15748
15749 DRM_DEBUG_KMS("Sanitizing transcoder select for HDMI %c\n",
15750 port_name(port));
15751
15752 val &= ~SDVO_PIPE_SEL_MASK;
15753 val |= SDVO_PIPE_SEL(PIPE_A);
15754
15755 I915_WRITE(hdmi_reg, val);
15756}
15757
15758static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
15759 enum port port, i915_reg_t dp_reg)
15760{
15761 u32 val = I915_READ(dp_reg);
15762
15763 if (val & DP_PORT_EN ||
15764 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
15765 return;
15766
15767 DRM_DEBUG_KMS("Sanitizing transcoder select for DP %c\n",
15768 port_name(port));
15769
15770 val &= ~DP_PIPE_SEL_MASK;
15771 val |= DP_PIPE_SEL(PIPE_A);
15772
15773 I915_WRITE(dp_reg, val);
15774}
15775
15776static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
15777{
15778 /*
15779 * The BIOS may select transcoder B on some of the PCH
15780 * ports even it doesn't enable the port. This would trip
15781 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
15782 * Sanitize the transcoder select bits to prevent that. We
15783 * assume that the BIOS never actually enabled the port,
15784 * because if it did we'd actually have to toggle the port
15785 * on and back off to make the transcoder A select stick
15786 * (see. intel_dp_link_down(), intel_disable_hdmi(),
15787 * intel_disable_sdvo()).
15788 */
15789 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
15790 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
15791 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
15792
15793 /* PCH SDVOB multiplex with HDMIB */
15794 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
15795 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
15796 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
15797}
15798
15911/* Scan out the current hw modeset state, 15799/* Scan out the current hw modeset state,
15912 * and sanitizes it to the current state 15800 * and sanitizes it to the current state
15913 */ 15801 */
@@ -15917,6 +15805,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
15917{ 15805{
15918 struct drm_i915_private *dev_priv = to_i915(dev); 15806 struct drm_i915_private *dev_priv = to_i915(dev);
15919 struct intel_crtc *crtc; 15807 struct intel_crtc *crtc;
15808 struct intel_crtc_state *crtc_state;
15920 struct intel_encoder *encoder; 15809 struct intel_encoder *encoder;
15921 int i; 15810 int i;
15922 15811
@@ -15928,6 +15817,9 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
15928 /* HW state is read out, now we need to sanitize this mess. */ 15817 /* HW state is read out, now we need to sanitize this mess. */
15929 get_encoder_power_domains(dev_priv); 15818 get_encoder_power_domains(dev_priv);
15930 15819
15820 if (HAS_PCH_IBX(dev_priv))
15821 ibx_sanitize_pch_ports(dev_priv);
15822
15931 /* 15823 /*
15932 * intel_sanitize_plane_mapping() may need to do vblank 15824 * intel_sanitize_plane_mapping() may need to do vblank
15933 * waits, so we need vblank interrupts restored beforehand. 15825 * waits, so we need vblank interrupts restored beforehand.
@@ -15935,7 +15827,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
15935 for_each_intel_crtc(&dev_priv->drm, crtc) { 15827 for_each_intel_crtc(&dev_priv->drm, crtc) {
15936 drm_crtc_vblank_reset(&crtc->base); 15828 drm_crtc_vblank_reset(&crtc->base);
15937 15829
15938 if (crtc->active) 15830 if (crtc->base.state->active)
15939 drm_crtc_vblank_on(&crtc->base); 15831 drm_crtc_vblank_on(&crtc->base);
15940 } 15832 }
15941 15833
@@ -15945,8 +15837,9 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
15945 intel_sanitize_encoder(encoder); 15837 intel_sanitize_encoder(encoder);
15946 15838
15947 for_each_intel_crtc(&dev_priv->drm, crtc) { 15839 for_each_intel_crtc(&dev_priv->drm, crtc) {
15840 crtc_state = to_intel_crtc_state(crtc->base.state);
15948 intel_sanitize_crtc(crtc, ctx); 15841 intel_sanitize_crtc(crtc, ctx);
15949 intel_dump_pipe_config(crtc, crtc->config, 15842 intel_dump_pipe_config(crtc, crtc_state,
15950 "[setup_hw_state]"); 15843 "[setup_hw_state]");
15951 } 15844 }
15952 15845
@@ -15980,7 +15873,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
15980 for_each_intel_crtc(dev, crtc) { 15873 for_each_intel_crtc(dev, crtc) {
15981 u64 put_domains; 15874 u64 put_domains;
15982 15875
15983 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); 15876 crtc_state = to_intel_crtc_state(crtc->base.state);
15877 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc_state);
15984 if (WARN_ON(put_domains)) 15878 if (WARN_ON(put_domains))
15985 modeset_put_power_domains(dev_priv, put_domains); 15879 modeset_put_power_domains(dev_priv, put_domains);
15986 } 15880 }
@@ -16024,29 +15918,6 @@ void intel_display_resume(struct drm_device *dev)
16024 drm_atomic_state_put(state); 15918 drm_atomic_state_put(state);
16025} 15919}
16026 15920
16027int intel_connector_register(struct drm_connector *connector)
16028{
16029 struct intel_connector *intel_connector = to_intel_connector(connector);
16030 int ret;
16031
16032 ret = intel_backlight_device_register(intel_connector);
16033 if (ret)
16034 goto err;
16035
16036 return 0;
16037
16038err:
16039 return ret;
16040}
16041
16042void intel_connector_unregister(struct drm_connector *connector)
16043{
16044 struct intel_connector *intel_connector = to_intel_connector(connector);
16045
16046 intel_backlight_device_unregister(intel_connector);
16047 intel_panel_destroy_backlight(connector);
16048}
16049
16050static void intel_hpd_poll_fini(struct drm_device *dev) 15921static void intel_hpd_poll_fini(struct drm_device *dev)
16051{ 15922{
16052 struct intel_connector *connector; 15923 struct intel_connector *connector;
@@ -16057,9 +15928,9 @@ static void intel_hpd_poll_fini(struct drm_device *dev)
16057 for_each_intel_connector_iter(connector, &conn_iter) { 15928 for_each_intel_connector_iter(connector, &conn_iter) {
16058 if (connector->modeset_retry_work.func) 15929 if (connector->modeset_retry_work.func)
16059 cancel_work_sync(&connector->modeset_retry_work); 15930 cancel_work_sync(&connector->modeset_retry_work);
16060 if (connector->hdcp_shim) { 15931 if (connector->hdcp.shim) {
16061 cancel_delayed_work_sync(&connector->hdcp_check_work); 15932 cancel_delayed_work_sync(&connector->hdcp.check_work);
16062 cancel_work_sync(&connector->hdcp_prop_work); 15933 cancel_work_sync(&connector->hdcp.prop_work);
16063 } 15934 }
16064 } 15935 }
16065 drm_connector_list_iter_end(&conn_iter); 15936 drm_connector_list_iter_end(&conn_iter);
@@ -16099,18 +15970,13 @@ void intel_modeset_cleanup(struct drm_device *dev)
16099 15970
16100 drm_mode_config_cleanup(dev); 15971 drm_mode_config_cleanup(dev);
16101 15972
16102 intel_cleanup_overlay(dev_priv); 15973 intel_overlay_cleanup(dev_priv);
16103 15974
16104 intel_teardown_gmbus(dev_priv); 15975 intel_teardown_gmbus(dev_priv);
16105 15976
16106 destroy_workqueue(dev_priv->modeset_wq); 15977 destroy_workqueue(dev_priv->modeset_wq);
16107}
16108 15978
16109void intel_connector_attach_encoder(struct intel_connector *connector, 15979 intel_fbc_cleanup_cfb(dev_priv);
16110 struct intel_encoder *encoder)
16111{
16112 connector->encoder = encoder;
16113 drm_connector_attach_encoder(&connector->base, &encoder->base);
16114} 15980}
16115 15981
16116/* 15982/*
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-23 16:34:58 -0400