1 files changed, 11 insertions, 46 deletions

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 29075c763428..25e3aba9cded 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2138,16 +2138,8 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv,
 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
                                      int pixel_rate)
 {
-        if (INTEL_GEN(dev_priv) >= 10)
+        if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
                 return DIV_ROUND_UP(pixel_rate, 2);
-        else if (IS_GEMINILAKE(dev_priv))
-                /*
-                 * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
-                 * as a temporary workaround. Use a higher cdclk instead. (Note that
-                 * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
-                 * cdclk.)
-                 */
-                return DIV_ROUND_UP(pixel_rate * 100, 2 * 99);
         else if (IS_GEN9(dev_priv) ||
                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
                 return pixel_rate;
@@ -2543,14 +2535,8 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
 {
         int max_cdclk_freq = dev_priv->max_cdclk_freq;
 
-        if (INTEL_GEN(dev_priv) >= 10)
+        if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
                 return 2 * max_cdclk_freq;
-        else if (IS_GEMINILAKE(dev_priv))
-                /*
-                 * FIXME: Limiting to 99% as a temporary workaround. See
-                 * intel_min_cdclk() for details.
-                 */
-                return 2 * max_cdclk_freq * 99 / 100;
         else if (IS_GEN9(dev_priv) ||
                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
                 return max_cdclk_freq;
@@ -2674,37 +2660,18 @@ static int cnp_rawclk(struct drm_i915_private *dev_priv)
                 fraction = 200;
         }
 
-        rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1);
-        if (fraction)
-                rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
-                                                            fraction) - 1);
-
-        I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
-        return divider + fraction;
-}
+        rawclk = CNP_RAWCLK_DIV(divider / 1000);
+        if (fraction) {
+                int numerator = 1;
 
-static int icp_rawclk(struct drm_i915_private *dev_priv)
-{
-        u32 rawclk;
-        int divider, numerator, denominator, frequency;
-
-        if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
-                frequency = 24000;
-                divider = 23;
-                numerator = 0;
-                denominator = 0;
-        } else {
-                frequency = 19200;
-                divider = 18;
-                numerator = 1;
-                denominator = 4;
+                rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
+                                                           fraction) - 1);
+                if (HAS_PCH_ICP(dev_priv))
+                        rawclk |= ICP_RAWCLK_NUM(numerator);
         }
 
-        rawclk = CNP_RAWCLK_DIV(divider) | ICP_RAWCLK_NUM(numerator) |
-                 ICP_RAWCLK_DEN(denominator);
-
         I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
-        return frequency;
+        return divider + fraction;
 }
 
 static int pch_rawclk(struct drm_i915_private *dev_priv)
@@ -2754,9 +2721,7 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv)
  */
 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 {
-        if (HAS_PCH_ICP(dev_priv))
-                dev_priv->rawclk_freq = icp_rawclk(dev_priv);
-        else if (HAS_PCH_CNP(dev_priv))
+        if (HAS_PCH_CNP(dev_priv) || HAS_PCH_ICP(dev_priv))
                 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
         else if (HAS_PCH_SPLIT(dev_priv))
                 dev_priv->rawclk_freq = pch_rawclk(dev_priv);