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path: root/drivers/gpu/drm/i915/i915_reg.h
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h822
1 files changed, 614 insertions, 208 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7c491ea3d052..47baf2fe8f71 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -157,20 +157,37 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
157/* 157/*
158 * Named helper wrappers around _PICK_EVEN() and _PICK(). 158 * Named helper wrappers around _PICK_EVEN() and _PICK().
159 */ 159 */
160#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) 160#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
161#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) 161#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
162#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) 162#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
163#define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b) 163#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
164#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) 164#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
165#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) 165
166#define _PORT(port, a, b) _PICK_EVEN(port, a, b) 166#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
167#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) 167#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
168#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 168#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
169#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 169#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
170#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) 170#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
171#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) 171
172#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) 172#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
173#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) 173
174#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
175#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
176#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
177
178/*
179 * Device info offset array based helpers for groups of registers with unevenly
180 * spaced base offsets.
181 */
182#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
183 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
184 dev_priv->info.display_mmio_offset)
185#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
186 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
187 dev_priv->info.display_mmio_offset)
188#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
189 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
190 dev_priv->info.display_mmio_offset)
174 191
175#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) 192#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
176#define _MASKED_FIELD(mask, value) ({ \ 193#define _MASKED_FIELD(mask, value) ({ \
@@ -1631,35 +1648,6 @@ enum i915_power_well_id {
1631#define PHY_RESERVED (1 << 7) 1648#define PHY_RESERVED (1 << 7)
1632#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC) 1649#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
1633 1650
1634#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
1635#define CL_POWER_DOWN_ENABLE (1 << 4)
1636#define SUS_CLOCK_CONFIG (3 << 0)
1637
1638#define _ICL_PORT_CL_DW5_A 0x162014
1639#define _ICL_PORT_CL_DW5_B 0x6C014
1640#define ICL_PORT_CL_DW5(port) _MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
1641 _ICL_PORT_CL_DW5_B)
1642
1643#define _CNL_PORT_CL_DW10_A 0x162028
1644#define _ICL_PORT_CL_DW10_B 0x6c028
1645#define ICL_PORT_CL_DW10(port) _MMIO_PORT(port, \
1646 _CNL_PORT_CL_DW10_A, \
1647 _ICL_PORT_CL_DW10_B)
1648#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
1649#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
1650#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
1651#define PWR_UP_ALL_LANES (0x0 << 4)
1652#define PWR_DOWN_LN_3_2_1 (0xe << 4)
1653#define PWR_DOWN_LN_3_2 (0xc << 4)
1654#define PWR_DOWN_LN_3 (0x8 << 4)
1655#define PWR_DOWN_LN_2_1_0 (0x7 << 4)
1656#define PWR_DOWN_LN_1_0 (0x3 << 4)
1657#define PWR_DOWN_LN_1 (0x2 << 4)
1658#define PWR_DOWN_LN_3_1 (0xa << 4)
1659#define PWR_DOWN_LN_3_1_0 (0xb << 4)
1660#define PWR_DOWN_LN_MASK (0xf << 4)
1661#define PWR_DOWN_LN_SHIFT 4
1662
1663#define _PORT_CL1CM_DW9_A 0x162024 1651#define _PORT_CL1CM_DW9_A 0x162024
1664#define _PORT_CL1CM_DW9_BC 0x6C024 1652#define _PORT_CL1CM_DW9_BC 0x6C024
1665#define IREF0RC_OFFSET_SHIFT 8 1653#define IREF0RC_OFFSET_SHIFT 8
@@ -1672,13 +1660,6 @@ enum i915_power_well_id {
1672#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) 1660#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1673#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC) 1661#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1674 1662
1675#define _ICL_PORT_CL_DW12_A 0x162030
1676#define _ICL_PORT_CL_DW12_B 0x6C030
1677#define ICL_LANE_ENABLE_AUX (1 << 0)
1678#define ICL_PORT_CL_DW12(port) _MMIO_PORT((port), \
1679 _ICL_PORT_CL_DW12_A, \
1680 _ICL_PORT_CL_DW12_B)
1681
1682#define _PORT_CL1CM_DW28_A 0x162070 1663#define _PORT_CL1CM_DW28_A 0x162070
1683#define _PORT_CL1CM_DW28_BC 0x6C070 1664#define _PORT_CL1CM_DW28_BC 0x6C070
1684#define OCL1_POWER_DOWN_EN (1 << 23) 1665#define OCL1_POWER_DOWN_EN (1 << 23)
@@ -1691,6 +1672,74 @@ enum i915_power_well_id {
1691#define OCL2_LDOFUSE_PWR_DIS (1 << 6) 1672#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1692#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC) 1673#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1693 1674
1675/*
1676 * CNL/ICL Port/COMBO-PHY Registers
1677 */
1678#define _ICL_COMBOPHY_A 0x162000
1679#define _ICL_COMBOPHY_B 0x6C000
1680#define _ICL_COMBOPHY(port) _PICK(port, _ICL_COMBOPHY_A, \
1681 _ICL_COMBOPHY_B)
1682
1683/* CNL/ICL Port CL_DW registers */
1684#define _ICL_PORT_CL_DW(dw, port) (_ICL_COMBOPHY(port) + \
1685 4 * (dw))
1686
1687#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
1688#define ICL_PORT_CL_DW5(port) _MMIO(_ICL_PORT_CL_DW(5, port))
1689#define CL_POWER_DOWN_ENABLE (1 << 4)
1690#define SUS_CLOCK_CONFIG (3 << 0)
1691
1692#define ICL_PORT_CL_DW10(port) _MMIO(_ICL_PORT_CL_DW(10, port))
1693#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
1694#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
1695#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
1696#define PWR_UP_ALL_LANES (0x0 << 4)
1697#define PWR_DOWN_LN_3_2_1 (0xe << 4)
1698#define PWR_DOWN_LN_3_2 (0xc << 4)
1699#define PWR_DOWN_LN_3 (0x8 << 4)
1700#define PWR_DOWN_LN_2_1_0 (0x7 << 4)
1701#define PWR_DOWN_LN_1_0 (0x3 << 4)
1702#define PWR_DOWN_LN_1 (0x2 << 4)
1703#define PWR_DOWN_LN_3_1 (0xa << 4)
1704#define PWR_DOWN_LN_3_1_0 (0xb << 4)
1705#define PWR_DOWN_LN_MASK (0xf << 4)
1706#define PWR_DOWN_LN_SHIFT 4
1707
1708#define ICL_PORT_CL_DW12(port) _MMIO(_ICL_PORT_CL_DW(12, port))
1709#define ICL_LANE_ENABLE_AUX (1 << 0)
1710
1711/* CNL/ICL Port COMP_DW registers */
1712#define _ICL_PORT_COMP 0x100
1713#define _ICL_PORT_COMP_DW(dw, port) (_ICL_COMBOPHY(port) + \
1714 _ICL_PORT_COMP + 4 * (dw))
1715
1716#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
1717#define ICL_PORT_COMP_DW0(port) _MMIO(_ICL_PORT_COMP_DW(0, port))
1718#define COMP_INIT (1 << 31)
1719
1720#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
1721#define ICL_PORT_COMP_DW1(port) _MMIO(_ICL_PORT_COMP_DW(1, port))
1722
1723#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
1724#define ICL_PORT_COMP_DW3(port) _MMIO(_ICL_PORT_COMP_DW(3, port))
1725#define PROCESS_INFO_DOT_0 (0 << 26)
1726#define PROCESS_INFO_DOT_1 (1 << 26)
1727#define PROCESS_INFO_DOT_4 (2 << 26)
1728#define PROCESS_INFO_MASK (7 << 26)
1729#define PROCESS_INFO_SHIFT 26
1730#define VOLTAGE_INFO_0_85V (0 << 24)
1731#define VOLTAGE_INFO_0_95V (1 << 24)
1732#define VOLTAGE_INFO_1_05V (2 << 24)
1733#define VOLTAGE_INFO_MASK (3 << 24)
1734#define VOLTAGE_INFO_SHIFT 24
1735
1736#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
1737#define ICL_PORT_COMP_DW9(port) _MMIO(_ICL_PORT_COMP_DW(9, port))
1738
1739#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
1740#define ICL_PORT_COMP_DW10(port) _MMIO(_ICL_PORT_COMP_DW(10, port))
1741
1742/* CNL/ICL Port PCS registers */
1694#define _CNL_PORT_PCS_DW1_GRP_AE 0x162304 1743#define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
1695#define _CNL_PORT_PCS_DW1_GRP_B 0x162384 1744#define _CNL_PORT_PCS_DW1_GRP_B 0x162384
1696#define _CNL_PORT_PCS_DW1_GRP_C 0x162B04 1745#define _CNL_PORT_PCS_DW1_GRP_C 0x162B04
@@ -1708,7 +1757,6 @@ enum i915_power_well_id {
1708 _CNL_PORT_PCS_DW1_GRP_D, \ 1757 _CNL_PORT_PCS_DW1_GRP_D, \
1709 _CNL_PORT_PCS_DW1_GRP_AE, \ 1758 _CNL_PORT_PCS_DW1_GRP_AE, \
1710 _CNL_PORT_PCS_DW1_GRP_F)) 1759 _CNL_PORT_PCS_DW1_GRP_F))
1711
1712#define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \ 1760#define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \
1713 _CNL_PORT_PCS_DW1_LN0_AE, \ 1761 _CNL_PORT_PCS_DW1_LN0_AE, \
1714 _CNL_PORT_PCS_DW1_LN0_B, \ 1762 _CNL_PORT_PCS_DW1_LN0_B, \
@@ -1717,24 +1765,21 @@ enum i915_power_well_id {
1717 _CNL_PORT_PCS_DW1_LN0_AE, \ 1765 _CNL_PORT_PCS_DW1_LN0_AE, \
1718 _CNL_PORT_PCS_DW1_LN0_F)) 1766 _CNL_PORT_PCS_DW1_LN0_F))
1719 1767
1720#define _ICL_PORT_PCS_DW1_GRP_A 0x162604 1768#define _ICL_PORT_PCS_AUX 0x300
1721#define _ICL_PORT_PCS_DW1_GRP_B 0x6C604 1769#define _ICL_PORT_PCS_GRP 0x600
1722#define _ICL_PORT_PCS_DW1_LN0_A 0x162804 1770#define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
1723#define _ICL_PORT_PCS_DW1_LN0_B 0x6C804 1771#define _ICL_PORT_PCS_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \
1724#define _ICL_PORT_PCS_DW1_AUX_A 0x162304 1772 _ICL_PORT_PCS_AUX + 4 * (dw))
1725#define _ICL_PORT_PCS_DW1_AUX_B 0x6c304 1773#define _ICL_PORT_PCS_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \
1726#define ICL_PORT_PCS_DW1_GRP(port) _MMIO_PORT(port,\ 1774 _ICL_PORT_PCS_GRP + 4 * (dw))
1727 _ICL_PORT_PCS_DW1_GRP_A, \ 1775#define _ICL_PORT_PCS_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
1728 _ICL_PORT_PCS_DW1_GRP_B) 1776 _ICL_PORT_PCS_LN(ln) + 4 * (dw))
1729#define ICL_PORT_PCS_DW1_LN0(port) _MMIO_PORT(port, \ 1777#define ICL_PORT_PCS_DW1_AUX(port) _MMIO(_ICL_PORT_PCS_DW_AUX(1, port))
1730 _ICL_PORT_PCS_DW1_LN0_A, \ 1778#define ICL_PORT_PCS_DW1_GRP(port) _MMIO(_ICL_PORT_PCS_DW_GRP(1, port))
1731 _ICL_PORT_PCS_DW1_LN0_B) 1779#define ICL_PORT_PCS_DW1_LN0(port) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port))
1732#define ICL_PORT_PCS_DW1_AUX(port) _MMIO_PORT(port, \
1733 _ICL_PORT_PCS_DW1_AUX_A, \
1734 _ICL_PORT_PCS_DW1_AUX_B)
1735#define COMMON_KEEPER_EN (1 << 26) 1780#define COMMON_KEEPER_EN (1 << 26)
1736 1781
1737/* CNL Port TX registers */ 1782/* CNL/ICL Port TX registers */
1738#define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340 1783#define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
1739#define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0 1784#define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0
1740#define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40 1785#define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40
@@ -1762,23 +1807,22 @@ enum i915_power_well_id {
1762 _CNL_PORT_TX_F_LN0_OFFSET) + \ 1807 _CNL_PORT_TX_F_LN0_OFFSET) + \
1763 4 * (dw)) 1808 4 * (dw))
1764 1809
1765#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 2)) 1810#define _ICL_PORT_TX_AUX 0x380
1766#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 2)) 1811#define _ICL_PORT_TX_GRP 0x680
1767#define _ICL_PORT_TX_DW2_GRP_A 0x162688 1812#define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
1768#define _ICL_PORT_TX_DW2_GRP_B 0x6C688 1813
1769#define _ICL_PORT_TX_DW2_LN0_A 0x162888 1814#define _ICL_PORT_TX_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \
1770#define _ICL_PORT_TX_DW2_LN0_B 0x6C888 1815 _ICL_PORT_TX_AUX + 4 * (dw))
1771#define _ICL_PORT_TX_DW2_AUX_A 0x162388 1816#define _ICL_PORT_TX_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \
1772#define _ICL_PORT_TX_DW2_AUX_B 0x6c388 1817 _ICL_PORT_TX_GRP + 4 * (dw))
1773#define ICL_PORT_TX_DW2_GRP(port) _MMIO_PORT(port, \ 1818#define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
1774 _ICL_PORT_TX_DW2_GRP_A, \ 1819 _ICL_PORT_TX_LN(ln) + 4 * (dw))
1775 _ICL_PORT_TX_DW2_GRP_B) 1820
1776#define ICL_PORT_TX_DW2_LN0(port) _MMIO_PORT(port, \ 1821#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
1777 _ICL_PORT_TX_DW2_LN0_A, \ 1822#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
1778 _ICL_PORT_TX_DW2_LN0_B) 1823#define ICL_PORT_TX_DW2_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(2, port))
1779#define ICL_PORT_TX_DW2_AUX(port) _MMIO_PORT(port, \ 1824#define ICL_PORT_TX_DW2_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(2, port))
1780 _ICL_PORT_TX_DW2_AUX_A, \ 1825#define ICL_PORT_TX_DW2_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, port))
1781 _ICL_PORT_TX_DW2_AUX_B)
1782#define SWING_SEL_UPPER(x) (((x) >> 3) << 15) 1826#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
1783#define SWING_SEL_UPPER_MASK (1 << 15) 1827#define SWING_SEL_UPPER_MASK (1 << 15)
1784#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11) 1828#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
@@ -1795,24 +1839,10 @@ enum i915_power_well_id {
1795#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \ 1839#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
1796 ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \ 1840 ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
1797 _CNL_PORT_TX_DW4_LN0_AE))) 1841 _CNL_PORT_TX_DW4_LN0_AE)))
1798#define _ICL_PORT_TX_DW4_GRP_A 0x162690 1842#define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port))
1799#define _ICL_PORT_TX_DW4_GRP_B 0x6C690 1843#define ICL_PORT_TX_DW4_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(4, port))
1800#define _ICL_PORT_TX_DW4_LN0_A 0x162890 1844#define ICL_PORT_TX_DW4_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, port))
1801#define _ICL_PORT_TX_DW4_LN1_A 0x162990 1845#define ICL_PORT_TX_DW4_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, port))
1802#define _ICL_PORT_TX_DW4_LN0_B 0x6C890
1803#define _ICL_PORT_TX_DW4_AUX_A 0x162390
1804#define _ICL_PORT_TX_DW4_AUX_B 0x6c390
1805#define ICL_PORT_TX_DW4_GRP(port) _MMIO_PORT(port, \
1806 _ICL_PORT_TX_DW4_GRP_A, \
1807 _ICL_PORT_TX_DW4_GRP_B)
1808#define ICL_PORT_TX_DW4_LN(port, ln) _MMIO(_PORT(port, \
1809 _ICL_PORT_TX_DW4_LN0_A, \
1810 _ICL_PORT_TX_DW4_LN0_B) + \
1811 ((ln) * (_ICL_PORT_TX_DW4_LN1_A - \
1812 _ICL_PORT_TX_DW4_LN0_A)))
1813#define ICL_PORT_TX_DW4_AUX(port) _MMIO_PORT(port, \
1814 _ICL_PORT_TX_DW4_AUX_A, \
1815 _ICL_PORT_TX_DW4_AUX_B)
1816#define LOADGEN_SELECT (1 << 31) 1846#define LOADGEN_SELECT (1 << 31)
1817#define POST_CURSOR_1(x) ((x) << 12) 1847#define POST_CURSOR_1(x) ((x) << 12)
1818#define POST_CURSOR_1_MASK (0x3F << 12) 1848#define POST_CURSOR_1_MASK (0x3F << 12)
@@ -1821,23 +1851,11 @@ enum i915_power_well_id {
1821#define CURSOR_COEFF(x) ((x) << 0) 1851#define CURSOR_COEFF(x) ((x) << 0)
1822#define CURSOR_COEFF_MASK (0x3F << 0) 1852#define CURSOR_COEFF_MASK (0x3F << 0)
1823 1853
1824#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 5)) 1854#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
1825#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 5)) 1855#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
1826#define _ICL_PORT_TX_DW5_GRP_A 0x162694 1856#define ICL_PORT_TX_DW5_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(5, port))
1827#define _ICL_PORT_TX_DW5_GRP_B 0x6C694 1857#define ICL_PORT_TX_DW5_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(5, port))
1828#define _ICL_PORT_TX_DW5_LN0_A 0x162894 1858#define ICL_PORT_TX_DW5_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, port))
1829#define _ICL_PORT_TX_DW5_LN0_B 0x6C894
1830#define _ICL_PORT_TX_DW5_AUX_A 0x162394
1831#define _ICL_PORT_TX_DW5_AUX_B 0x6c394
1832#define ICL_PORT_TX_DW5_GRP(port) _MMIO_PORT(port, \
1833 _ICL_PORT_TX_DW5_GRP_A, \
1834 _ICL_PORT_TX_DW5_GRP_B)
1835#define ICL_PORT_TX_DW5_LN0(port) _MMIO_PORT(port, \
1836 _ICL_PORT_TX_DW5_LN0_A, \
1837 _ICL_PORT_TX_DW5_LN0_B)
1838#define ICL_PORT_TX_DW5_AUX(port) _MMIO_PORT(port, \
1839 _ICL_PORT_TX_DW5_AUX_A, \
1840 _ICL_PORT_TX_DW5_AUX_B)
1841#define TX_TRAINING_EN (1 << 31) 1859#define TX_TRAINING_EN (1 << 31)
1842#define TAP2_DISABLE (1 << 30) 1860#define TAP2_DISABLE (1 << 30)
1843#define TAP3_DISABLE (1 << 29) 1861#define TAP3_DISABLE (1 << 29)
@@ -2054,49 +2072,16 @@ enum i915_power_well_id {
2054#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC) 2072#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
2055#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) 2073#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
2056 2074
2057#define CNL_PORT_COMP_DW0 _MMIO(0x162100) 2075#define FIA1_BASE 0x163000
2058#define COMP_INIT (1 << 31)
2059#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
2060#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
2061#define PROCESS_INFO_DOT_0 (0 << 26)
2062#define PROCESS_INFO_DOT_1 (1 << 26)
2063#define PROCESS_INFO_DOT_4 (2 << 26)
2064#define PROCESS_INFO_MASK (7 << 26)
2065#define PROCESS_INFO_SHIFT 26
2066#define VOLTAGE_INFO_0_85V (0 << 24)
2067#define VOLTAGE_INFO_0_95V (1 << 24)
2068#define VOLTAGE_INFO_1_05V (2 << 24)
2069#define VOLTAGE_INFO_MASK (3 << 24)
2070#define VOLTAGE_INFO_SHIFT 24
2071#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
2072#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
2073
2074#define _ICL_PORT_COMP_DW0_A 0x162100
2075#define _ICL_PORT_COMP_DW0_B 0x6C100
2076#define ICL_PORT_COMP_DW0(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
2077 _ICL_PORT_COMP_DW0_B)
2078#define _ICL_PORT_COMP_DW1_A 0x162104
2079#define _ICL_PORT_COMP_DW1_B 0x6C104
2080#define ICL_PORT_COMP_DW1(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
2081 _ICL_PORT_COMP_DW1_B)
2082#define _ICL_PORT_COMP_DW3_A 0x16210C
2083#define _ICL_PORT_COMP_DW3_B 0x6C10C
2084#define ICL_PORT_COMP_DW3(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
2085 _ICL_PORT_COMP_DW3_B)
2086#define _ICL_PORT_COMP_DW9_A 0x162124
2087#define _ICL_PORT_COMP_DW9_B 0x6C124
2088#define ICL_PORT_COMP_DW9(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
2089 _ICL_PORT_COMP_DW9_B)
2090#define _ICL_PORT_COMP_DW10_A 0x162128
2091#define _ICL_PORT_COMP_DW10_B 0x6C128
2092#define ICL_PORT_COMP_DW10(port) _MMIO_PORT(port, \
2093 _ICL_PORT_COMP_DW10_A, \
2094 _ICL_PORT_COMP_DW10_B)
2095 2076
2096/* ICL PHY DFLEX registers */ 2077/* ICL PHY DFLEX registers */
2097#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0) 2078#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0)
2098#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n))) 2079#define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
2099#define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n))) 2080#define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
2081#define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
2082#define DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port)))
2083#define DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) (12 << (4 * (tc_port)))
2084#define DFLEXDPMLE1_DPMLETC_ML3_0(tc_port) (15 << (4 * (tc_port)))
2100 2085
2101/* BXT PHY Ref registers */ 2086/* BXT PHY Ref registers */
2102#define _PORT_REF_DW3_A 0x16218C 2087#define _PORT_REF_DW3_A 0x16218C
@@ -2413,6 +2398,7 @@ enum i915_power_well_id {
2413 2398
2414#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080) 2399#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2415#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF 2400#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2401#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
2416 2402
2417#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8) 2403#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
2418#define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31) 2404#define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31)
@@ -2573,6 +2559,7 @@ enum i915_power_well_id {
2573/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */ 2559/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
2574#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4) 2560#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2575#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2) 2561#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
2562#define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
2576 2563
2577/* WaClearTdlStateAckDirtyBits */ 2564/* WaClearTdlStateAckDirtyBits */
2578#define GEN8_STATE_ACK _MMIO(0x20F0) 2565#define GEN8_STATE_ACK _MMIO(0x20F0)
@@ -3475,11 +3462,13 @@ enum i915_power_well_id {
3475/* 3462/*
3476 * Palette regs 3463 * Palette regs
3477 */ 3464 */
3478#define PALETTE_A_OFFSET 0xa000 3465#define _PALETTE_A 0xa000
3479#define PALETTE_B_OFFSET 0xa800 3466#define _PALETTE_B 0xa800
3480#define CHV_PALETTE_C_OFFSET 0xc000 3467#define _CHV_PALETTE_C 0xc000
3481#define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \ 3468#define PALETTE(pipe, i) _MMIO(dev_priv->info.display_mmio_offset + \
3482 dev_priv->info.display_mmio_offset + (i) * 4) 3469 _PICK((pipe), _PALETTE_A, \
3470 _PALETTE_B, _CHV_PALETTE_C) + \
3471 (i) * 4)
3483 3472
3484/* MCH MMIO space */ 3473/* MCH MMIO space */
3485 3474
@@ -4061,15 +4050,27 @@ enum {
4061#define _VSYNCSHIFT_B 0x61028 4050#define _VSYNCSHIFT_B 0x61028
4062#define _PIPE_MULT_B 0x6102c 4051#define _PIPE_MULT_B 0x6102c
4063 4052
4053/* DSI 0 timing regs */
4054#define _HTOTAL_DSI0 0x6b000
4055#define _HSYNC_DSI0 0x6b008
4056#define _VTOTAL_DSI0 0x6b00c
4057#define _VSYNC_DSI0 0x6b014
4058#define _VSYNCSHIFT_DSI0 0x6b028
4059
4060/* DSI 1 timing regs */
4061#define _HTOTAL_DSI1 0x6b800
4062#define _HSYNC_DSI1 0x6b808
4063#define _VTOTAL_DSI1 0x6b80c
4064#define _VSYNC_DSI1 0x6b814
4065#define _VSYNCSHIFT_DSI1 0x6b828
4066
4064#define TRANSCODER_A_OFFSET 0x60000 4067#define TRANSCODER_A_OFFSET 0x60000
4065#define TRANSCODER_B_OFFSET 0x61000 4068#define TRANSCODER_B_OFFSET 0x61000
4066#define TRANSCODER_C_OFFSET 0x62000 4069#define TRANSCODER_C_OFFSET 0x62000
4067#define CHV_TRANSCODER_C_OFFSET 0x63000 4070#define CHV_TRANSCODER_C_OFFSET 0x63000
4068#define TRANSCODER_EDP_OFFSET 0x6f000 4071#define TRANSCODER_EDP_OFFSET 0x6f000
4069 4072#define TRANSCODER_DSI0_OFFSET 0x6b000
4070#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \ 4073#define TRANSCODER_DSI1_OFFSET 0x6b800
4071 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
4072 dev_priv->info.display_mmio_offset)
4073 4074
4074#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) 4075#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
4075#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) 4076#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
@@ -4149,9 +4150,13 @@ enum {
4149/* Bspec claims those aren't shifted but stay at 0x64800 */ 4150/* Bspec claims those aren't shifted but stay at 0x64800 */
4150#define EDP_PSR_IMR _MMIO(0x64834) 4151#define EDP_PSR_IMR _MMIO(0x64834)
4151#define EDP_PSR_IIR _MMIO(0x64838) 4152#define EDP_PSR_IIR _MMIO(0x64838)
4152#define EDP_PSR_ERROR(trans) (1 << (((trans) * 8 + 10) & 31)) 4153#define EDP_PSR_ERROR(shift) (1 << ((shift) + 2))
4153#define EDP_PSR_POST_EXIT(trans) (1 << (((trans) * 8 + 9) & 31)) 4154#define EDP_PSR_POST_EXIT(shift) (1 << ((shift) + 1))
4154#define EDP_PSR_PRE_ENTRY(trans) (1 << (((trans) * 8 + 8) & 31)) 4155#define EDP_PSR_PRE_ENTRY(shift) (1 << (shift))
4156#define EDP_PSR_TRANSCODER_C_SHIFT 24
4157#define EDP_PSR_TRANSCODER_B_SHIFT 16
4158#define EDP_PSR_TRANSCODER_A_SHIFT 8
4159#define EDP_PSR_TRANSCODER_EDP_SHIFT 0
4155 4160
4156#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10) 4161#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
4157#define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26) 4162#define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26)
@@ -4195,7 +4200,7 @@ enum {
4195#define EDP_PSR_DEBUG_MASK_LPSP (1 << 27) 4200#define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
4196#define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26) 4201#define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
4197#define EDP_PSR_DEBUG_MASK_HPD (1 << 25) 4202#define EDP_PSR_DEBUG_MASK_HPD (1 << 25)
4198#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) 4203#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */
4199#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ 4204#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
4200 4205
4201#define EDP_PSR2_CTL _MMIO(0x6f900) 4206#define EDP_PSR2_CTL _MMIO(0x6f900)
@@ -4232,7 +4237,7 @@ enum {
4232#define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9) 4237#define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9)
4233#define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8) 4238#define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8)
4234#define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6) 4239#define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6)
4235#define PSR_EVENT_REGISTER_UPDATE (1 << 5) 4240#define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */
4236#define PSR_EVENT_HDCP_ENABLE (1 << 4) 4241#define PSR_EVENT_HDCP_ENABLE (1 << 4)
4237#define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3) 4242#define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3)
4238#define PSR_EVENT_VBI_ENABLE (1 << 2) 4243#define PSR_EVENT_VBI_ENABLE (1 << 2)
@@ -4584,6 +4589,15 @@ enum {
4584#define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 4589#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
4585#define VIDEO_DIP_FREQ_MASK (3 << 16) 4590#define VIDEO_DIP_FREQ_MASK (3 << 16)
4586/* HSW and later: */ 4591/* HSW and later: */
4592#define DRM_DIP_ENABLE (1 << 28)
4593#define PSR_VSC_BIT_7_SET (1 << 27)
4594#define VSC_SELECT_MASK (0x3 << 25)
4595#define VSC_SELECT_SHIFT 25
4596#define VSC_DIP_HW_HEA_DATA (0 << 25)
4597#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
4598#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
4599#define VSC_DIP_SW_HEA_DATA (3 << 25)
4600#define VDIP_ENABLE_PPS (1 << 24)
4587#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 4601#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
4588#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 4602#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
4589#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 4603#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
@@ -4591,16 +4605,6 @@ enum {
4591#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 4605#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
4592#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 4606#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
4593 4607
4594#define DRM_DIP_ENABLE (1 << 28)
4595#define PSR_VSC_BIT_7_SET (1 << 27)
4596#define VSC_SELECT_MASK (0x3 << 26)
4597#define VSC_SELECT_SHIFT 26
4598#define VSC_DIP_HW_HEA_DATA (0 << 26)
4599#define VSC_DIP_HW_HEA_SW_DATA (1 << 26)
4600#define VSC_DIP_HW_DATA_SW_HEA (2 << 26)
4601#define VSC_DIP_SW_HEA_DATA (3 << 26)
4602#define VDIP_ENABLE_PPS (1 << 24)
4603
4604/* Panel power sequencing */ 4608/* Panel power sequencing */
4605#define PPS_BASE 0x61200 4609#define PPS_BASE 0x61200
4606#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) 4610#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
@@ -5636,9 +5640,9 @@ enum {
5636 */ 5640 */
5637#define PIPE_EDP_OFFSET 0x7f000 5641#define PIPE_EDP_OFFSET 0x7f000
5638 5642
5639#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \ 5643/* ICL DSI 0 and 1 */
5640 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ 5644#define PIPE_DSI0_OFFSET 0x7b000
5641 dev_priv->info.display_mmio_offset) 5645#define PIPE_DSI1_OFFSET 0x7b800
5642 5646
5643#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) 5647#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
5644#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) 5648#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
@@ -6087,10 +6091,6 @@ enum {
6087#define _CURBBASE_IVB 0x71084 6091#define _CURBBASE_IVB 0x71084
6088#define _CURBPOS_IVB 0x71088 6092#define _CURBPOS_IVB 0x71088
6089 6093
6090#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
6091 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
6092 dev_priv->info.display_mmio_offset)
6093
6094#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) 6094#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
6095#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) 6095#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
6096#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) 6096#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
@@ -6224,6 +6224,10 @@ enum {
6224#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4) 6224#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
6225#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC) 6225#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
6226 6226
6227/* ICL DSI 0 and 1 */
6228#define _PIPEDSI0CONF 0x7b008
6229#define _PIPEDSI1CONF 0x7b808
6230
6227/* Sprite A control */ 6231/* Sprite A control */
6228#define _DVSACNTR 0x72180 6232#define _DVSACNTR 0x72180
6229#define DVS_ENABLE (1 << 31) 6233#define DVS_ENABLE (1 << 31)
@@ -6511,6 +6515,7 @@ enum {
6511#define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21) 6515#define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
6512#define PLANE_CTL_ORDER_BGRX (0 << 20) 6516#define PLANE_CTL_ORDER_BGRX (0 << 20)
6513#define PLANE_CTL_ORDER_RGBX (1 << 20) 6517#define PLANE_CTL_ORDER_RGBX (1 << 20)
6518#define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
6514#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) 6519#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
6515#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16) 6520#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
6516#define PLANE_CTL_YUV422_YUYV (0 << 16) 6521#define PLANE_CTL_YUV422_YUYV (0 << 16)
@@ -6554,17 +6559,33 @@ enum {
6554#define _PLANE_KEYVAL_2_A 0x70294 6559#define _PLANE_KEYVAL_2_A 0x70294
6555#define _PLANE_KEYMSK_1_A 0x70198 6560#define _PLANE_KEYMSK_1_A 0x70198
6556#define _PLANE_KEYMSK_2_A 0x70298 6561#define _PLANE_KEYMSK_2_A 0x70298
6562#define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31)
6557#define _PLANE_KEYMAX_1_A 0x701a0 6563#define _PLANE_KEYMAX_1_A 0x701a0
6558#define _PLANE_KEYMAX_2_A 0x702a0 6564#define _PLANE_KEYMAX_2_A 0x702a0
6565#define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
6559#define _PLANE_AUX_DIST_1_A 0x701c0 6566#define _PLANE_AUX_DIST_1_A 0x701c0
6560#define _PLANE_AUX_DIST_2_A 0x702c0 6567#define _PLANE_AUX_DIST_2_A 0x702c0
6561#define _PLANE_AUX_OFFSET_1_A 0x701c4 6568#define _PLANE_AUX_OFFSET_1_A 0x701c4
6562#define _PLANE_AUX_OFFSET_2_A 0x702c4 6569#define _PLANE_AUX_OFFSET_2_A 0x702c4
6570#define _PLANE_CUS_CTL_1_A 0x701c8
6571#define _PLANE_CUS_CTL_2_A 0x702c8
6572#define PLANE_CUS_ENABLE (1 << 31)
6573#define PLANE_CUS_PLANE_6 (0 << 30)
6574#define PLANE_CUS_PLANE_7 (1 << 30)
6575#define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
6576#define PLANE_CUS_HPHASE_0 (0 << 16)
6577#define PLANE_CUS_HPHASE_0_25 (1 << 16)
6578#define PLANE_CUS_HPHASE_0_5 (2 << 16)
6579#define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15)
6580#define PLANE_CUS_VPHASE_0 (0 << 12)
6581#define PLANE_CUS_VPHASE_0_25 (1 << 12)
6582#define PLANE_CUS_VPHASE_0_5 (2 << 12)
6563#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ 6583#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
6564#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ 6584#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
6565#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ 6585#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
6566#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */ 6586#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
6567#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28) 6587#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6588#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
6568#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */ 6589#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
6569#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17) 6590#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
6570#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17) 6591#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
@@ -6581,6 +6602,55 @@ enum {
6581#define _PLANE_NV12_BUF_CFG_1_A 0x70278 6602#define _PLANE_NV12_BUF_CFG_1_A 0x70278
6582#define _PLANE_NV12_BUF_CFG_2_A 0x70378 6603#define _PLANE_NV12_BUF_CFG_2_A 0x70378
6583 6604
6605/* Input CSC Register Definitions */
6606#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
6607#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
6608
6609#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
6610#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
6611
6612#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
6613 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
6614 _PLANE_INPUT_CSC_RY_GY_1_B)
6615#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
6616 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
6617 _PLANE_INPUT_CSC_RY_GY_2_B)
6618
6619#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
6620 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
6621 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
6622
6623#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
6624#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
6625
6626#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
6627#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
6628
6629#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
6630 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
6631 _PLANE_INPUT_CSC_PREOFF_HI_1_B)
6632#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
6633 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
6634 _PLANE_INPUT_CSC_PREOFF_HI_2_B)
6635#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
6636 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
6637 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
6638
6639#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
6640#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
6641
6642#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
6643#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
6644
6645#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
6646 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
6647 _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
6648#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
6649 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
6650 _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
6651#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
6652 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
6653 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
6584 6654
6585#define _PLANE_CTL_1_B 0x71180 6655#define _PLANE_CTL_1_B 0x71180
6586#define _PLANE_CTL_2_B 0x71280 6656#define _PLANE_CTL_2_B 0x71280
@@ -6697,6 +6767,15 @@ enum {
6697#define PLANE_AUX_OFFSET(pipe, plane) \ 6767#define PLANE_AUX_OFFSET(pipe, plane) \
6698 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) 6768 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
6699 6769
6770#define _PLANE_CUS_CTL_1_B 0x711c8
6771#define _PLANE_CUS_CTL_2_B 0x712c8
6772#define _PLANE_CUS_CTL_1(pipe) \
6773 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
6774#define _PLANE_CUS_CTL_2(pipe) \
6775 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
6776#define PLANE_CUS_CTL(pipe, plane) \
6777 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
6778
6700#define _PLANE_COLOR_CTL_1_B 0x711CC 6779#define _PLANE_COLOR_CTL_1_B 0x711CC
6701#define _PLANE_COLOR_CTL_2_B 0x712CC 6780#define _PLANE_COLOR_CTL_2_B 0x712CC
6702#define _PLANE_COLOR_CTL_3_B 0x713CC 6781#define _PLANE_COLOR_CTL_3_B 0x713CC
@@ -6850,11 +6929,12 @@ enum {
6850#define _PS_2B_CTRL 0x68A80 6929#define _PS_2B_CTRL 0x68A80
6851#define _PS_1C_CTRL 0x69180 6930#define _PS_1C_CTRL 0x69180
6852#define PS_SCALER_EN (1 << 31) 6931#define PS_SCALER_EN (1 << 31)
6853#define PS_SCALER_MODE_MASK (3 << 28) 6932#define SKL_PS_SCALER_MODE_MASK (3 << 28)
6854#define PS_SCALER_MODE_DYN (0 << 28) 6933#define SKL_PS_SCALER_MODE_DYN (0 << 28)
6855#define PS_SCALER_MODE_HQ (1 << 28) 6934#define SKL_PS_SCALER_MODE_HQ (1 << 28)
6856#define SKL_PS_SCALER_MODE_NV12 (2 << 28) 6935#define SKL_PS_SCALER_MODE_NV12 (2 << 28)
6857#define PS_SCALER_MODE_PLANAR (1 << 29) 6936#define PS_SCALER_MODE_PLANAR (1 << 29)
6937#define PS_SCALER_MODE_NORMAL (0 << 29)
6858#define PS_PLANE_SEL_MASK (7 << 25) 6938#define PS_PLANE_SEL_MASK (7 << 25)
6859#define PS_PLANE_SEL(plane) (((plane) + 1) << 25) 6939#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
6860#define PS_FILTER_MASK (3 << 23) 6940#define PS_FILTER_MASK (3 << 23)
@@ -6871,6 +6951,8 @@ enum {
6871#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) 6951#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
6872#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) 6952#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
6873#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) 6953#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
6954#define PS_PLANE_Y_SEL_MASK (7 << 5)
6955#define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
6874 6956
6875#define _PS_PWR_GATE_1A 0x68160 6957#define _PS_PWR_GATE_1A 0x68160
6876#define _PS_PWR_GATE_2A 0x68260 6958#define _PS_PWR_GATE_2A 0x68260
@@ -7317,9 +7399,10 @@ enum {
7317#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 7399#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
7318#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 7400#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
7319 7401
7320#define CHICKEN_TRANS_A 0x420c0 7402#define CHICKEN_TRANS_A _MMIO(0x420c0)
7321#define CHICKEN_TRANS_B 0x420c4 7403#define CHICKEN_TRANS_B _MMIO(0x420c4)
7322#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B) 7404#define CHICKEN_TRANS_C _MMIO(0x420c8)
7405#define CHICKEN_TRANS_EDP _MMIO(0x420cc)
7323#define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */ 7406#define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
7324#define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19) 7407#define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
7325#define DDI_TRAINING_OVERRIDE_VALUE (1 << 18) 7408#define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
@@ -7409,6 +7492,10 @@ enum {
7409#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) 7492#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
7410#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11) 7493#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
7411 7494
7495#define GEN7_SARCHKMD _MMIO(0xB000)
7496#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
7497#define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30)
7498
7412#define GEN7_L3SQCREG1 _MMIO(0xB010) 7499#define GEN7_L3SQCREG1 _MMIO(0xB010)
7413#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 7500#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
7414 7501
@@ -7824,8 +7911,7 @@ enum {
7824#define CNP_RAWCLK_DIV_MASK (0x3ff << 16) 7911#define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
7825#define CNP_RAWCLK_DIV(div) ((div) << 16) 7912#define CNP_RAWCLK_DIV(div) ((div) << 16)
7826#define CNP_RAWCLK_FRAC_MASK (0xf << 26) 7913#define CNP_RAWCLK_FRAC_MASK (0xf << 26)
7827#define CNP_RAWCLK_FRAC(frac) ((frac) << 26) 7914#define CNP_RAWCLK_DEN(den) ((den) << 26)
7828#define ICP_RAWCLK_DEN(den) ((den) << 26)
7829#define ICP_RAWCLK_NUM(num) ((num) << 11) 7915#define ICP_RAWCLK_NUM(num) ((num) << 11)
7830 7916
7831#define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 7917#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
@@ -8625,8 +8711,7 @@ enum {
8625#define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9) 8711#define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9)
8626#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7) 8712#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
8627 8713
8628#define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080) 8714#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
8629#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
8630 8715
8631/* IVYBRIDGE DPF */ 8716/* IVYBRIDGE DPF */
8632#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 8717#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
@@ -8927,6 +9012,15 @@ enum skl_power_gate {
8927#define CNL_AUX_ANAOVRD1_ENABLE (1 << 16) 9012#define CNL_AUX_ANAOVRD1_ENABLE (1 << 16)
8928#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23) 9013#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23)
8929 9014
9015#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
9016#define _ICL_AUX_ANAOVRD1_A 0x162398
9017#define _ICL_AUX_ANAOVRD1_B 0x6C398
9018#define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
9019 _ICL_AUX_ANAOVRD1_A, \
9020 _ICL_AUX_ANAOVRD1_B))
9021#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
9022#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
9023
8930/* HDCP Key Registers */ 9024/* HDCP Key Registers */
8931#define HDCP_KEY_CONF _MMIO(0x66c00) 9025#define HDCP_KEY_CONF _MMIO(0x66c00)
8932#define HDCP_AKSV_SEND_TRIGGER BIT(31) 9026#define HDCP_AKSV_SEND_TRIGGER BIT(31)
@@ -9009,11 +9103,45 @@ enum skl_power_gate {
9009#define HDCP_STATUS_CIPHER BIT(16) 9103#define HDCP_STATUS_CIPHER BIT(16)
9010#define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff) 9104#define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff)
9011 9105
9106/* HDCP2.2 Registers */
9107#define _PORTA_HDCP2_BASE 0x66800
9108#define _PORTB_HDCP2_BASE 0x66500
9109#define _PORTC_HDCP2_BASE 0x66600
9110#define _PORTD_HDCP2_BASE 0x66700
9111#define _PORTE_HDCP2_BASE 0x66A00
9112#define _PORTF_HDCP2_BASE 0x66900
9113#define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \
9114 _PORTA_HDCP2_BASE, \
9115 _PORTB_HDCP2_BASE, \
9116 _PORTC_HDCP2_BASE, \
9117 _PORTD_HDCP2_BASE, \
9118 _PORTE_HDCP2_BASE, \
9119 _PORTF_HDCP2_BASE) + (x))
9120
9121#define HDCP2_AUTH_DDI(port) _PORT_HDCP2_BASE(port, 0x98)
9122#define AUTH_LINK_AUTHENTICATED BIT(31)
9123#define AUTH_LINK_TYPE BIT(30)
9124#define AUTH_FORCE_CLR_INPUTCTR BIT(19)
9125#define AUTH_CLR_KEYS BIT(18)
9126
9127#define HDCP2_CTL_DDI(port) _PORT_HDCP2_BASE(port, 0xB0)
9128#define CTL_LINK_ENCRYPTION_REQ BIT(31)
9129
9130#define HDCP2_STATUS_DDI(port) _PORT_HDCP2_BASE(port, 0xB4)
9131#define STREAM_ENCRYPTION_STATUS_A BIT(31)
9132#define STREAM_ENCRYPTION_STATUS_B BIT(30)
9133#define STREAM_ENCRYPTION_STATUS_C BIT(29)
9134#define LINK_TYPE_STATUS BIT(22)
9135#define LINK_AUTH_STATUS BIT(21)
9136#define LINK_ENCRYPTION_STATUS BIT(20)
9137
9012/* Per-pipe DDI Function Control */ 9138/* Per-pipe DDI Function Control */
9013#define _TRANS_DDI_FUNC_CTL_A 0x60400 9139#define _TRANS_DDI_FUNC_CTL_A 0x60400
9014#define _TRANS_DDI_FUNC_CTL_B 0x61400 9140#define _TRANS_DDI_FUNC_CTL_B 0x61400
9015#define _TRANS_DDI_FUNC_CTL_C 0x62400 9141#define _TRANS_DDI_FUNC_CTL_C 0x62400
9016#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 9142#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
9143#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
9144#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
9017#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) 9145#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
9018 9146
9019#define TRANS_DDI_FUNC_ENABLE (1 << 31) 9147#define TRANS_DDI_FUNC_ENABLE (1 << 31)
@@ -9051,6 +9179,19 @@ enum skl_power_gate {
9051 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ 9179 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
9052 | TRANS_DDI_HDMI_SCRAMBLING) 9180 | TRANS_DDI_HDMI_SCRAMBLING)
9053 9181
9182#define _TRANS_DDI_FUNC_CTL2_A 0x60404
9183#define _TRANS_DDI_FUNC_CTL2_B 0x61404
9184#define _TRANS_DDI_FUNC_CTL2_C 0x62404
9185#define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
9186#define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
9187#define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
9188#define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, \
9189 _TRANS_DDI_FUNC_CTL2_A)
9190#define PORT_SYNC_MODE_ENABLE (1 << 4)
9191#define PORT_SYNC_MODE_MASTER_SELECT(x) ((x) < 0)
9192#define PORT_SYNC_MODE_MASTER_SELECT_MASK (0x7 << 0)
9193#define PORT_SYNC_MODE_MASTER_SELECT_SHIFT 0
9194
9054/* DisplayPort Transport Control */ 9195/* DisplayPort Transport Control */
9055#define _DP_TP_CTL_A 0x64040 9196#define _DP_TP_CTL_A 0x64040
9056#define _DP_TP_CTL_B 0x64140 9197#define _DP_TP_CTL_B 0x64140
@@ -9222,6 +9363,8 @@ enum skl_power_gate {
9222#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) 9363#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
9223 9364
9224#define TRANS_MSA_SYNC_CLK (1 << 0) 9365#define TRANS_MSA_SYNC_CLK (1 << 0)
9366#define TRANS_MSA_SAMPLING_444 (2 << 1)
9367#define TRANS_MSA_CLRSP_YCBCR (2 << 3)
9225#define TRANS_MSA_6_BPC (0 << 5) 9368#define TRANS_MSA_6_BPC (0 << 5)
9226#define TRANS_MSA_8_BPC (1 << 5) 9369#define TRANS_MSA_8_BPC (1 << 5)
9227#define TRANS_MSA_10_BPC (2 << 5) 9370#define TRANS_MSA_10_BPC (2 << 5)
@@ -9789,6 +9932,10 @@ enum skl_power_gate {
9789#define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ 9932#define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
9790#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) 9933#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
9791 9934
9935/* Gen11 DSI */
9936#define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
9937 dsi0, dsi1)
9938
9792#define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004) 9939#define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
9793#define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF 9940#define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF
9794#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008) 9941#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
@@ -9952,6 +10099,39 @@ enum skl_power_gate {
9952 _ICL_DSI_IO_MODECTL_1) 10099 _ICL_DSI_IO_MODECTL_1)
9953#define COMBO_PHY_MODE_DSI (1 << 0) 10100#define COMBO_PHY_MODE_DSI (1 << 0)
9954 10101
10102/* Display Stream Splitter Control */
10103#define DSS_CTL1 _MMIO(0x67400)
10104#define SPLITTER_ENABLE (1 << 31)
10105#define JOINER_ENABLE (1 << 30)
10106#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
10107#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
10108#define OVERLAP_PIXELS_MASK (0xf << 16)
10109#define OVERLAP_PIXELS(pixels) ((pixels) << 16)
10110#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
10111#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
10112#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
10113
10114#define DSS_CTL2 _MMIO(0x67404)
10115#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
10116#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
10117#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
10118#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
10119
10120#define _ICL_PIPE_DSS_CTL1_PB 0x78200
10121#define _ICL_PIPE_DSS_CTL1_PC 0x78400
10122#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10123 _ICL_PIPE_DSS_CTL1_PB, \
10124 _ICL_PIPE_DSS_CTL1_PC)
10125#define BIG_JOINER_ENABLE (1 << 29)
10126#define MASTER_BIG_JOINER_ENABLE (1 << 28)
10127#define VGA_CENTERING_ENABLE (1 << 27)
10128
10129#define _ICL_PIPE_DSS_CTL2_PB 0x78204
10130#define _ICL_PIPE_DSS_CTL2_PC 0x78404
10131#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10132 _ICL_PIPE_DSS_CTL2_PB, \
10133 _ICL_PIPE_DSS_CTL2_PC)
10134
9955#define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) 10135#define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
9956#define STAP_SELECT (1 << 0) 10136#define STAP_SELECT (1 << 0)
9957 10137
@@ -10288,6 +10468,235 @@ enum skl_power_gate {
10288 _ICL_DSI_T_INIT_MASTER_0,\ 10468 _ICL_DSI_T_INIT_MASTER_0,\
10289 _ICL_DSI_T_INIT_MASTER_1) 10469 _ICL_DSI_T_INIT_MASTER_1)
10290 10470
10471#define _DPHY_CLK_TIMING_PARAM_0 0x162180
10472#define _DPHY_CLK_TIMING_PARAM_1 0x6c180
10473#define DPHY_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \
10474 _DPHY_CLK_TIMING_PARAM_0,\
10475 _DPHY_CLK_TIMING_PARAM_1)
10476#define _DSI_CLK_TIMING_PARAM_0 0x6b080
10477#define _DSI_CLK_TIMING_PARAM_1 0x6b880
10478#define DSI_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \
10479 _DSI_CLK_TIMING_PARAM_0,\
10480 _DSI_CLK_TIMING_PARAM_1)
10481#define CLK_PREPARE_OVERRIDE (1 << 31)
10482#define CLK_PREPARE(x) ((x) << 28)
10483#define CLK_PREPARE_MASK (0x7 << 28)
10484#define CLK_PREPARE_SHIFT 28
10485#define CLK_ZERO_OVERRIDE (1 << 27)
10486#define CLK_ZERO(x) ((x) << 20)
10487#define CLK_ZERO_MASK (0xf << 20)
10488#define CLK_ZERO_SHIFT 20
10489#define CLK_PRE_OVERRIDE (1 << 19)
10490#define CLK_PRE(x) ((x) << 16)
10491#define CLK_PRE_MASK (0x3 << 16)
10492#define CLK_PRE_SHIFT 16
10493#define CLK_POST_OVERRIDE (1 << 15)
10494#define CLK_POST(x) ((x) << 8)
10495#define CLK_POST_MASK (0x7 << 8)
10496#define CLK_POST_SHIFT 8
10497#define CLK_TRAIL_OVERRIDE (1 << 7)
10498#define CLK_TRAIL(x) ((x) << 0)
10499#define CLK_TRAIL_MASK (0xf << 0)
10500#define CLK_TRAIL_SHIFT 0
10501
10502#define _DPHY_DATA_TIMING_PARAM_0 0x162184
10503#define _DPHY_DATA_TIMING_PARAM_1 0x6c184
10504#define DPHY_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \
10505 _DPHY_DATA_TIMING_PARAM_0,\
10506 _DPHY_DATA_TIMING_PARAM_1)
10507#define _DSI_DATA_TIMING_PARAM_0 0x6B084
10508#define _DSI_DATA_TIMING_PARAM_1 0x6B884
10509#define DSI_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \
10510 _DSI_DATA_TIMING_PARAM_0,\
10511 _DSI_DATA_TIMING_PARAM_1)
10512#define HS_PREPARE_OVERRIDE (1 << 31)
10513#define HS_PREPARE(x) ((x) << 24)
10514#define HS_PREPARE_MASK (0x7 << 24)
10515#define HS_PREPARE_SHIFT 24
10516#define HS_ZERO_OVERRIDE (1 << 23)
10517#define HS_ZERO(x) ((x) << 16)
10518#define HS_ZERO_MASK (0xf << 16)
10519#define HS_ZERO_SHIFT 16
10520#define HS_TRAIL_OVERRIDE (1 << 15)
10521#define HS_TRAIL(x) ((x) << 8)
10522#define HS_TRAIL_MASK (0x7 << 8)
10523#define HS_TRAIL_SHIFT 8
10524#define HS_EXIT_OVERRIDE (1 << 7)
10525#define HS_EXIT(x) ((x) << 0)
10526#define HS_EXIT_MASK (0x7 << 0)
10527#define HS_EXIT_SHIFT 0
10528
10529#define _DPHY_TA_TIMING_PARAM_0 0x162188
10530#define _DPHY_TA_TIMING_PARAM_1 0x6c188
10531#define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
10532 _DPHY_TA_TIMING_PARAM_0,\
10533 _DPHY_TA_TIMING_PARAM_1)
10534#define _DSI_TA_TIMING_PARAM_0 0x6b098
10535#define _DSI_TA_TIMING_PARAM_1 0x6b898
10536#define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
10537 _DSI_TA_TIMING_PARAM_0,\
10538 _DSI_TA_TIMING_PARAM_1)
10539#define TA_SURE_OVERRIDE (1 << 31)
10540#define TA_SURE(x) ((x) << 16)
10541#define TA_SURE_MASK (0x1f << 16)
10542#define TA_SURE_SHIFT 16
10543#define TA_GO_OVERRIDE (1 << 15)
10544#define TA_GO(x) ((x) << 8)
10545#define TA_GO_MASK (0xf << 8)
10546#define TA_GO_SHIFT 8
10547#define TA_GET_OVERRIDE (1 << 7)
10548#define TA_GET(x) ((x) << 0)
10549#define TA_GET_MASK (0xf << 0)
10550#define TA_GET_SHIFT 0
10551
10552/* DSI transcoder configuration */
10553#define _DSI_TRANS_FUNC_CONF_0 0x6b030
10554#define _DSI_TRANS_FUNC_CONF_1 0x6b830
10555#define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \
10556 _DSI_TRANS_FUNC_CONF_0,\
10557 _DSI_TRANS_FUNC_CONF_1)
10558#define OP_MODE_MASK (0x3 << 28)
10559#define OP_MODE_SHIFT 28
10560#define CMD_MODE_NO_GATE (0x0 << 28)
10561#define CMD_MODE_TE_GATE (0x1 << 28)
10562#define VIDEO_MODE_SYNC_EVENT (0x2 << 28)
10563#define VIDEO_MODE_SYNC_PULSE (0x3 << 28)
10564#define LINK_READY (1 << 20)
10565#define PIX_FMT_MASK (0x3 << 16)
10566#define PIX_FMT_SHIFT 16
10567#define PIX_FMT_RGB565 (0x0 << 16)
10568#define PIX_FMT_RGB666_PACKED (0x1 << 16)
10569#define PIX_FMT_RGB666_LOOSE (0x2 << 16)
10570#define PIX_FMT_RGB888 (0x3 << 16)
10571#define PIX_FMT_RGB101010 (0x4 << 16)
10572#define PIX_FMT_RGB121212 (0x5 << 16)
10573#define PIX_FMT_COMPRESSED (0x6 << 16)
10574#define BGR_TRANSMISSION (1 << 15)
10575#define PIX_VIRT_CHAN(x) ((x) << 12)
10576#define PIX_VIRT_CHAN_MASK (0x3 << 12)
10577#define PIX_VIRT_CHAN_SHIFT 12
10578#define PIX_BUF_THRESHOLD_MASK (0x3 << 10)
10579#define PIX_BUF_THRESHOLD_SHIFT 10
10580#define PIX_BUF_THRESHOLD_1_4 (0x0 << 10)
10581#define PIX_BUF_THRESHOLD_1_2 (0x1 << 10)
10582#define PIX_BUF_THRESHOLD_3_4 (0x2 << 10)
10583#define PIX_BUF_THRESHOLD_FULL (0x3 << 10)
10584#define CONTINUOUS_CLK_MASK (0x3 << 8)
10585#define CONTINUOUS_CLK_SHIFT 8
10586#define CLK_ENTER_LP_AFTER_DATA (0x0 << 8)
10587#define CLK_HS_OR_LP (0x2 << 8)
10588#define CLK_HS_CONTINUOUS (0x3 << 8)
10589#define LINK_CALIBRATION_MASK (0x3 << 4)
10590#define LINK_CALIBRATION_SHIFT 4
10591#define CALIBRATION_DISABLED (0x0 << 4)
10592#define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4)
10593#define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4)
10594#define S3D_ORIENTATION_LANDSCAPE (1 << 1)
10595#define EOTP_DISABLED (1 << 0)
10596
10597#define _DSI_CMD_RXCTL_0 0x6b0d4
10598#define _DSI_CMD_RXCTL_1 0x6b8d4
10599#define DSI_CMD_RXCTL(tc) _MMIO_DSI(tc, \
10600 _DSI_CMD_RXCTL_0,\
10601 _DSI_CMD_RXCTL_1)
10602#define READ_UNLOADS_DW (1 << 16)
10603#define RECEIVED_UNASSIGNED_TRIGGER (1 << 15)
10604#define RECEIVED_ACKNOWLEDGE_TRIGGER (1 << 14)
10605#define RECEIVED_TEAR_EFFECT_TRIGGER (1 << 13)
10606#define RECEIVED_RESET_TRIGGER (1 << 12)
10607#define RECEIVED_PAYLOAD_WAS_LOST (1 << 11)
10608#define RECEIVED_CRC_WAS_LOST (1 << 10)
10609#define NUMBER_RX_PLOAD_DW_MASK (0xff << 0)
10610#define NUMBER_RX_PLOAD_DW_SHIFT 0
10611
10612#define _DSI_CMD_TXCTL_0 0x6b0d0
10613#define _DSI_CMD_TXCTL_1 0x6b8d0
10614#define DSI_CMD_TXCTL(tc) _MMIO_DSI(tc, \
10615 _DSI_CMD_TXCTL_0,\
10616 _DSI_CMD_TXCTL_1)
10617#define KEEP_LINK_IN_HS (1 << 24)
10618#define FREE_HEADER_CREDIT_MASK (0x1f << 8)
10619#define FREE_HEADER_CREDIT_SHIFT 0x8
10620#define FREE_PLOAD_CREDIT_MASK (0xff << 0)
10621#define FREE_PLOAD_CREDIT_SHIFT 0
10622#define MAX_HEADER_CREDIT 0x10
10623#define MAX_PLOAD_CREDIT 0x40
10624
10625#define _DSI_CMD_TXHDR_0 0x6b100
10626#define _DSI_CMD_TXHDR_1 0x6b900
10627#define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \
10628 _DSI_CMD_TXHDR_0,\
10629 _DSI_CMD_TXHDR_1)
10630#define PAYLOAD_PRESENT (1 << 31)
10631#define LP_DATA_TRANSFER (1 << 30)
10632#define VBLANK_FENCE (1 << 29)
10633#define PARAM_WC_MASK (0xffff << 8)
10634#define PARAM_WC_LOWER_SHIFT 8
10635#define PARAM_WC_UPPER_SHIFT 16
10636#define VC_MASK (0x3 << 6)
10637#define VC_SHIFT 6
10638#define DT_MASK (0x3f << 0)
10639#define DT_SHIFT 0
10640
10641#define _DSI_CMD_TXPYLD_0 0x6b104
10642#define _DSI_CMD_TXPYLD_1 0x6b904
10643#define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \
10644 _DSI_CMD_TXPYLD_0,\
10645 _DSI_CMD_TXPYLD_1)
10646
10647#define _DSI_LP_MSG_0 0x6b0d8
10648#define _DSI_LP_MSG_1 0x6b8d8
10649#define DSI_LP_MSG(tc) _MMIO_DSI(tc, \
10650 _DSI_LP_MSG_0,\
10651 _DSI_LP_MSG_1)
10652#define LPTX_IN_PROGRESS (1 << 17)
10653#define LINK_IN_ULPS (1 << 16)
10654#define LINK_ULPS_TYPE_LP11 (1 << 8)
10655#define LINK_ENTER_ULPS (1 << 0)
10656
10657/* DSI timeout registers */
10658#define _DSI_HSTX_TO_0 0x6b044
10659#define _DSI_HSTX_TO_1 0x6b844
10660#define DSI_HSTX_TO(tc) _MMIO_DSI(tc, \
10661 _DSI_HSTX_TO_0,\
10662 _DSI_HSTX_TO_1)
10663#define HSTX_TIMEOUT_VALUE_MASK (0xffff << 16)
10664#define HSTX_TIMEOUT_VALUE_SHIFT 16
10665#define HSTX_TIMEOUT_VALUE(x) ((x) << 16)
10666#define HSTX_TIMED_OUT (1 << 0)
10667
10668#define _DSI_LPRX_HOST_TO_0 0x6b048
10669#define _DSI_LPRX_HOST_TO_1 0x6b848
10670#define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \
10671 _DSI_LPRX_HOST_TO_0,\
10672 _DSI_LPRX_HOST_TO_1)
10673#define LPRX_TIMED_OUT (1 << 16)
10674#define LPRX_TIMEOUT_VALUE_MASK (0xffff << 0)
10675#define LPRX_TIMEOUT_VALUE_SHIFT 0
10676#define LPRX_TIMEOUT_VALUE(x) ((x) << 0)
10677
10678#define _DSI_PWAIT_TO_0 0x6b040
10679#define _DSI_PWAIT_TO_1 0x6b840
10680#define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \
10681 _DSI_PWAIT_TO_0,\
10682 _DSI_PWAIT_TO_1)
10683#define PRESET_TIMEOUT_VALUE_MASK (0xffff << 16)
10684#define PRESET_TIMEOUT_VALUE_SHIFT 16
10685#define PRESET_TIMEOUT_VALUE(x) ((x) << 16)
10686#define PRESPONSE_TIMEOUT_VALUE_MASK (0xffff << 0)
10687#define PRESPONSE_TIMEOUT_VALUE_SHIFT 0
10688#define PRESPONSE_TIMEOUT_VALUE(x) ((x) << 0)
10689
10690#define _DSI_TA_TO_0 0x6b04c
10691#define _DSI_TA_TO_1 0x6b84c
10692#define DSI_TA_TO(tc) _MMIO_DSI(tc, \
10693 _DSI_TA_TO_0,\
10694 _DSI_TA_TO_1)
10695#define TA_TIMED_OUT (1 << 16)
10696#define TA_TIMEOUT_VALUE_MASK (0xffff << 0)
10697#define TA_TIMEOUT_VALUE_SHIFT 0
10698#define TA_TIMEOUT_VALUE(x) ((x) << 0)
10699
10291/* bits 31:0 */ 10700/* bits 31:0 */
10292#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) 10701#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
10293#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) 10702#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
@@ -10400,10 +10809,6 @@ enum skl_power_gate {
10400#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) 10809#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
10401#define READ_DATA_VALID(n) (1 << (n)) 10810#define READ_DATA_VALID(n) (1 << (n))
10402 10811
10403/* For UMS only (deprecated): */
10404#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
10405#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
10406
10407/* MOCS (Memory Object Control State) registers */ 10812/* MOCS (Memory Object Control State) registers */
10408#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */ 10813#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
10409 10814
@@ -10689,6 +11094,7 @@ enum skl_power_gate {
10689#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11094#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10690 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \ 11095 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
10691 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC) 11096 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
11097#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20)
10692#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) 11098#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
10693#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0) 11099#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
10694 11100
@@ -10743,17 +11149,17 @@ enum skl_power_gate {
10743 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \ 11149 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
10744 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC) 11150 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
10745 11151
10746#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0) 11152#define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE + 0x008A0)
10747#define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6)) 11153#define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
10748#define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5)) 11154#define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
10749#define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8) 11155#define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
10750#define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8)) 11156#define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
10751#define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8)) 11157#define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
10752 11158
10753#define PORT_TX_DFLEXDPPMS _MMIO(0x163890) 11159#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE + 0x00890)
10754#define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port)) 11160#define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
10755 11161
10756#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894) 11162#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + 0x00894)
10757#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port)) 11163#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
10758 11164
10759#endif /* _I915_REG_H_ */ 11165#endif /* _I915_REG_H_ */
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