1 files changed, 61 insertions, 22 deletions

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2e242270e270..d447d7d508f4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2887,21 +2887,39 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
         return ret;
 }
 
+static inline u32 gen8_master_intr_disable(void __iomem * const regs)
+{
+        raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
+
+        /*
+         * Now with master disabled, get a sample of level indications
+         * for this interrupt. Indications will be cleared on related acks.
+         * New indications can and will light up during processing,
+         * and will generate new interrupt after enabling master.
+         */
+        return raw_reg_read(regs, GEN8_MASTER_IRQ);
+}
+
+static inline void gen8_master_intr_enable(void __iomem * const regs)
+{
+        raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
+}
+
 static irqreturn_t gen8_irq_handler(int irq, void *arg)
 {
         struct drm_i915_private *dev_priv = to_i915(arg);
+        void __iomem * const regs = dev_priv->regs;
         u32 master_ctl;
         u32 gt_iir[4];
 
         if (!intel_irqs_enabled(dev_priv))
                 return IRQ_NONE;
 
-        master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
-        master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
-        if (!master_ctl)
+        master_ctl = gen8_master_intr_disable(regs);
+        if (!master_ctl) {
+                gen8_master_intr_enable(regs);
                 return IRQ_NONE;
-
-        I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
+        }
 
         /* Find, clear, then process each source of interrupt */
         gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
@@ -2913,7 +2931,7 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
                 enable_rpm_wakeref_asserts(dev_priv);
         }
 
-        I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
+        gen8_master_intr_enable(regs);
 
         gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
 
@@ -3111,6 +3129,24 @@ gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv, const u32 iir)
                 intel_opregion_asle_intr(dev_priv);
 }
 
+static inline u32 gen11_master_intr_disable(void __iomem * const regs)
+{
+        raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
+
+        /*
+         * Now with master disabled, get a sample of level indications
+         * for this interrupt. Indications will be cleared on related acks.
+         * New indications can and will light up during processing,
+         * and will generate new interrupt after enabling master.
+         */
+        return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
+}
+
+static inline void gen11_master_intr_enable(void __iomem * const regs)
+{
+        raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
+}
+
 static irqreturn_t gen11_irq_handler(int irq, void *arg)
 {
         struct drm_i915_private * const i915 = to_i915(arg);
@@ -3121,13 +3157,11 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
         if (!intel_irqs_enabled(i915))
                 return IRQ_NONE;
 
-        master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
-        master_ctl &= ~GEN11_MASTER_IRQ;
-        if (!master_ctl)
+        master_ctl = gen11_master_intr_disable(regs);
+        if (!master_ctl) {
+                gen11_master_intr_enable(regs);
                 return IRQ_NONE;
-
-        /* Disable interrupts. */
-        raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
+        }
 
         /* Find, clear, then process each source of interrupt. */
         gen11_gt_irq_handler(i915, master_ctl);
@@ -3147,8 +3181,7 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
 
         gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
 
-        /* Acknowledge and enable interrupts. */
-        raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
+        gen11_master_intr_enable(regs);
 
         gen11_gu_misc_irq_handler(i915, gu_misc_iir);
 
@@ -3598,8 +3631,7 @@ static void gen8_irq_reset(struct drm_device *dev)
         struct drm_i915_private *dev_priv = to_i915(dev);
         int pipe;
 
-        I915_WRITE(GEN8_MASTER_IRQ, 0);
-        POSTING_READ(GEN8_MASTER_IRQ);
+        gen8_master_intr_disable(dev_priv->regs);
 
         gen8_gt_irq_reset(dev_priv);
 
@@ -3641,13 +3673,15 @@ static void gen11_irq_reset(struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
         int pipe;
 
-        I915_WRITE(GEN11_GFX_MSTR_IRQ, 0);
-        POSTING_READ(GEN11_GFX_MSTR_IRQ);
+        gen11_master_intr_disable(dev_priv->regs);
 
         gen11_gt_irq_reset(dev_priv);
 
         I915_WRITE(GEN11_DISPLAY_INT_CTL, 0);
 
+        I915_WRITE(EDP_PSR_IMR, 0xffffffff);
+        I915_WRITE(EDP_PSR_IIR, 0xffffffff);
+
         for_each_pipe(dev_priv, pipe)
                 if (intel_display_power_is_enabled(dev_priv,
                                                    POWER_DOMAIN_PIPE(pipe)))
@@ -4244,8 +4278,7 @@ static int gen8_irq_postinstall(struct drm_device *dev)
         if (HAS_PCH_SPLIT(dev_priv))
                 ibx_irq_postinstall(dev);
 
-        I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
-        POSTING_READ(GEN8_MASTER_IRQ);
+        gen8_master_intr_enable(dev_priv->regs);
 
         return 0;
 }
@@ -4307,8 +4340,7 @@ static int gen11_irq_postinstall(struct drm_device *dev)
 
         I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
 
-        I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
-        POSTING_READ(GEN11_GFX_MSTR_IRQ);
+        gen11_master_intr_enable(dev_priv->regs);
 
         return 0;
 }
@@ -4834,6 +4866,13 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
                 dev_priv->display_irqs_enabled = false;
 
         dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
+        /* If we have MST support, we want to avoid doing short HPD IRQ storm
+         * detection, as short HPD storms will occur as a natural part of
+         * sideband messaging with MST.
+         * On older platforms however, IRQ storms can occur with both long and
+         * short pulses, as seen on some G4x systems.
+         */
+        dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
 
         dev->driver->get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos;
         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;