1 files changed, 43 insertions, 19 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 54b5d4c582b6..36bb4927484a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -67,7 +67,6 @@
 #include "i915_gem_fence_reg.h"
 #include "i915_gem_object.h"
 #include "i915_gem_gtt.h"
-#include "i915_gem_render_state.h"
 #include "i915_gem_request.h"
 #include "i915_gem_timeline.h"
 
@@ -80,8 +79,8 @@
 
 #define DRIVER_NAME             "i915"
 #define DRIVER_DESC             "Intel Graphics"
-#define DRIVER_DATE             "20171023"
-#define DRIVER_TIMESTAMP        1508748913
+#define DRIVER_DATE             "20171117"
+#define DRIVER_TIMESTAMP        1510958822
 
 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
  * WARN_ON()) for hw state sanity checks to check for unexpected conditions
@@ -726,10 +725,12 @@ struct drm_i915_display_funcs {
         void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
                              struct drm_atomic_state *old_state);
         void (*update_crtcs)(struct drm_atomic_state *state);
-        void (*audio_codec_enable)(struct drm_connector *connector,
-                                   struct intel_encoder *encoder,
-                                   const struct drm_display_mode *adjusted_mode);
-        void (*audio_codec_disable)(struct intel_encoder *encoder);
+        void (*audio_codec_enable)(struct intel_encoder *encoder,
+                                   const struct intel_crtc_state *crtc_state,
+                                   const struct drm_connector_state *conn_state);
+        void (*audio_codec_disable)(struct intel_encoder *encoder,
+                                    const struct intel_crtc_state *old_crtc_state,
+                                    const struct drm_connector_state *old_conn_state);
         void (*fdi_link_train)(struct intel_crtc *crtc,
                                const struct intel_crtc_state *crtc_state);
         void (*init_clock_gating)(struct drm_i915_private *dev_priv);
@@ -884,6 +885,8 @@ struct intel_device_info {
         /* Slice/subslice/EU info */
         struct sseu_dev_info sseu;
 
+        u32 cs_timestamp_frequency_khz;
+
         struct color_luts {
                 u16 degamma_lut_size;
                 u16 gamma_lut_size;
@@ -911,6 +914,12 @@ struct i915_gpu_state {
         struct intel_device_info device_info;
         struct i915_params params;
 
+        struct i915_error_uc {
+                struct intel_uc_fw guc_fw;
+                struct intel_uc_fw huc_fw;
+                struct drm_i915_error_object *guc_log;
+        } uc;
+
         /* Generic register state */
         u32 eir;
         u32 pgtbl_er;
@@ -934,7 +943,6 @@ struct i915_gpu_state {
         struct intel_overlay_error_state *overlay;
         struct intel_display_error_state *display;
         struct drm_i915_error_object *semaphore;
-        struct drm_i915_error_object *guc_log;
 
         struct drm_i915_error_engine {
                 int engine_id;
@@ -1386,7 +1394,6 @@ struct intel_gen6_power_mgmt {
         struct intel_rps rps;
         struct intel_rc6 rc6;
         struct intel_llc_pstate llc_pstate;
-        struct delayed_work autoenable_work;
 };
 
 /* defined intel_pm.c */
@@ -1698,6 +1705,8 @@ enum modeset_restore {
 #define DDC_PIN_D  0x06
 
 struct ddi_vbt_port_info {
+        int max_tmds_clock;
+
         /*
          * This is an index in the HDMI/DVI DDI buffer translation table.
          * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
@@ -2228,6 +2237,7 @@ struct i915_oa_ops {
 
 struct intel_cdclk_state {
         unsigned int cdclk, vco, ref;
+        u8 voltage_level;
 };
 
 struct drm_i915_private {
@@ -2339,6 +2349,7 @@ struct drm_i915_private {
         unsigned int max_dotclk_freq;
         unsigned int rawclk_freq;
         unsigned int hpll_freq;
+        unsigned int fdi_pll_freq;
         unsigned int czclk_freq;
 
         struct {
@@ -2415,6 +2426,8 @@ struct drm_i915_private {
         unsigned int active_crtcs;
         /* minimum acceptable cdclk for each pipe */
         int min_cdclk[I915_MAX_PIPES];
+        /* minimum acceptable voltage level for each pipe */
+        u8 min_voltage_level[I915_MAX_PIPES];
 
         int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
 
@@ -3046,6 +3059,8 @@ intel_info(const struct drm_i915_private *dev_priv)
                                  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
 #define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
                                  (dev_priv)->info.gt == 2)
+#define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
+                                 (dev_priv)->info.gt == 3)
 
 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
 
@@ -3137,6 +3152,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
                 ((dev_priv)->info.has_logical_ring_contexts)
+#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
+                ((dev_priv)->info.has_logical_ring_preemption)
 #define USES_PPGTT(dev_priv)            (i915_modparams.enable_ppgtt)
 #define USES_FULL_PPGTT(dev_priv)       (i915_modparams.enable_ppgtt >= 2)
 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
@@ -3315,7 +3332,9 @@ extern int i915_reset_engine(struct intel_engine_cs *engine,
                              unsigned int flags);
 
 extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
-extern int intel_guc_reset(struct drm_i915_private *dev_priv);
+extern int intel_reset_guc(struct drm_i915_private *dev_priv);
+extern int intel_guc_reset_engine(struct intel_guc *guc,
+                                  struct intel_engine_cs *engine);
 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
@@ -4107,7 +4126,6 @@ void intel_device_info_dump(struct drm_i915_private *dev_priv);
 /* modesetting */
 extern void intel_modeset_init_hw(struct drm_device *dev);
 extern int intel_modeset_init(struct drm_device *dev);
-extern void intel_modeset_gem_init(struct drm_device *dev);
 extern void intel_modeset_cleanup(struct drm_device *dev);
 extern int intel_connector_register(struct drm_connector *);
 extern void intel_connector_unregister(struct drm_connector *);
@@ -4174,8 +4192,7 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
                             enum dpio_phy phy);
 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
                               enum dpio_phy phy);
-uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
-                                             uint8_t lane_count);
+uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
                                      uint8_t lane_lat_optim_mask);
 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
@@ -4184,18 +4201,25 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
                               u32 deemph_reg_value, u32 margin_reg_value,
                               bool uniq_trans_scale);
 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
+                              const struct intel_crtc_state *crtc_state,
                               bool reset);
-void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
-void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
+void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
+                            const struct intel_crtc_state *crtc_state);
+void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
+                                const struct intel_crtc_state *crtc_state);
 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
-void chv_phy_post_pll_disable(struct intel_encoder *encoder);
+void chv_phy_post_pll_disable(struct intel_encoder *encoder,
+                              const struct intel_crtc_state *old_crtc_state);
 
 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
                               u32 demph_reg_value, u32 preemph_reg_value,
                               u32 uniqtranscale_reg_value, u32 tx3_demph);
-void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
-void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
-void vlv_phy_reset_lanes(struct intel_encoder *encoder);
+void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
+                            const struct intel_crtc_state *crtc_state);
+void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
+                                const struct intel_crtc_state *crtc_state);
+void vlv_phy_reset_lanes(struct intel_encoder *encoder,
+                         const struct intel_crtc_state *old_crtc_state);
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);