1 files changed, 59 insertions, 54 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 44e2c0f5ec50..b1d23c73c147 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -345,7 +345,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
                 value = HAS_WT(dev_priv);
                 break;
         case I915_PARAM_HAS_ALIASING_PPGTT:
-                value = USES_PPGTT(dev_priv);
+                value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
                 break;
         case I915_PARAM_HAS_SEMAPHORES:
                 value = HAS_LEGACY_SEMAPHORES(dev_priv);
@@ -645,6 +645,13 @@ static int i915_load_modeset_init(struct drm_device *dev)
         if (i915_inject_load_failure())
                 return -ENODEV;
 
+        if (INTEL_INFO(dev_priv)->num_pipes) {
+                ret = drm_vblank_init(&dev_priv->drm,
+                                      INTEL_INFO(dev_priv)->num_pipes);
+                if (ret)
+                        goto out;
+        }
+
         intel_bios_init(dev_priv);
 
         /* If we have > 1 VGA cards, then we need to arbitrate access
@@ -687,7 +694,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
         if (ret)
                 goto cleanup_modeset;
 
-        intel_setup_overlay(dev_priv);
+        intel_overlay_setup(dev_priv);
 
         if (INTEL_INFO(dev_priv)->num_pipes == 0)
                 return 0;
@@ -699,6 +706,8 @@ static int i915_load_modeset_init(struct drm_device *dev)
         /* Only enable hotplug handling once the fbdev is fully set up. */
         intel_hpd_init(dev_priv);
 
+        intel_init_ipc(dev_priv);
+
         return 0;
 
 cleanup_gem:
@@ -1030,6 +1039,7 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 
 err_uncore:
         intel_uncore_fini(dev_priv);
+        i915_mmio_cleanup(dev_priv);
 err_bridge:
         pci_dev_put(dev_priv->bridge_dev);
 
@@ -1049,17 +1059,6 @@ static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 
 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 {
-        /*
-         * i915.enable_ppgtt is read-only, so do an early pass to validate the
-         * user's requested state against the hardware/driver capabilities.  We
-         * do this now so that we can print out any log messages once rather
-         * than every time we check intel_enable_ppgtt().
-         */
-        i915_modparams.enable_ppgtt =
-                intel_sanitize_enable_ppgtt(dev_priv,
-                                            i915_modparams.enable_ppgtt);
-        DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
-
         intel_gvt_sanitize_options(dev_priv);
 }
 
@@ -1175,8 +1174,6 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
                 return -EINVAL;
         }
 
-        dram_info->valid_dimm = true;
-
         /*
          * If any of the channel is single rank channel, worst case output
          * will be same as if single rank memory, so consider single rank
@@ -1193,8 +1190,7 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
                 return -EINVAL;
         }
 
-        if (ch0.is_16gb_dimm || ch1.is_16gb_dimm)
-                dram_info->is_16gb_dimm = true;
+        dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
 
         dev_priv->dram_info.symmetric_memory = intel_is_dram_symmetric(val_ch0,
                                                                        val_ch1,
@@ -1314,7 +1310,6 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
                 return -EINVAL;
         }
 
-        dram_info->valid_dimm = true;
         dram_info->valid = true;
         return 0;
 }
@@ -1327,19 +1322,24 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
         int ret;
 
         dram_info->valid = false;
-        dram_info->valid_dimm = false;
-        dram_info->is_16gb_dimm = false;
         dram_info->rank = I915_DRAM_RANK_INVALID;
         dram_info->bandwidth_kbps = 0;
         dram_info->num_channels = 0;
 
+        /*
+         * Assume 16Gb DIMMs are present until proven otherwise.
+         * This is only used for the level 0 watermark latency
+         * w/a which does not apply to bxt/glk.
+         */
+        dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
+
         if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv))
                 return;
 
         /* Need to calculate bandwidth only for Gen9 */
         if (IS_BROXTON(dev_priv))
                 ret = bxt_get_dram_info(dev_priv);
-        else if (INTEL_GEN(dev_priv) == 9)
+        else if (IS_GEN9(dev_priv))
                 ret = skl_get_dram_info(dev_priv);
         else
                 ret = skl_dram_get_channels_info(dev_priv);
@@ -1374,6 +1374,15 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 
         intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
 
+        if (HAS_PPGTT(dev_priv)) {
+                if (intel_vgpu_active(dev_priv) &&
+                    !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
+                        i915_report_error(dev_priv,
+                                          "incompatible vGPU found, support for isolated ppGTT required\n");
+                        return -ENXIO;
+                }
+        }
+
         intel_sanitize_options(dev_priv);
 
         i915_perf_init(dev_priv);
@@ -1629,14 +1638,16 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
                 (struct intel_device_info *)ent->driver_data;
         struct intel_device_info *device_info;
         struct drm_i915_private *i915;
+        int err;
 
         i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
         if (!i915)
-                return NULL;
+                return ERR_PTR(-ENOMEM);
 
-        if (drm_dev_init(&i915->drm, &driver, &pdev->dev)) {
+        err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
+        if (err) {
                 kfree(i915);
-                return NULL;
+                return ERR_PTR(err);
         }
 
         i915->drm.pdev = pdev;
@@ -1649,8 +1660,8 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
         device_info->device_id = pdev->device;
 
         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
-                     sizeof(device_info->platform_mask) * BITS_PER_BYTE);
-        BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
+                     BITS_PER_TYPE(device_info->platform_mask));
+        BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
 
         return i915;
 }
@@ -1685,8 +1696,8 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
         int ret;
 
         dev_priv = i915_driver_create(pdev, ent);
-        if (!dev_priv)
-                return -ENOMEM;
+        if (IS_ERR(dev_priv))
+                return PTR_ERR(dev_priv);
 
         /* Disable nuclear pageflip by default on pre-ILK */
         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
@@ -1710,26 +1721,12 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
         if (ret < 0)
                 goto out_cleanup_mmio;
 
-        /*
-         * TODO: move the vblank init and parts of modeset init steps into one
-         * of the i915_driver_init_/i915_driver_register functions according
-         * to the role/effect of the given init step.
-         */
-        if (INTEL_INFO(dev_priv)->num_pipes) {
-                ret = drm_vblank_init(&dev_priv->drm,
-                                      INTEL_INFO(dev_priv)->num_pipes);
-                if (ret)
-                        goto out_cleanup_hw;
-        }
-
         ret = i915_load_modeset_init(&dev_priv->drm);
         if (ret < 0)
                 goto out_cleanup_hw;
 
         i915_driver_register(dev_priv);
 
-        intel_init_ipc(dev_priv);
-
         enable_rpm_wakeref_asserts(dev_priv);
 
         i915_welcome_messages(dev_priv);
@@ -1781,7 +1778,6 @@ void i915_driver_unload(struct drm_device *dev)
         i915_reset_error_state(dev_priv);
 
         i915_gem_fini(dev_priv);
-        intel_fbc_cleanup_cfb(dev_priv);
 
         intel_power_domains_fini_hw(dev_priv);
 
@@ -1919,9 +1915,7 @@ static int i915_drm_suspend(struct drm_device *dev)
         i915_save_state(dev_priv);
 
         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
-        intel_opregion_notify_adapter(dev_priv, opregion_target_state);
-
-        intel_opregion_unregister(dev_priv);
+        intel_opregion_suspend(dev_priv, opregion_target_state);
 
         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
 
@@ -1962,7 +1956,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
                                     get_suspend_mode(dev_priv, hibernation));
 
         ret = 0;
-        if (IS_GEN9_LP(dev_priv))
+        if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv))
                 bxt_enable_dc9(dev_priv);
         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
                 hsw_enable_pc8(dev_priv);
@@ -2040,7 +2034,6 @@ static int i915_drm_resume(struct drm_device *dev)
 
         i915_restore_state(dev_priv);
         intel_pps_unlock_regs_wa(dev_priv);
-        intel_opregion_setup(dev_priv);
 
         intel_init_pch_refclk(dev_priv);
 
@@ -2082,12 +2075,10 @@ static int i915_drm_resume(struct drm_device *dev)
          * */
         intel_hpd_init(dev_priv);
 
-        intel_opregion_register(dev_priv);
+        intel_opregion_resume(dev_priv);
 
         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
 
-        intel_opregion_notify_adapter(dev_priv, PCI_D0);
-
         intel_power_domains_enable(dev_priv);
 
         enable_rpm_wakeref_asserts(dev_priv);
@@ -2155,7 +2146,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
         intel_uncore_resume_early(dev_priv);
 
-        if (IS_GEN9_LP(dev_priv)) {
+        if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
                 gen9_sanitize_dc_state(dev_priv);
                 bxt_disable_dc9(dev_priv);
         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -2922,7 +2913,10 @@ static int intel_runtime_suspend(struct device *kdev)
         intel_uncore_suspend(dev_priv);
 
         ret = 0;
-        if (IS_GEN9_LP(dev_priv)) {
+        if (INTEL_GEN(dev_priv) >= 11) {
+                icl_display_core_uninit(dev_priv);
+                bxt_enable_dc9(dev_priv);
+        } else if (IS_GEN9_LP(dev_priv)) {
                 bxt_display_core_uninit(dev_priv);
                 bxt_enable_dc9(dev_priv);
         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -3007,7 +3001,18 @@ static int intel_runtime_resume(struct device *kdev)
         if (intel_uncore_unclaimed_mmio(dev_priv))
                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
-        if (IS_GEN9_LP(dev_priv)) {
+        if (INTEL_GEN(dev_priv) >= 11) {
+                bxt_disable_dc9(dev_priv);
+                icl_display_core_init(dev_priv, true);
+                if (dev_priv->csr.dmc_payload) {
+                        if (dev_priv->csr.allowed_dc_mask &
+                            DC_STATE_EN_UPTO_DC6)
+                                skl_enable_dc6(dev_priv);
+                        else if (dev_priv->csr.allowed_dc_mask &
+                                 DC_STATE_EN_UPTO_DC5)
+                                gen9_enable_dc5(dev_priv);
+                }
+        } else if (IS_GEN9_LP(dev_priv)) {
                 bxt_disable_dc9(dev_priv);
                 bxt_display_core_init(dev_priv, true);
                 if (dev_priv->csr.dmc_payload &&