diff options
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/handlers.c')
-rw-r--r-- | drivers/gpu/drm/i915/gvt/handlers.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 90f50f67909a..aa280bb07125 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c | |||
@@ -1609,7 +1609,7 @@ static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu, | |||
1609 | return 0; | 1609 | return 0; |
1610 | } | 1610 | } |
1611 | 1611 | ||
1612 | static int bxt_edp_psr_imr_iir_write(struct intel_vgpu *vgpu, | 1612 | static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu, |
1613 | unsigned int offset, void *p_data, unsigned int bytes) | 1613 | unsigned int offset, void *p_data, unsigned int bytes) |
1614 | { | 1614 | { |
1615 | vgpu_vreg(vgpu, offset) = 0; | 1615 | vgpu_vreg(vgpu, offset) = 0; |
@@ -2607,6 +2607,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) | |||
2607 | MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); | 2607 | MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); |
2608 | MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); | 2608 | MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); |
2609 | MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); | 2609 | MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); |
2610 | |||
2611 | MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); | ||
2612 | MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); | ||
2610 | return 0; | 2613 | return 0; |
2611 | } | 2614 | } |
2612 | 2615 | ||
@@ -3205,9 +3208,6 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt) | |||
3205 | MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT); | 3208 | MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT); |
3206 | MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT); | 3209 | MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT); |
3207 | 3210 | ||
3208 | MMIO_DH(EDP_PSR_IMR, D_BXT, NULL, bxt_edp_psr_imr_iir_write); | ||
3209 | MMIO_DH(EDP_PSR_IIR, D_BXT, NULL, bxt_edp_psr_imr_iir_write); | ||
3210 | |||
3211 | MMIO_D(RC6_CTX_BASE, D_BXT); | 3211 | MMIO_D(RC6_CTX_BASE, D_BXT); |
3212 | 3212 | ||
3213 | MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT); | 3213 | MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT); |