1 files changed, 38 insertions, 10 deletions

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index 8e28e738cb52..e6403b9549f1 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -98,6 +98,8 @@
 #define DP0_STARTVAL            0x064c
 #define DP0_ACTIVEVAL           0x0650
 #define DP0_SYNCVAL             0x0654
+#define SYNCVAL_HS_POL_ACTIVE_LOW       (1 << 15)
+#define SYNCVAL_VS_POL_ACTIVE_LOW       (1 << 31)
 #define DP0_MISC                0x0658
 #define TU_SIZE_RECOMMENDED             (63) /* LSCLK cycles per TU */
 #define BPC_6                           (0 << 5)
@@ -142,6 +144,8 @@
 #define DP0_LTLOOPCTRL          0x06d8
 #define DP0_SNKLTCTRL           0x06e4
 
+#define DP1_SRCCTRL             0x07a0
+
 /* PHY */
 #define DP_PHY_CTRL             0x0800
 #define DP_PHY_RST                      BIT(28)  /* DP PHY Global Soft Reset */
@@ -150,6 +154,7 @@
 #define PHY_M1_RST                      BIT(12)  /* Reset PHY1 Main Channel */
 #define PHY_RDY                         BIT(16)  /* PHY Main Channels Ready */
 #define PHY_M0_RST                      BIT(8)   /* Reset PHY0 Main Channel */
+#define PHY_2LANE                       BIT(2)   /* PHY Enable 2 lanes */
 #define PHY_A0_EN                       BIT(1)   /* PHY Aux Channel0 Enable */
 #define PHY_M0_EN                       BIT(0)   /* PHY Main Channel0 Enable */
 
@@ -540,6 +545,7 @@ static int tc_aux_link_setup(struct tc_data *tc)
         unsigned long rate;
         u32 value;
         int ret;
+        u32 dp_phy_ctrl;
 
         rate = clk_get_rate(tc->refclk);
         switch (rate) {
@@ -564,7 +570,10 @@ static int tc_aux_link_setup(struct tc_data *tc)
         value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
         tc_write(SYS_PLLPARAM, value);
 
-        tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN);
+        dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN;
+        if (tc->link.base.num_lanes == 2)
+                dp_phy_ctrl |= PHY_2LANE;
+        tc_write(DP_PHY_CTRL, dp_phy_ctrl);
 
         /*
          * Initially PLLs are in bypass. Force PLL parameter update,
@@ -719,7 +728,9 @@ static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode)
 
         tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay));
 
-        tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0));
+        tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0) |
+                 ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? SYNCVAL_HS_POL_ACTIVE_LOW : 0) |
+                 ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? SYNCVAL_VS_POL_ACTIVE_LOW : 0));
 
         tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
                  DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888);
@@ -829,12 +840,11 @@ static int tc_main_link_setup(struct tc_data *tc)
         if (!tc->mode)
                 return -EINVAL;
 
-        /* from excel file - DP0_SrcCtrl */
-        tc_write(DP0_SRCCTRL, DP0_SRCCTRL_SCRMBLDIS | DP0_SRCCTRL_EN810B |
-                 DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_LANES_2 |
-                 DP0_SRCCTRL_BW27 | DP0_SRCCTRL_AUTOCORRECT);
-        /* from excel file - DP1_SrcCtrl */
-        tc_write(0x07a0, 0x00003083);
+        tc_write(DP0_SRCCTRL, tc_srcctrl(tc));
+        /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
+        tc_write(DP1_SRCCTRL,
+                 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
+                 ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
 
         rate = clk_get_rate(tc->refclk);
         switch (rate) {
@@ -855,8 +865,11 @@ static int tc_main_link_setup(struct tc_data *tc)
         }
         value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
         tc_write(SYS_PLLPARAM, value);
+
         /* Setup Main Link */
-        dp_phy_ctrl = BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN |  PHY_M0_EN;
+        dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
+        if (tc->link.base.num_lanes == 2)
+                dp_phy_ctrl |= PHY_2LANE;
         tc_write(DP_PHY_CTRL, dp_phy_ctrl);
         msleep(100);
 
@@ -1105,10 +1118,20 @@ static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
 static enum drm_mode_status tc_connector_mode_valid(struct drm_connector *connector,
                                    struct drm_display_mode *mode)
 {
+        struct tc_data *tc = connector_to_tc(connector);
+        u32 req, avail;
+        u32 bits_per_pixel = 24;
+
         /* DPI interface clock limitation: upto 154 MHz */
         if (mode->clock > 154000)
                 return MODE_CLOCK_HIGH;
 
+        req = mode->clock * bits_per_pixel / 8;
+        avail = tc->link.base.num_lanes * tc->link.base.rate;
+
+        if (req > avail)
+                return MODE_BAD;
+
         return MODE_OK;
 }
 
@@ -1186,7 +1209,8 @@ static int tc_bridge_attach(struct drm_bridge *bridge)
         /* Create eDP connector */
         drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
         ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs,
-                                 DRM_MODE_CONNECTOR_eDP);
+                                 tc->panel ? DRM_MODE_CONNECTOR_eDP :
+                                 DRM_MODE_CONNECTOR_DisplayPort);
         if (ret)
                 return ret;
 
@@ -1195,6 +1219,10 @@ static int tc_bridge_attach(struct drm_bridge *bridge)
 
         drm_display_info_set_bus_formats(&tc->connector.display_info,
                                          &bus_format, 1);
+        tc->connector.display_info.bus_flags =
+                DRM_BUS_FLAG_DE_HIGH |
+                DRM_BUS_FLAG_PIXDATA_NEGEDGE |
+                DRM_BUS_FLAG_SYNC_NEGEDGE;
         drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
 
         return 0;