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-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h16
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c19
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c41
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c16
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c20
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c17
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_sdma.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_dpm.c86
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v10_0.c26
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.c26
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.c26
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c54
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c90
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v3_0.c48
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c35
-rw-r--r--drivers/gpu/drm/amd/amdkfd/kfd_process.c9
19 files changed, 416 insertions, 136 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 01657830b470..f7b49d5ce4b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1130,6 +1130,9 @@ struct amdgpu_gfx {
1130 uint32_t me_feature_version; 1130 uint32_t me_feature_version;
1131 uint32_t ce_feature_version; 1131 uint32_t ce_feature_version;
1132 uint32_t pfp_feature_version; 1132 uint32_t pfp_feature_version;
1133 uint32_t rlc_feature_version;
1134 uint32_t mec_feature_version;
1135 uint32_t mec2_feature_version;
1133 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1136 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1134 unsigned num_gfx_rings; 1137 unsigned num_gfx_rings;
1135 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1138 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
@@ -1614,6 +1617,9 @@ struct amdgpu_uvd {
1614#define AMDGPU_MAX_VCE_HANDLES 16 1617#define AMDGPU_MAX_VCE_HANDLES 16
1615#define AMDGPU_VCE_FIRMWARE_OFFSET 256 1618#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1616 1619
1620#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1621#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1622
1617struct amdgpu_vce { 1623struct amdgpu_vce {
1618 struct amdgpu_bo *vcpu_bo; 1624 struct amdgpu_bo *vcpu_bo;
1619 uint64_t gpu_addr; 1625 uint64_t gpu_addr;
@@ -1626,6 +1632,7 @@ struct amdgpu_vce {
1626 const struct firmware *fw; /* VCE firmware */ 1632 const struct firmware *fw; /* VCE firmware */
1627 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 1633 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1628 struct amdgpu_irq_src irq; 1634 struct amdgpu_irq_src irq;
1635 unsigned harvest_config;
1629}; 1636};
1630 1637
1631/* 1638/*
@@ -1635,6 +1642,7 @@ struct amdgpu_sdma {
1635 /* SDMA firmware */ 1642 /* SDMA firmware */
1636 const struct firmware *fw; 1643 const struct firmware *fw;
1637 uint32_t fw_version; 1644 uint32_t fw_version;
1645 uint32_t feature_version;
1638 1646
1639 struct amdgpu_ring ring; 1647 struct amdgpu_ring ring;
1640}; 1648};
@@ -1862,6 +1870,12 @@ typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1862typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1870typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1863typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1871typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1864 1872
1873struct amdgpu_ip_block_status {
1874 bool valid;
1875 bool sw;
1876 bool hw;
1877};
1878
1865struct amdgpu_device { 1879struct amdgpu_device {
1866 struct device *dev; 1880 struct device *dev;
1867 struct drm_device *ddev; 1881 struct drm_device *ddev;
@@ -2004,7 +2018,7 @@ struct amdgpu_device {
2004 2018
2005 const struct amdgpu_ip_block_version *ip_blocks; 2019 const struct amdgpu_ip_block_version *ip_blocks;
2006 int num_ip_blocks; 2020 int num_ip_blocks;
2007 bool *ip_block_enabled; 2021 struct amdgpu_ip_block_status *ip_block_status;
2008 struct mutex mn_lock; 2022 struct mutex mn_lock;
2009 DECLARE_HASHTABLE(mn_hash, 7); 2023 DECLARE_HASHTABLE(mn_hash, 7);
2010 2024
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index d63135bf29c0..1f040d85ac47 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -669,6 +669,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
669static int amdgpu_cs_dependencies(struct amdgpu_device *adev, 669static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
670 struct amdgpu_cs_parser *p) 670 struct amdgpu_cs_parser *p)
671{ 671{
672 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
672 struct amdgpu_ib *ib; 673 struct amdgpu_ib *ib;
673 int i, j, r; 674 int i, j, r;
674 675
@@ -694,6 +695,7 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
694 for (j = 0; j < num_deps; ++j) { 695 for (j = 0; j < num_deps; ++j) {
695 struct amdgpu_fence *fence; 696 struct amdgpu_fence *fence;
696 struct amdgpu_ring *ring; 697 struct amdgpu_ring *ring;
698 struct amdgpu_ctx *ctx;
697 699
698 r = amdgpu_cs_get_ring(adev, deps[j].ip_type, 700 r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
699 deps[j].ip_instance, 701 deps[j].ip_instance,
@@ -701,14 +703,21 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
701 if (r) 703 if (r)
702 return r; 704 return r;
703 705
706 ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
707 if (ctx == NULL)
708 return -EINVAL;
709
704 r = amdgpu_fence_recreate(ring, p->filp, 710 r = amdgpu_fence_recreate(ring, p->filp,
705 deps[j].handle, 711 deps[j].handle,
706 &fence); 712 &fence);
707 if (r) 713 if (r) {
714 amdgpu_ctx_put(ctx);
708 return r; 715 return r;
716 }
709 717
710 amdgpu_sync_fence(&ib->sync, fence); 718 amdgpu_sync_fence(&ib->sync, fence);
711 amdgpu_fence_unref(&fence); 719 amdgpu_fence_unref(&fence);
720 amdgpu_ctx_put(ctx);
712 } 721 }
713 } 722 }
714 723
@@ -808,12 +817,16 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
808 817
809 r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance, 818 r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
810 wait->in.ring, &ring); 819 wait->in.ring, &ring);
811 if (r) 820 if (r) {
821 amdgpu_ctx_put(ctx);
812 return r; 822 return r;
823 }
813 824
814 r = amdgpu_fence_recreate(ring, filp, wait->in.handle, &fence); 825 r = amdgpu_fence_recreate(ring, filp, wait->in.handle, &fence);
815 if (r) 826 if (r) {
827 amdgpu_ctx_put(ctx);
816 return r; 828 return r;
829 }
817 830
818 r = fence_wait_timeout(&fence->base, true, timeout); 831 r = fence_wait_timeout(&fence->base, true, timeout);
819 amdgpu_fence_unref(&fence); 832 amdgpu_fence_unref(&fence);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ba46be361c9b..99f158e1baff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1191,8 +1191,9 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
1191 return -EINVAL; 1191 return -EINVAL;
1192 } 1192 }
1193 1193
1194 adev->ip_block_enabled = kcalloc(adev->num_ip_blocks, sizeof(bool), GFP_KERNEL); 1194 adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1195 if (adev->ip_block_enabled == NULL) 1195 sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1196 if (adev->ip_block_status == NULL)
1196 return -ENOMEM; 1197 return -ENOMEM;
1197 1198
1198 if (adev->ip_blocks == NULL) { 1199 if (adev->ip_blocks == NULL) {
@@ -1203,14 +1204,19 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
1203 for (i = 0; i < adev->num_ip_blocks; i++) { 1204 for (i = 0; i < adev->num_ip_blocks; i++) {
1204 if ((amdgpu_ip_block_mask & (1 << i)) == 0) { 1205 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1205 DRM_ERROR("disabled ip block: %d\n", i); 1206 DRM_ERROR("disabled ip block: %d\n", i);
1206 adev->ip_block_enabled[i] = false; 1207 adev->ip_block_status[i].valid = false;
1207 } else { 1208 } else {
1208 if (adev->ip_blocks[i].funcs->early_init) { 1209 if (adev->ip_blocks[i].funcs->early_init) {
1209 r = adev->ip_blocks[i].funcs->early_init((void *)adev); 1210 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1210 if (r) 1211 if (r == -ENOENT)
1212 adev->ip_block_status[i].valid = false;
1213 else if (r)
1211 return r; 1214 return r;
1215 else
1216 adev->ip_block_status[i].valid = true;
1217 } else {
1218 adev->ip_block_status[i].valid = true;
1212 } 1219 }
1213 adev->ip_block_enabled[i] = true;
1214 } 1220 }
1215 } 1221 }
1216 1222
@@ -1222,11 +1228,12 @@ static int amdgpu_init(struct amdgpu_device *adev)
1222 int i, r; 1228 int i, r;
1223 1229
1224 for (i = 0; i < adev->num_ip_blocks; i++) { 1230 for (i = 0; i < adev->num_ip_blocks; i++) {
1225 if (!adev->ip_block_enabled[i]) 1231 if (!adev->ip_block_status[i].valid)
1226 continue; 1232 continue;
1227 r = adev->ip_blocks[i].funcs->sw_init((void *)adev); 1233 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1228 if (r) 1234 if (r)
1229 return r; 1235 return r;
1236 adev->ip_block_status[i].sw = true;
1230 /* need to do gmc hw init early so we can allocate gpu mem */ 1237 /* need to do gmc hw init early so we can allocate gpu mem */
1231 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) { 1238 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1232 r = amdgpu_vram_scratch_init(adev); 1239 r = amdgpu_vram_scratch_init(adev);
@@ -1238,11 +1245,12 @@ static int amdgpu_init(struct amdgpu_device *adev)
1238 r = amdgpu_wb_init(adev); 1245 r = amdgpu_wb_init(adev);
1239 if (r) 1246 if (r)
1240 return r; 1247 return r;
1248 adev->ip_block_status[i].hw = true;
1241 } 1249 }
1242 } 1250 }
1243 1251
1244 for (i = 0; i < adev->num_ip_blocks; i++) { 1252 for (i = 0; i < adev->num_ip_blocks; i++) {
1245 if (!adev->ip_block_enabled[i]) 1253 if (!adev->ip_block_status[i].sw)
1246 continue; 1254 continue;
1247 /* gmc hw init is done early */ 1255 /* gmc hw init is done early */
1248 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) 1256 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
@@ -1250,6 +1258,7 @@ static int amdgpu_init(struct amdgpu_device *adev)
1250 r = adev->ip_blocks[i].funcs->hw_init((void *)adev); 1258 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1251 if (r) 1259 if (r)
1252 return r; 1260 return r;
1261 adev->ip_block_status[i].hw = true;
1253 } 1262 }
1254 1263
1255 return 0; 1264 return 0;
@@ -1260,7 +1269,7 @@ static int amdgpu_late_init(struct amdgpu_device *adev)
1260 int i = 0, r; 1269 int i = 0, r;
1261 1270
1262 for (i = 0; i < adev->num_ip_blocks; i++) { 1271 for (i = 0; i < adev->num_ip_blocks; i++) {
1263 if (!adev->ip_block_enabled[i]) 1272 if (!adev->ip_block_status[i].valid)
1264 continue; 1273 continue;
1265 /* enable clockgating to save power */ 1274 /* enable clockgating to save power */
1266 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, 1275 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
@@ -1282,7 +1291,7 @@ static int amdgpu_fini(struct amdgpu_device *adev)
1282 int i, r; 1291 int i, r;
1283 1292
1284 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 1293 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1285 if (!adev->ip_block_enabled[i]) 1294 if (!adev->ip_block_status[i].hw)
1286 continue; 1295 continue;
1287 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) { 1296 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1288 amdgpu_wb_fini(adev); 1297 amdgpu_wb_fini(adev);
@@ -1295,14 +1304,16 @@ static int amdgpu_fini(struct amdgpu_device *adev)
1295 return r; 1304 return r;
1296 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev); 1305 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1297 /* XXX handle errors */ 1306 /* XXX handle errors */
1307 adev->ip_block_status[i].hw = false;
1298 } 1308 }
1299 1309
1300 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 1310 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1301 if (!adev->ip_block_enabled[i]) 1311 if (!adev->ip_block_status[i].sw)
1302 continue; 1312 continue;
1303 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev); 1313 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1304 /* XXX handle errors */ 1314 /* XXX handle errors */
1305 adev->ip_block_enabled[i] = false; 1315 adev->ip_block_status[i].sw = false;
1316 adev->ip_block_status[i].valid = false;
1306 } 1317 }
1307 1318
1308 return 0; 1319 return 0;
@@ -1313,7 +1324,7 @@ static int amdgpu_suspend(struct amdgpu_device *adev)
1313 int i, r; 1324 int i, r;
1314 1325
1315 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 1326 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1316 if (!adev->ip_block_enabled[i]) 1327 if (!adev->ip_block_status[i].valid)
1317 continue; 1328 continue;
1318 /* ungate blocks so that suspend can properly shut them down */ 1329 /* ungate blocks so that suspend can properly shut them down */
1319 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, 1330 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
@@ -1331,7 +1342,7 @@ static int amdgpu_resume(struct amdgpu_device *adev)
1331 int i, r; 1342 int i, r;
1332 1343
1333 for (i = 0; i < adev->num_ip_blocks; i++) { 1344 for (i = 0; i < adev->num_ip_blocks; i++) {
1334 if (!adev->ip_block_enabled[i]) 1345 if (!adev->ip_block_status[i].valid)
1335 continue; 1346 continue;
1336 r = adev->ip_blocks[i].funcs->resume(adev); 1347 r = adev->ip_blocks[i].funcs->resume(adev);
1337 if (r) 1348 if (r)
@@ -1577,8 +1588,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
1577 amdgpu_fence_driver_fini(adev); 1588 amdgpu_fence_driver_fini(adev);
1578 amdgpu_fbdev_fini(adev); 1589 amdgpu_fbdev_fini(adev);
1579 r = amdgpu_fini(adev); 1590 r = amdgpu_fini(adev);
1580 kfree(adev->ip_block_enabled); 1591 kfree(adev->ip_block_status);
1581 adev->ip_block_enabled = NULL; 1592 adev->ip_block_status = NULL;
1582 adev->accel_working = false; 1593 adev->accel_working = false;
1583 /* free i2c buses */ 1594 /* free i2c buses */
1584 amdgpu_i2c_fini(adev); 1595 amdgpu_i2c_fini(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 975edb1000a2..4afc507820c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -352,7 +352,7 @@ unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
352 if (((int64_t)timeout_ns) < 0) 352 if (((int64_t)timeout_ns) < 0)
353 return MAX_SCHEDULE_TIMEOUT; 353 return MAX_SCHEDULE_TIMEOUT;
354 354
355 timeout = ktime_sub_ns(ktime_get(), timeout_ns); 355 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
356 if (ktime_to_ns(timeout) < 0) 356 if (ktime_to_ns(timeout) < 0)
357 return 0; 357 return 0;
358 358
@@ -449,7 +449,7 @@ out:
449 * vital here, so they are not reported back to userspace. 449 * vital here, so they are not reported back to userspace.
450 */ 450 */
451static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 451static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
452 struct amdgpu_bo_va *bo_va) 452 struct amdgpu_bo_va *bo_va, uint32_t operation)
453{ 453{
454 struct ttm_validate_buffer tv, *entry; 454 struct ttm_validate_buffer tv, *entry;
455 struct amdgpu_bo_list_entry *vm_bos; 455 struct amdgpu_bo_list_entry *vm_bos;
@@ -485,7 +485,9 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
485 if (r) 485 if (r)
486 goto error_unlock; 486 goto error_unlock;
487 487
488 r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem); 488
489 if (operation == AMDGPU_VA_OP_MAP)
490 r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem);
489 491
490error_unlock: 492error_unlock:
491 mutex_unlock(&bo_va->vm->mutex); 493 mutex_unlock(&bo_va->vm->mutex);
@@ -580,7 +582,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
580 } 582 }
581 583
582 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE)) 584 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE))
583 amdgpu_gem_va_update_vm(adev, bo_va); 585 amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
584 586
585 drm_gem_object_unreference_unlocked(gobj); 587 drm_gem_object_unreference_unlocked(gobj);
586 return r; 588 return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 52dff75aac6f..bc0fac618a3f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -180,16 +180,16 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
180 if (vm) { 180 if (vm) {
181 /* do context switch */ 181 /* do context switch */
182 amdgpu_vm_flush(ring, vm, ib->sync.last_vm_update); 182 amdgpu_vm_flush(ring, vm, ib->sync.last_vm_update);
183 }
184 183
185 if (vm && ring->funcs->emit_gds_switch) 184 if (ring->funcs->emit_gds_switch)
186 amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id, 185 amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id,
187 ib->gds_base, ib->gds_size, 186 ib->gds_base, ib->gds_size,
188 ib->gws_base, ib->gws_size, 187 ib->gws_base, ib->gws_size,
189 ib->oa_base, ib->oa_size); 188 ib->oa_base, ib->oa_size);
190 189
191 if (ring->funcs->emit_hdp_flush) 190 if (ring->funcs->emit_hdp_flush)
192 amdgpu_ring_emit_hdp_flush(ring); 191 amdgpu_ring_emit_hdp_flush(ring);
192 }
193 193
194 old_ctx = ring->current_ctx; 194 old_ctx = ring->current_ctx;
195 for (i = 0; i < num_ibs; ++i) { 195 for (i = 0; i < num_ibs; ++i) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 5533434c7a8f..3bfe67de8349 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -235,7 +235,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
235 235
236 for (i = 0; i < adev->num_ip_blocks; i++) { 236 for (i = 0; i < adev->num_ip_blocks; i++) {
237 if (adev->ip_blocks[i].type == type && 237 if (adev->ip_blocks[i].type == type &&
238 adev->ip_block_enabled[i]) { 238 adev->ip_block_status[i].valid) {
239 ip.hw_ip_version_major = adev->ip_blocks[i].major; 239 ip.hw_ip_version_major = adev->ip_blocks[i].major;
240 ip.hw_ip_version_minor = adev->ip_blocks[i].minor; 240 ip.hw_ip_version_minor = adev->ip_blocks[i].minor;
241 ip.capabilities_flags = 0; 241 ip.capabilities_flags = 0;
@@ -274,7 +274,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
274 274
275 for (i = 0; i < adev->num_ip_blocks; i++) 275 for (i = 0; i < adev->num_ip_blocks; i++)
276 if (adev->ip_blocks[i].type == type && 276 if (adev->ip_blocks[i].type == type &&
277 adev->ip_block_enabled[i] && 277 adev->ip_block_status[i].valid &&
278 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 278 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
279 count++; 279 count++;
280 280
@@ -317,16 +317,17 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
317 break; 317 break;
318 case AMDGPU_INFO_FW_GFX_RLC: 318 case AMDGPU_INFO_FW_GFX_RLC:
319 fw_info.ver = adev->gfx.rlc_fw_version; 319 fw_info.ver = adev->gfx.rlc_fw_version;
320 fw_info.feature = 0; 320 fw_info.feature = adev->gfx.rlc_feature_version;
321 break; 321 break;
322 case AMDGPU_INFO_FW_GFX_MEC: 322 case AMDGPU_INFO_FW_GFX_MEC:
323 if (info->query_fw.index == 0) 323 if (info->query_fw.index == 0) {
324 fw_info.ver = adev->gfx.mec_fw_version; 324 fw_info.ver = adev->gfx.mec_fw_version;
325 else if (info->query_fw.index == 1) 325 fw_info.feature = adev->gfx.mec_feature_version;
326 } else if (info->query_fw.index == 1) {
326 fw_info.ver = adev->gfx.mec2_fw_version; 327 fw_info.ver = adev->gfx.mec2_fw_version;
327 else 328 fw_info.feature = adev->gfx.mec2_feature_version;
329 } else
328 return -EINVAL; 330 return -EINVAL;
329 fw_info.feature = 0;
330 break; 331 break;
331 case AMDGPU_INFO_FW_SMC: 332 case AMDGPU_INFO_FW_SMC:
332 fw_info.ver = adev->pm.fw_version; 333 fw_info.ver = adev->pm.fw_version;
@@ -336,7 +337,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
336 if (info->query_fw.index >= 2) 337 if (info->query_fw.index >= 2)
337 return -EINVAL; 338 return -EINVAL;
338 fw_info.ver = adev->sdma[info->query_fw.index].fw_version; 339 fw_info.ver = adev->sdma[info->query_fw.index].fw_version;
339 fw_info.feature = 0; 340 fw_info.feature = adev->sdma[info->query_fw.index].feature_version;
340 break; 341 break;
341 default: 342 default:
342 return -EINVAL; 343 return -EINVAL;
@@ -416,7 +417,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
416 return n ? -EFAULT : 0; 417 return n ? -EFAULT : 0;
417 } 418 }
418 case AMDGPU_INFO_DEV_INFO: { 419 case AMDGPU_INFO_DEV_INFO: {
419 struct drm_amdgpu_info_device dev_info; 420 struct drm_amdgpu_info_device dev_info = {};
420 struct amdgpu_cu_info cu_info; 421 struct amdgpu_cu_info cu_info;
421 422
422 dev_info.device_id = dev->pdev->device; 423 dev_info.device_id = dev->pdev->device;
@@ -459,6 +460,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
459 memcpy(&dev_info.cu_bitmap[0], &cu_info.bitmap[0], sizeof(cu_info.bitmap)); 460 memcpy(&dev_info.cu_bitmap[0], &cu_info.bitmap[0], sizeof(cu_info.bitmap));
460 dev_info.vram_type = adev->mc.vram_type; 461 dev_info.vram_type = adev->mc.vram_type;
461 dev_info.vram_bit_width = adev->mc.vram_width; 462 dev_info.vram_bit_width = adev->mc.vram_width;
463 dev_info.vce_harvest_config = adev->vce.harvest_config;
462 464
463 return copy_to_user(out, &dev_info, 465 return copy_to_user(out, &dev_info,
464 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 466 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 2f7a5efa21c2..f5c22556ec2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -374,7 +374,7 @@ static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
374 unsigned height_in_mb = ALIGN(height / 16, 2); 374 unsigned height_in_mb = ALIGN(height / 16, 2);
375 unsigned fs_in_mb = width_in_mb * height_in_mb; 375 unsigned fs_in_mb = width_in_mb * height_in_mb;
376 376
377 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; 377 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer, min_ctx_size;
378 378
379 image_size = width * height; 379 image_size = width * height;
380 image_size += image_size / 2; 380 image_size += image_size / 2;
@@ -466,6 +466,8 @@ static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
466 466
467 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 467 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
468 min_dpb_size = image_size * num_dpb_buffer; 468 min_dpb_size = image_size * num_dpb_buffer;
469 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
470 * 16 * num_dpb_buffer + 52 * 1024;
469 break; 471 break;
470 472
471 default: 473 default:
@@ -486,6 +488,7 @@ static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
486 488
487 buf_sizes[0x1] = dpb_size; 489 buf_sizes[0x1] = dpb_size;
488 buf_sizes[0x2] = image_size; 490 buf_sizes[0x2] = image_size;
491 buf_sizes[0x4] = min_ctx_size;
489 return 0; 492 return 0;
490} 493}
491 494
@@ -628,6 +631,13 @@ static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
628 return -EINVAL; 631 return -EINVAL;
629 } 632 }
630 633
634 } else if (cmd == 0x206) {
635 if ((end - start) < ctx->buf_sizes[4]) {
636 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
637 (unsigned)(end - start),
638 ctx->buf_sizes[4]);
639 return -EINVAL;
640 }
631 } else if ((cmd != 0x100) && (cmd != 0x204)) { 641 } else if ((cmd != 0x100) && (cmd != 0x204)) {
632 DRM_ERROR("invalid UVD command %X!\n", cmd); 642 DRM_ERROR("invalid UVD command %X!\n", cmd);
633 return -EINVAL; 643 return -EINVAL;
@@ -755,9 +765,10 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
755 struct amdgpu_uvd_cs_ctx ctx = {}; 765 struct amdgpu_uvd_cs_ctx ctx = {};
756 unsigned buf_sizes[] = { 766 unsigned buf_sizes[] = {
757 [0x00000000] = 2048, 767 [0x00000000] = 2048,
758 [0x00000001] = 32 * 1024 * 1024, 768 [0x00000001] = 0xFFFFFFFF,
759 [0x00000002] = 2048 * 1152 * 3, 769 [0x00000002] = 0xFFFFFFFF,
760 [0x00000003] = 2048, 770 [0x00000003] = 2048,
771 [0x00000004] = 0xFFFFFFFF,
761 }; 772 };
762 struct amdgpu_ib *ib = &parser->ibs[ib_idx]; 773 struct amdgpu_ib *ib = &parser->ibs[ib_idx];
763 int r; 774 int r;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index ab83cc1ca4cc..15df46c93f0a 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -500,6 +500,7 @@ static int cik_sdma_load_microcode(struct amdgpu_device *adev)
500 amdgpu_ucode_print_sdma_hdr(&hdr->header); 500 amdgpu_ucode_print_sdma_hdr(&hdr->header);
501 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 501 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
502 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 502 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
503 adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
503 fw_data = (const __le32 *) 504 fw_data = (const __le32 *)
504 (adev->sdma[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 505 (adev->sdma[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
505 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 506 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index f75a31df30bd..ace870afc7d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -494,29 +494,67 @@ static void cz_dpm_fini(struct amdgpu_device *adev)
494 amdgpu_free_extended_power_table(adev); 494 amdgpu_free_extended_power_table(adev);
495} 495}
496 496
497#define ixSMUSVI_NB_CURRENTVID 0xD8230044
498#define CURRENT_NB_VID_MASK 0xff000000
499#define CURRENT_NB_VID__SHIFT 24
500#define ixSMUSVI_GFX_CURRENTVID 0xD8230048
501#define CURRENT_GFX_VID_MASK 0xff000000
502#define CURRENT_GFX_VID__SHIFT 24
503
497static void 504static void
498cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, 505cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
499 struct seq_file *m) 506 struct seq_file *m)
500{ 507{
508 struct cz_power_info *pi = cz_get_pi(adev);
501 struct amdgpu_clock_voltage_dependency_table *table = 509 struct amdgpu_clock_voltage_dependency_table *table =
502 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 510 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
503 u32 current_index = 511 struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
504 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & 512 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
505 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >> 513 struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
506 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT; 514 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
507 u32 sclk, tmp; 515 u32 sclk_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX),
508 u16 vddc; 516 TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
509 517 u32 uvd_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
510 if (current_index >= NUM_SCLK_LEVELS) { 518 TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
511 seq_printf(m, "invalid dpm profile %d\n", current_index); 519 u32 vce_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
520 TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
521 u32 sclk, vclk, dclk, ecclk, tmp;
522 u16 vddnb, vddgfx;
523
524 if (sclk_index >= NUM_SCLK_LEVELS) {
525 seq_printf(m, "invalid sclk dpm profile %d\n", sclk_index);
512 } else { 526 } else {
513 sclk = table->entries[current_index].clk; 527 sclk = table->entries[sclk_index].clk;
514 tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) & 528 seq_printf(m, "%u sclk: %u\n", sclk_index, sclk);
515 SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >> 529 }
516 SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT; 530
517 vddc = cz_convert_8bit_index_to_voltage(adev, (u16)tmp); 531 tmp = (RREG32_SMC(ixSMUSVI_NB_CURRENTVID) &
518 seq_printf(m, "power level %d sclk: %u vddc: %u\n", 532 CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
519 current_index, sclk, vddc); 533 vddnb = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
534 tmp = (RREG32_SMC(ixSMUSVI_GFX_CURRENTVID) &
535 CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
536 vddgfx = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
537 seq_printf(m, "vddnb: %u vddgfx: %u\n", vddnb, vddgfx);
538
539 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
540 if (!pi->uvd_power_gated) {
541 if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
542 seq_printf(m, "invalid uvd dpm level %d\n", uvd_index);
543 } else {
544 vclk = uvd_table->entries[uvd_index].vclk;
545 dclk = uvd_table->entries[uvd_index].dclk;
546 seq_printf(m, "%u uvd vclk: %u dclk: %u\n", uvd_index, vclk, dclk);
547 }
548 }
549
550 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en");
551 if (!pi->vce_power_gated) {
552 if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
553 seq_printf(m, "invalid vce dpm level %d\n", vce_index);
554 } else {
555 ecclk = vce_table->entries[vce_index].ecclk;
556 seq_printf(m, "%u vce ecclk: %u\n", vce_index, ecclk);
557 }
520 } 558 }
521} 559}
522 560
@@ -1679,25 +1717,31 @@ static int cz_dpm_unforce_dpm_levels(struct amdgpu_device *adev)
1679 if (ret) 1717 if (ret)
1680 return ret; 1718 return ret;
1681 1719
1682 DRM_INFO("DPM unforce state min=%d, max=%d.\n", 1720 DRM_DEBUG("DPM unforce state min=%d, max=%d.\n",
1683 pi->sclk_dpm.soft_min_clk, 1721 pi->sclk_dpm.soft_min_clk,
1684 pi->sclk_dpm.soft_max_clk); 1722 pi->sclk_dpm.soft_max_clk);
1685 1723
1686 return 0; 1724 return 0;
1687} 1725}
1688 1726
1689static int cz_dpm_force_dpm_level(struct amdgpu_device *adev, 1727static int cz_dpm_force_dpm_level(struct amdgpu_device *adev,
1690 enum amdgpu_dpm_forced_level level) 1728 enum amdgpu_dpm_forced_level level)
1691{ 1729{
1692 int ret = 0; 1730 int ret = 0;
1693 1731
1694 switch (level) { 1732 switch (level) {
1695 case AMDGPU_DPM_FORCED_LEVEL_HIGH: 1733 case AMDGPU_DPM_FORCED_LEVEL_HIGH:
1734 ret = cz_dpm_unforce_dpm_levels(adev);
1735 if (ret)
1736 return ret;
1696 ret = cz_dpm_force_highest(adev); 1737 ret = cz_dpm_force_highest(adev);
1697 if (ret) 1738 if (ret)
1698 return ret; 1739 return ret;
1699 break; 1740 break;
1700 case AMDGPU_DPM_FORCED_LEVEL_LOW: 1741 case AMDGPU_DPM_FORCED_LEVEL_LOW:
1742 ret = cz_dpm_unforce_dpm_levels(adev);
1743 if (ret)
1744 return ret;
1701 ret = cz_dpm_force_lowest(adev); 1745 ret = cz_dpm_force_lowest(adev);
1702 if (ret) 1746 if (ret)
1703 return ret; 1747 return ret;
@@ -1711,6 +1755,8 @@ static int cz_dpm_force_dpm_level(struct amdgpu_device *adev,
1711 break; 1755 break;
1712 } 1756 }
1713 1757
1758 adev->pm.dpm.forced_level = level;
1759
1714 return ret; 1760 return ret;
1715} 1761}
1716 1762
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 5cde635978f9..e70a26f587a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -2632,6 +2632,7 @@ static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2632 struct drm_device *dev = crtc->dev; 2632 struct drm_device *dev = crtc->dev;
2633 struct amdgpu_device *adev = dev->dev_private; 2633 struct amdgpu_device *adev = dev->dev_private;
2634 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2634 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2635 unsigned type;
2635 2636
2636 switch (mode) { 2637 switch (mode) {
2637 case DRM_MODE_DPMS_ON: 2638 case DRM_MODE_DPMS_ON:
@@ -2640,6 +2641,9 @@ static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2640 dce_v10_0_vga_enable(crtc, true); 2641 dce_v10_0_vga_enable(crtc, true);
2641 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2642 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2642 dce_v10_0_vga_enable(crtc, false); 2643 dce_v10_0_vga_enable(crtc, false);
2644 /* Make sure VBLANK interrupt is still enabled */
2645 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2646 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2643 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id); 2647 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2644 dce_v10_0_crtc_load_lut(crtc); 2648 dce_v10_0_crtc_load_lut(crtc);
2645 break; 2649 break;
@@ -3403,19 +3407,25 @@ static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3403 3407
3404 switch (entry->src_data) { 3408 switch (entry->src_data) {
3405 case 0: /* vblank */ 3409 case 0: /* vblank */
3406 if (disp_int & interrupt_status_offsets[crtc].vblank) { 3410 if (disp_int & interrupt_status_offsets[crtc].vblank)
3407 dce_v10_0_crtc_vblank_int_ack(adev, crtc); 3411 dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3408 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3412 else
3409 drm_handle_vblank(adev->ddev, crtc); 3413 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3410 } 3414
3411 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3415 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3416 drm_handle_vblank(adev->ddev, crtc);
3412 } 3417 }
3418 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3419
3413 break; 3420 break;
3414 case 1: /* vline */ 3421 case 1: /* vline */
3415 if (disp_int & interrupt_status_offsets[crtc].vline) { 3422 if (disp_int & interrupt_status_offsets[crtc].vline)
3416 dce_v10_0_crtc_vline_int_ack(adev, crtc); 3423 dce_v10_0_crtc_vline_int_ack(adev, crtc);
3417 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3424 else
3418 } 3425 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3426
3427 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3428
3419 break; 3429 break;
3420 default: 3430 default:
3421 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3431 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 95efd98b202d..dcb402ee048a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -2631,6 +2631,7 @@ static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2631 struct drm_device *dev = crtc->dev; 2631 struct drm_device *dev = crtc->dev;
2632 struct amdgpu_device *adev = dev->dev_private; 2632 struct amdgpu_device *adev = dev->dev_private;
2633 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2633 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2634 unsigned type;
2634 2635
2635 switch (mode) { 2636 switch (mode) {
2636 case DRM_MODE_DPMS_ON: 2637 case DRM_MODE_DPMS_ON:
@@ -2639,6 +2640,9 @@ static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2639 dce_v11_0_vga_enable(crtc, true); 2640 dce_v11_0_vga_enable(crtc, true);
2640 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2641 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2641 dce_v11_0_vga_enable(crtc, false); 2642 dce_v11_0_vga_enable(crtc, false);
2643 /* Make sure VBLANK interrupt is still enabled */
2644 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2645 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2642 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id); 2646 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2643 dce_v11_0_crtc_load_lut(crtc); 2647 dce_v11_0_crtc_load_lut(crtc);
2644 break; 2648 break;
@@ -3402,19 +3406,25 @@ static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3402 3406
3403 switch (entry->src_data) { 3407 switch (entry->src_data) {
3404 case 0: /* vblank */ 3408 case 0: /* vblank */
3405 if (disp_int & interrupt_status_offsets[crtc].vblank) { 3409 if (disp_int & interrupt_status_offsets[crtc].vblank)
3406 dce_v11_0_crtc_vblank_int_ack(adev, crtc); 3410 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3407 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3411 else
3408 drm_handle_vblank(adev->ddev, crtc); 3412 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3409 } 3413
3410 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3414 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3415 drm_handle_vblank(adev->ddev, crtc);
3411 } 3416 }
3417 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3418
3412 break; 3419 break;
3413 case 1: /* vline */ 3420 case 1: /* vline */
3414 if (disp_int & interrupt_status_offsets[crtc].vline) { 3421 if (disp_int & interrupt_status_offsets[crtc].vline)
3415 dce_v11_0_crtc_vline_int_ack(adev, crtc); 3422 dce_v11_0_crtc_vline_int_ack(adev, crtc);
3416 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3423 else
3417 } 3424 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3425
3426 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3427
3418 break; 3428 break;
3419 default: 3429 default:
3420 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3430 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index aaca8d663f2c..cc050a329c49 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -2566,6 +2566,7 @@ static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2566 struct drm_device *dev = crtc->dev; 2566 struct drm_device *dev = crtc->dev;
2567 struct amdgpu_device *adev = dev->dev_private; 2567 struct amdgpu_device *adev = dev->dev_private;
2568 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2568 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2569 unsigned type;
2569 2570
2570 switch (mode) { 2571 switch (mode) {
2571 case DRM_MODE_DPMS_ON: 2572 case DRM_MODE_DPMS_ON:
@@ -2574,6 +2575,9 @@ static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2574 dce_v8_0_vga_enable(crtc, true); 2575 dce_v8_0_vga_enable(crtc, true);
2575 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2576 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2576 dce_v8_0_vga_enable(crtc, false); 2577 dce_v8_0_vga_enable(crtc, false);
2578 /* Make sure VBLANK interrupt is still enabled */
2579 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2580 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2577 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id); 2581 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2578 dce_v8_0_crtc_load_lut(crtc); 2582 dce_v8_0_crtc_load_lut(crtc);
2579 break; 2583 break;
@@ -3237,19 +3241,25 @@ static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3237 3241
3238 switch (entry->src_data) { 3242 switch (entry->src_data) {
3239 case 0: /* vblank */ 3243 case 0: /* vblank */
3240 if (disp_int & interrupt_status_offsets[crtc].vblank) { 3244 if (disp_int & interrupt_status_offsets[crtc].vblank)
3241 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK); 3245 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
3242 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3246 else
3243 drm_handle_vblank(adev->ddev, crtc); 3247 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3244 } 3248
3245 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3249 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3250 drm_handle_vblank(adev->ddev, crtc);
3246 } 3251 }
3252 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3253
3247 break; 3254 break;
3248 case 1: /* vline */ 3255 case 1: /* vline */
3249 if (disp_int & interrupt_status_offsets[crtc].vline) { 3256 if (disp_int & interrupt_status_offsets[crtc].vline)
3250 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK); 3257 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
3251 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3258 else
3252 } 3259 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3260
3261 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3262
3253 break; 3263 break;
3254 default: 3264 default:
3255 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3265 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 2c188fb9fd22..0d8bf2cb1956 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2561,7 +2561,7 @@ static bool gfx_v7_0_ring_emit_semaphore(struct amdgpu_ring *ring,
2561 * sheduling on the ring. This function schedules the IB 2561 * sheduling on the ring. This function schedules the IB
2562 * on the gfx ring for execution by the GPU. 2562 * on the gfx ring for execution by the GPU.
2563 */ 2563 */
2564static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring, 2564static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2565 struct amdgpu_ib *ib) 2565 struct amdgpu_ib *ib)
2566{ 2566{
2567 bool need_ctx_switch = ring->current_ctx != ib->ctx; 2567 bool need_ctx_switch = ring->current_ctx != ib->ctx;
@@ -2569,15 +2569,10 @@ static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
2569 u32 next_rptr = ring->wptr + 5; 2569 u32 next_rptr = ring->wptr + 5;
2570 2570
2571 /* drop the CE preamble IB for the same context */ 2571 /* drop the CE preamble IB for the same context */
2572 if ((ring->type == AMDGPU_RING_TYPE_GFX) && 2572 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
2573 (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
2574 !need_ctx_switch)
2575 return; 2573 return;
2576 2574
2577 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) 2575 if (need_ctx_switch)
2578 control |= INDIRECT_BUFFER_VALID;
2579
2580 if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX)
2581 next_rptr += 2; 2576 next_rptr += 2;
2582 2577
2583 next_rptr += 4; 2578 next_rptr += 4;
@@ -2588,7 +2583,7 @@ static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
2588 amdgpu_ring_write(ring, next_rptr); 2583 amdgpu_ring_write(ring, next_rptr);
2589 2584
2590 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 2585 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
2591 if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) { 2586 if (need_ctx_switch) {
2592 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2587 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2593 amdgpu_ring_write(ring, 0); 2588 amdgpu_ring_write(ring, 0);
2594 } 2589 }
@@ -2611,6 +2606,35 @@ static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
2611 amdgpu_ring_write(ring, control); 2606 amdgpu_ring_write(ring, control);
2612} 2607}
2613 2608
2609static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2610 struct amdgpu_ib *ib)
2611{
2612 u32 header, control = 0;
2613 u32 next_rptr = ring->wptr + 5;
2614
2615 control |= INDIRECT_BUFFER_VALID;
2616 next_rptr += 4;
2617 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2618 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2619 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2620 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2621 amdgpu_ring_write(ring, next_rptr);
2622
2623 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2624
2625 control |= ib->length_dw |
2626 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
2627
2628 amdgpu_ring_write(ring, header);
2629 amdgpu_ring_write(ring,
2630#ifdef __BIG_ENDIAN
2631 (2 << 0) |
2632#endif
2633 (ib->gpu_addr & 0xFFFFFFFC));
2634 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2635 amdgpu_ring_write(ring, control);
2636}
2637
2614/** 2638/**
2615 * gfx_v7_0_ring_test_ib - basic ring IB test 2639 * gfx_v7_0_ring_test_ib - basic ring IB test
2616 * 2640 *
@@ -3056,6 +3080,8 @@ static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3056 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3080 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3057 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3081 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3058 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); 3082 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
3083 adev->gfx.mec_feature_version = le32_to_cpu(
3084 mec_hdr->ucode_feature_version);
3059 3085
3060 gfx_v7_0_cp_compute_enable(adev, false); 3086 gfx_v7_0_cp_compute_enable(adev, false);
3061 3087
@@ -3078,6 +3104,8 @@ static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3078 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 3104 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3079 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header); 3105 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
3080 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); 3106 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
3107 adev->gfx.mec2_feature_version = le32_to_cpu(
3108 mec2_hdr->ucode_feature_version);
3081 3109
3082 /* MEC2 */ 3110 /* MEC2 */
3083 fw_data = (const __le32 *) 3111 fw_data = (const __le32 *)
@@ -4042,6 +4070,8 @@ static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
4042 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 4070 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
4043 amdgpu_ucode_print_rlc_hdr(&hdr->header); 4071 amdgpu_ucode_print_rlc_hdr(&hdr->header);
4044 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); 4072 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
4073 adev->gfx.rlc_feature_version = le32_to_cpu(
4074 hdr->ucode_feature_version);
4045 4075
4046 gfx_v7_0_rlc_stop(adev); 4076 gfx_v7_0_rlc_stop(adev);
4047 4077
@@ -5098,7 +5128,7 @@ static void gfx_v7_0_print_status(void *handle)
5098 dev_info(adev->dev, " CP_HPD_EOP_CONTROL=0x%08X\n", 5128 dev_info(adev->dev, " CP_HPD_EOP_CONTROL=0x%08X\n",
5099 RREG32(mmCP_HPD_EOP_CONTROL)); 5129 RREG32(mmCP_HPD_EOP_CONTROL));
5100 5130
5101 for (queue = 0; queue < 8; i++) { 5131 for (queue = 0; queue < 8; queue++) {
5102 cik_srbm_select(adev, me, pipe, queue, 0); 5132 cik_srbm_select(adev, me, pipe, queue, 0);
5103 dev_info(adev->dev, " queue: %d\n", queue); 5133 dev_info(adev->dev, " queue: %d\n", queue);
5104 dev_info(adev->dev, " CP_PQ_WPTR_POLL_CNTL=0x%08X\n", 5134 dev_info(adev->dev, " CP_PQ_WPTR_POLL_CNTL=0x%08X\n",
@@ -5555,7 +5585,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5555 .get_wptr = gfx_v7_0_ring_get_wptr_gfx, 5585 .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
5556 .set_wptr = gfx_v7_0_ring_set_wptr_gfx, 5586 .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
5557 .parse_cs = NULL, 5587 .parse_cs = NULL,
5558 .emit_ib = gfx_v7_0_ring_emit_ib, 5588 .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
5559 .emit_fence = gfx_v7_0_ring_emit_fence_gfx, 5589 .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
5560 .emit_semaphore = gfx_v7_0_ring_emit_semaphore, 5590 .emit_semaphore = gfx_v7_0_ring_emit_semaphore,
5561 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 5591 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
@@ -5571,7 +5601,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
5571 .get_wptr = gfx_v7_0_ring_get_wptr_compute, 5601 .get_wptr = gfx_v7_0_ring_get_wptr_compute,
5572 .set_wptr = gfx_v7_0_ring_set_wptr_compute, 5602 .set_wptr = gfx_v7_0_ring_set_wptr_compute,
5573 .parse_cs = NULL, 5603 .parse_cs = NULL,
5574 .emit_ib = gfx_v7_0_ring_emit_ib, 5604 .emit_ib = gfx_v7_0_ring_emit_ib_compute,
5575 .emit_fence = gfx_v7_0_ring_emit_fence_compute, 5605 .emit_fence = gfx_v7_0_ring_emit_fence_compute,
5576 .emit_semaphore = gfx_v7_0_ring_emit_semaphore, 5606 .emit_semaphore = gfx_v7_0_ring_emit_semaphore,
5577 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 5607 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 7b683fb2173c..20e2cfd521d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -587,6 +587,7 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
587 int err; 587 int err;
588 struct amdgpu_firmware_info *info = NULL; 588 struct amdgpu_firmware_info *info = NULL;
589 const struct common_firmware_header *header = NULL; 589 const struct common_firmware_header *header = NULL;
590 const struct gfx_firmware_header_v1_0 *cp_hdr;
590 591
591 DRM_DEBUG("\n"); 592 DRM_DEBUG("\n");
592 593
@@ -611,6 +612,9 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
611 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 612 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
612 if (err) 613 if (err)
613 goto out; 614 goto out;
615 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
616 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
617 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
614 618
615 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 619 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
616 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 620 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
@@ -619,6 +623,9 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
619 err = amdgpu_ucode_validate(adev->gfx.me_fw); 623 err = amdgpu_ucode_validate(adev->gfx.me_fw);
620 if (err) 624 if (err)
621 goto out; 625 goto out;
626 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
627 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
628 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
622 629
623 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 630 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
624 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 631 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
@@ -627,12 +634,18 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
627 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 634 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
628 if (err) 635 if (err)
629 goto out; 636 goto out;
637 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
638 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
639 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
630 640
631 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 641 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
632 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 642 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
633 if (err) 643 if (err)
634 goto out; 644 goto out;
635 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 645 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
646 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
647 adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
648 adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
636 649
637 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 650 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
638 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 651 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
@@ -641,6 +654,9 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
641 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 654 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
642 if (err) 655 if (err)
643 goto out; 656 goto out;
657 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
658 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
659 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
644 660
645 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 661 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
646 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 662 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
@@ -648,6 +664,12 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
648 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 664 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
649 if (err) 665 if (err)
650 goto out; 666 goto out;
667 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
668 adev->gfx.mec2_fw->data;
669 adev->gfx.mec2_fw_version = le32_to_cpu(
670 cp_hdr->header.ucode_version);
671 adev->gfx.mec2_feature_version = le32_to_cpu(
672 cp_hdr->ucode_feature_version);
651 } else { 673 } else {
652 err = 0; 674 err = 0;
653 adev->gfx.mec2_fw = NULL; 675 adev->gfx.mec2_fw = NULL;
@@ -1813,10 +1835,7 @@ static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev,
1813 u32 data, mask; 1835 u32 data, mask;
1814 1836
1815 data = RREG32(mmCC_RB_BACKEND_DISABLE); 1837 data = RREG32(mmCC_RB_BACKEND_DISABLE);
1816 if (data & 1) 1838 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1817 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1818 else
1819 data = 0;
1820 1839
1821 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1840 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1822 1841
@@ -1986,6 +2005,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
1986 adev->gfx.config.max_shader_engines = 1; 2005 adev->gfx.config.max_shader_engines = 1;
1987 adev->gfx.config.max_tile_pipes = 2; 2006 adev->gfx.config.max_tile_pipes = 2;
1988 adev->gfx.config.max_sh_per_se = 1; 2007 adev->gfx.config.max_sh_per_se = 1;
2008 adev->gfx.config.max_backends_per_se = 2;
1989 2009
1990 switch (adev->pdev->revision) { 2010 switch (adev->pdev->revision) {
1991 case 0xc4: 2011 case 0xc4:
@@ -1994,7 +2014,6 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
1994 case 0xcc: 2014 case 0xcc:
1995 /* B10 */ 2015 /* B10 */
1996 adev->gfx.config.max_cu_per_sh = 8; 2016 adev->gfx.config.max_cu_per_sh = 8;
1997 adev->gfx.config.max_backends_per_se = 2;
1998 break; 2017 break;
1999 case 0xc5: 2018 case 0xc5:
2000 case 0x81: 2019 case 0x81:
@@ -2003,14 +2022,12 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
2003 case 0xcd: 2022 case 0xcd:
2004 /* B8 */ 2023 /* B8 */
2005 adev->gfx.config.max_cu_per_sh = 6; 2024 adev->gfx.config.max_cu_per_sh = 6;
2006 adev->gfx.config.max_backends_per_se = 2;
2007 break; 2025 break;
2008 case 0xc6: 2026 case 0xc6:
2009 case 0xca: 2027 case 0xca:
2010 case 0xce: 2028 case 0xce:
2011 /* B6 */ 2029 /* B6 */
2012 adev->gfx.config.max_cu_per_sh = 6; 2030 adev->gfx.config.max_cu_per_sh = 6;
2013 adev->gfx.config.max_backends_per_se = 2;
2014 break; 2031 break;
2015 case 0xc7: 2032 case 0xc7:
2016 case 0x87: 2033 case 0x87:
@@ -2018,7 +2035,6 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
2018 default: 2035 default:
2019 /* B4 */ 2036 /* B4 */
2020 adev->gfx.config.max_cu_per_sh = 4; 2037 adev->gfx.config.max_cu_per_sh = 4;
2021 adev->gfx.config.max_backends_per_se = 1;
2022 break; 2038 break;
2023 } 2039 }
2024 2040
@@ -2278,7 +2294,6 @@ static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
2278 2294
2279 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2295 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2280 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2296 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2281 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
2282 2297
2283 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2298 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2284 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2299 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
@@ -2364,12 +2379,6 @@ static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2364 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2379 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2365 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2380 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2366 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2381 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2367 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2368 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2369 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2370 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2371 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2372 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2373 2382
2374 gfx_v8_0_cp_gfx_enable(adev, false); 2383 gfx_v8_0_cp_gfx_enable(adev, false);
2375 2384
@@ -2625,7 +2634,6 @@ static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2625 2634
2626 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2635 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2627 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2636 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2628 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2629 2637
2630 fw_data = (const __le32 *) 2638 fw_data = (const __le32 *)
2631 (adev->gfx.mec_fw->data + 2639 (adev->gfx.mec_fw->data +
@@ -2644,7 +2652,6 @@ static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2644 2652
2645 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2653 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2646 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header); 2654 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2647 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2648 2655
2649 fw_data = (const __le32 *) 2656 fw_data = (const __le32 *)
2650 (adev->gfx.mec2_fw->data + 2657 (adev->gfx.mec2_fw->data +
@@ -3128,7 +3135,7 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
3128 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, 3135 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
3129 AMDGPU_DOORBELL_KIQ << 2); 3136 AMDGPU_DOORBELL_KIQ << 2);
3130 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, 3137 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
3131 0x7FFFF << 2); 3138 AMDGPU_DOORBELL_MEC_RING7 << 2);
3132 } 3139 }
3133 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 3140 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3134 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3141 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
@@ -3756,7 +3763,7 @@ static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3756 amdgpu_ring_write(ring, 0x20); /* poll interval */ 3763 amdgpu_ring_write(ring, 0x20); /* poll interval */
3757} 3764}
3758 3765
3759static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring, 3766static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3760 struct amdgpu_ib *ib) 3767 struct amdgpu_ib *ib)
3761{ 3768{
3762 bool need_ctx_switch = ring->current_ctx != ib->ctx; 3769 bool need_ctx_switch = ring->current_ctx != ib->ctx;
@@ -3764,15 +3771,10 @@ static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring,
3764 u32 next_rptr = ring->wptr + 5; 3771 u32 next_rptr = ring->wptr + 5;
3765 3772
3766 /* drop the CE preamble IB for the same context */ 3773 /* drop the CE preamble IB for the same context */
3767 if ((ring->type == AMDGPU_RING_TYPE_GFX) && 3774 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
3768 (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
3769 !need_ctx_switch)
3770 return; 3775 return;
3771 3776
3772 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) 3777 if (need_ctx_switch)
3773 control |= INDIRECT_BUFFER_VALID;
3774
3775 if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX)
3776 next_rptr += 2; 3778 next_rptr += 2;
3777 3779
3778 next_rptr += 4; 3780 next_rptr += 4;
@@ -3783,7 +3785,7 @@ static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring,
3783 amdgpu_ring_write(ring, next_rptr); 3785 amdgpu_ring_write(ring, next_rptr);
3784 3786
3785 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 3787 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
3786 if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) { 3788 if (need_ctx_switch) {
3787 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3789 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3788 amdgpu_ring_write(ring, 0); 3790 amdgpu_ring_write(ring, 0);
3789 } 3791 }
@@ -3806,6 +3808,36 @@ static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring,
3806 amdgpu_ring_write(ring, control); 3808 amdgpu_ring_write(ring, control);
3807} 3809}
3808 3810
3811static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3812 struct amdgpu_ib *ib)
3813{
3814 u32 header, control = 0;
3815 u32 next_rptr = ring->wptr + 5;
3816
3817 control |= INDIRECT_BUFFER_VALID;
3818
3819 next_rptr += 4;
3820 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3821 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
3822 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3823 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3824 amdgpu_ring_write(ring, next_rptr);
3825
3826 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3827
3828 control |= ib->length_dw |
3829 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
3830
3831 amdgpu_ring_write(ring, header);
3832 amdgpu_ring_write(ring,
3833#ifdef __BIG_ENDIAN
3834 (2 << 0) |
3835#endif
3836 (ib->gpu_addr & 0xFFFFFFFC));
3837 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3838 amdgpu_ring_write(ring, control);
3839}
3840
3809static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, 3841static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
3810 u64 seq, unsigned flags) 3842 u64 seq, unsigned flags)
3811{ 3843{
@@ -4227,7 +4259,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
4227 .get_wptr = gfx_v8_0_ring_get_wptr_gfx, 4259 .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
4228 .set_wptr = gfx_v8_0_ring_set_wptr_gfx, 4260 .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
4229 .parse_cs = NULL, 4261 .parse_cs = NULL,
4230 .emit_ib = gfx_v8_0_ring_emit_ib, 4262 .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
4231 .emit_fence = gfx_v8_0_ring_emit_fence_gfx, 4263 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
4232 .emit_semaphore = gfx_v8_0_ring_emit_semaphore, 4264 .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4233 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, 4265 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
@@ -4243,7 +4275,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
4243 .get_wptr = gfx_v8_0_ring_get_wptr_compute, 4275 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
4244 .set_wptr = gfx_v8_0_ring_set_wptr_compute, 4276 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
4245 .parse_cs = NULL, 4277 .parse_cs = NULL,
4246 .emit_ib = gfx_v8_0_ring_emit_ib, 4278 .emit_ib = gfx_v8_0_ring_emit_ib_compute,
4247 .emit_fence = gfx_v8_0_ring_emit_fence_compute, 4279 .emit_fence = gfx_v8_0_ring_emit_fence_compute,
4248 .emit_semaphore = gfx_v8_0_ring_emit_semaphore, 4280 .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4249 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, 4281 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index d7895885fe0c..a988dfb1d394 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -121,6 +121,7 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
121 int err, i; 121 int err, i;
122 struct amdgpu_firmware_info *info = NULL; 122 struct amdgpu_firmware_info *info = NULL;
123 const struct common_firmware_header *header = NULL; 123 const struct common_firmware_header *header = NULL;
124 const struct sdma_firmware_header_v1_0 *hdr;
124 125
125 DRM_DEBUG("\n"); 126 DRM_DEBUG("\n");
126 127
@@ -142,6 +143,9 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
142 err = amdgpu_ucode_validate(adev->sdma[i].fw); 143 err = amdgpu_ucode_validate(adev->sdma[i].fw);
143 if (err) 144 if (err)
144 goto out; 145 goto out;
146 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
147 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
148 adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
145 149
146 if (adev->firmware.smu_load) { 150 if (adev->firmware.smu_load) {
147 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 151 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
@@ -541,8 +545,6 @@ static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
541 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data; 545 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
542 amdgpu_ucode_print_sdma_hdr(&hdr->header); 546 amdgpu_ucode_print_sdma_hdr(&hdr->header);
543 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 547 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
544 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
545
546 fw_data = (const __le32 *) 548 fw_data = (const __le32 *)
547 (adev->sdma[i].fw->data + 549 (adev->sdma[i].fw->data +
548 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 550 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 7bb37b93993f..2b86569b18d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -159,6 +159,7 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
159 int err, i; 159 int err, i;
160 struct amdgpu_firmware_info *info = NULL; 160 struct amdgpu_firmware_info *info = NULL;
161 const struct common_firmware_header *header = NULL; 161 const struct common_firmware_header *header = NULL;
162 const struct sdma_firmware_header_v1_0 *hdr;
162 163
163 DRM_DEBUG("\n"); 164 DRM_DEBUG("\n");
164 165
@@ -183,6 +184,9 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
183 err = amdgpu_ucode_validate(adev->sdma[i].fw); 184 err = amdgpu_ucode_validate(adev->sdma[i].fw);
184 if (err) 185 if (err)
185 goto out; 186 goto out;
187 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
188 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
189 adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
186 190
187 if (adev->firmware.smu_load) { 191 if (adev->firmware.smu_load) {
188 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 192 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
@@ -630,8 +634,6 @@ static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
630 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data; 634 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
631 amdgpu_ucode_print_sdma_hdr(&hdr->header); 635 amdgpu_ucode_print_sdma_hdr(&hdr->header);
632 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 636 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
633 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
634
635 fw_data = (const __le32 *) 637 fw_data = (const __le32 *)
636 (adev->sdma[i].fw->data + 638 (adev->sdma[i].fw->data +
637 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 639 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index d62c4002e39c..d1064ca3670e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -35,6 +35,8 @@
35#include "oss/oss_2_0_d.h" 35#include "oss/oss_2_0_d.h"
36#include "oss/oss_2_0_sh_mask.h" 36#include "oss/oss_2_0_sh_mask.h"
37#include "gca/gfx_8_0_d.h" 37#include "gca/gfx_8_0_d.h"
38#include "smu/smu_7_1_2_d.h"
39#include "smu/smu_7_1_2_sh_mask.h"
38 40
39#define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04 41#define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04
40#define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10 42#define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10
@@ -112,6 +114,10 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
112 114
113 mutex_lock(&adev->grbm_idx_mutex); 115 mutex_lock(&adev->grbm_idx_mutex);
114 for (idx = 0; idx < 2; ++idx) { 116 for (idx = 0; idx < 2; ++idx) {
117
118 if (adev->vce.harvest_config & (1 << idx))
119 continue;
120
115 if(idx == 0) 121 if(idx == 0)
116 WREG32_P(mmGRBM_GFX_INDEX, 0, 122 WREG32_P(mmGRBM_GFX_INDEX, 0,
117 ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK); 123 ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
@@ -190,10 +196,52 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
190 return 0; 196 return 0;
191} 197}
192 198
199#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074
200#define VCE_HARVEST_FUSE_MACRO__SHIFT 27
201#define VCE_HARVEST_FUSE_MACRO__MASK 0x18000000
202
203static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
204{
205 u32 tmp;
206 unsigned ret;
207
208 if (adev->flags & AMDGPU_IS_APU)
209 tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) &
210 VCE_HARVEST_FUSE_MACRO__MASK) >>
211 VCE_HARVEST_FUSE_MACRO__SHIFT;
212 else
213 tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) &
214 CC_HARVEST_FUSES__VCE_DISABLE_MASK) >>
215 CC_HARVEST_FUSES__VCE_DISABLE__SHIFT;
216
217 switch (tmp) {
218 case 1:
219 ret = AMDGPU_VCE_HARVEST_VCE0;
220 break;
221 case 2:
222 ret = AMDGPU_VCE_HARVEST_VCE1;
223 break;
224 case 3:
225 ret = AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1;
226 break;
227 default:
228 ret = 0;
229 }
230
231 return ret;
232}
233
193static int vce_v3_0_early_init(void *handle) 234static int vce_v3_0_early_init(void *handle)
194{ 235{
195 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 236 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
196 237
238 adev->vce.harvest_config = vce_v3_0_get_harvest_config(adev);
239
240 if ((adev->vce.harvest_config &
241 (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1)) ==
242 (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1))
243 return -ENOENT;
244
197 vce_v3_0_set_ring_funcs(adev); 245 vce_v3_0_set_ring_funcs(adev);
198 vce_v3_0_set_irq_funcs(adev); 246 vce_v3_0_set_irq_funcs(adev);
199 247
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index fa5a4448531d..68552da40287 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -122,6 +122,32 @@ static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
122 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 122 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
123} 123}
124 124
125/* smu_8_0_d.h */
126#define mmMP0PUB_IND_INDEX 0x180
127#define mmMP0PUB_IND_DATA 0x181
128
129static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
130{
131 unsigned long flags;
132 u32 r;
133
134 spin_lock_irqsave(&adev->smc_idx_lock, flags);
135 WREG32(mmMP0PUB_IND_INDEX, (reg));
136 r = RREG32(mmMP0PUB_IND_DATA);
137 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
138 return r;
139}
140
141static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
142{
143 unsigned long flags;
144
145 spin_lock_irqsave(&adev->smc_idx_lock, flags);
146 WREG32(mmMP0PUB_IND_INDEX, (reg));
147 WREG32(mmMP0PUB_IND_DATA, (v));
148 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
149}
150
125static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 151static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
126{ 152{
127 unsigned long flags; 153 unsigned long flags;
@@ -1222,8 +1248,13 @@ static int vi_common_early_init(void *handle)
1222 bool smc_enabled = false; 1248 bool smc_enabled = false;
1223 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1249 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1224 1250
1225 adev->smc_rreg = &vi_smc_rreg; 1251 if (adev->flags & AMDGPU_IS_APU) {
1226 adev->smc_wreg = &vi_smc_wreg; 1252 adev->smc_rreg = &cz_smc_rreg;
1253 adev->smc_wreg = &cz_smc_wreg;
1254 } else {
1255 adev->smc_rreg = &vi_smc_rreg;
1256 adev->smc_wreg = &vi_smc_wreg;
1257 }
1227 adev->pcie_rreg = &vi_pcie_rreg; 1258 adev->pcie_rreg = &vi_pcie_rreg;
1228 adev->pcie_wreg = &vi_pcie_wreg; 1259 adev->pcie_wreg = &vi_pcie_wreg;
1229 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg; 1260 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 8a1f999daa24..9be007081b72 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -420,6 +420,12 @@ void kfd_unbind_process_from_device(struct kfd_dev *dev, unsigned int pasid)
420 pqm_uninit(&p->pqm); 420 pqm_uninit(&p->pqm);
421 421
422 pdd = kfd_get_process_device_data(dev, p); 422 pdd = kfd_get_process_device_data(dev, p);
423
424 if (!pdd) {
425 mutex_unlock(&p->mutex);
426 return;
427 }
428
423 if (pdd->reset_wavefronts) { 429 if (pdd->reset_wavefronts) {
424 dbgdev_wave_reset_wavefronts(pdd->dev, p); 430 dbgdev_wave_reset_wavefronts(pdd->dev, p);
425 pdd->reset_wavefronts = false; 431 pdd->reset_wavefronts = false;
@@ -431,8 +437,7 @@ void kfd_unbind_process_from_device(struct kfd_dev *dev, unsigned int pasid)
431 * We don't call amd_iommu_unbind_pasid() here 437 * We don't call amd_iommu_unbind_pasid() here
432 * because the IOMMU called us. 438 * because the IOMMU called us.
433 */ 439 */
434 if (pdd) 440 pdd->bound = false;
435 pdd->bound = false;
436 441
437 mutex_unlock(&p->mutex); 442 mutex_unlock(&p->mutex);
438} 443}
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-06 20:15:23 -0500