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-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c36
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_display.c7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c14
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c44
-rw-r--r--drivers/gpu/drm/amd/amdgpu/soc15.c39
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c3
-rw-r--r--drivers/gpu/drm/amd/amdkfd/kfd_device.c7
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c24
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h1
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c5
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c2
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c4
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c3
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c2
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c32
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c37
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c23
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c86
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu7_ppsmc.h2
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c6
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c3
30 files changed, 288 insertions, 129 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 104b2e0d893b..b0fc116296cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -233,7 +233,7 @@ enum amdgpu_kiq_irq {
233 233
234#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 234#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
235#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 235#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
236#define MAX_KIQ_REG_TRY 20 236#define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */
237 237
238int amdgpu_device_ip_set_clockgating_state(void *dev, 238int amdgpu_device_ip_set_clockgating_state(void *dev,
239 enum amd_ip_block_type block_type, 239 enum amd_ip_block_type block_type,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index c31a8849e9f8..1580ec60b89f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -501,8 +501,11 @@ void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
501{ 501{
502 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 502 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
503 503
504 amdgpu_dpm_switch_power_profile(adev, 504 if (adev->powerplay.pp_funcs &&
505 PP_SMC_POWER_PROFILE_COMPUTE, !idle); 505 adev->powerplay.pp_funcs->switch_power_profile)
506 amdgpu_dpm_switch_power_profile(adev,
507 PP_SMC_POWER_PROFILE_COMPUTE,
508 !idle);
506} 509}
507 510
508bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) 511bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 8816c697b205..387f1cf1dc20 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -330,7 +330,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
330 case CHIP_TOPAZ: 330 case CHIP_TOPAZ:
331 if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) || 331 if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) ||
332 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) || 332 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) ||
333 ((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87))) { 333 ((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87)) ||
334 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0xD1)) ||
335 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0xD3))) {
334 info->is_kicker = true; 336 info->is_kicker = true;
335 strcpy(fw_name, "amdgpu/topaz_k_smc.bin"); 337 strcpy(fw_name, "amdgpu/topaz_k_smc.bin");
336 } else 338 } else
@@ -351,7 +353,6 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
351 if (type == CGS_UCODE_ID_SMU) { 353 if (type == CGS_UCODE_ID_SMU) {
352 if (((adev->pdev->device == 0x67ef) && 354 if (((adev->pdev->device == 0x67ef) &&
353 ((adev->pdev->revision == 0xe0) || 355 ((adev->pdev->revision == 0xe0) ||
354 (adev->pdev->revision == 0xe2) ||
355 (adev->pdev->revision == 0xe5))) || 356 (adev->pdev->revision == 0xe5))) ||
356 ((adev->pdev->device == 0x67ff) && 357 ((adev->pdev->device == 0x67ff) &&
357 ((adev->pdev->revision == 0xcf) || 358 ((adev->pdev->revision == 0xcf) ||
@@ -359,8 +360,13 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
359 (adev->pdev->revision == 0xff)))) { 360 (adev->pdev->revision == 0xff)))) {
360 info->is_kicker = true; 361 info->is_kicker = true;
361 strcpy(fw_name, "amdgpu/polaris11_k_smc.bin"); 362 strcpy(fw_name, "amdgpu/polaris11_k_smc.bin");
362 } else 363 } else if ((adev->pdev->device == 0x67ef) &&
364 (adev->pdev->revision == 0xe2)) {
365 info->is_kicker = true;
366 strcpy(fw_name, "amdgpu/polaris11_k2_smc.bin");
367 } else {
363 strcpy(fw_name, "amdgpu/polaris11_smc.bin"); 368 strcpy(fw_name, "amdgpu/polaris11_smc.bin");
369 }
364 } else if (type == CGS_UCODE_ID_SMU_SK) { 370 } else if (type == CGS_UCODE_ID_SMU_SK) {
365 strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin"); 371 strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
366 } 372 }
@@ -375,17 +381,35 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
375 (adev->pdev->revision == 0xe7) || 381 (adev->pdev->revision == 0xe7) ||
376 (adev->pdev->revision == 0xef))) || 382 (adev->pdev->revision == 0xef))) ||
377 ((adev->pdev->device == 0x6fdf) && 383 ((adev->pdev->device == 0x6fdf) &&
378 (adev->pdev->revision == 0xef))) { 384 ((adev->pdev->revision == 0xef) ||
385 (adev->pdev->revision == 0xff)))) {
379 info->is_kicker = true; 386 info->is_kicker = true;
380 strcpy(fw_name, "amdgpu/polaris10_k_smc.bin"); 387 strcpy(fw_name, "amdgpu/polaris10_k_smc.bin");
381 } else 388 } else if ((adev->pdev->device == 0x67df) &&
389 ((adev->pdev->revision == 0xe1) ||
390 (adev->pdev->revision == 0xf7))) {
391 info->is_kicker = true;
392 strcpy(fw_name, "amdgpu/polaris10_k2_smc.bin");
393 } else {
382 strcpy(fw_name, "amdgpu/polaris10_smc.bin"); 394 strcpy(fw_name, "amdgpu/polaris10_smc.bin");
395 }
383 } else if (type == CGS_UCODE_ID_SMU_SK) { 396 } else if (type == CGS_UCODE_ID_SMU_SK) {
384 strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin"); 397 strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
385 } 398 }
386 break; 399 break;
387 case CHIP_POLARIS12: 400 case CHIP_POLARIS12:
388 strcpy(fw_name, "amdgpu/polaris12_smc.bin"); 401 if (((adev->pdev->device == 0x6987) &&
402 ((adev->pdev->revision == 0xc0) ||
403 (adev->pdev->revision == 0xc3))) ||
404 ((adev->pdev->device == 0x6981) &&
405 ((adev->pdev->revision == 0x00) ||
406 (adev->pdev->revision == 0x01) ||
407 (adev->pdev->revision == 0x10)))) {
408 info->is_kicker = true;
409 strcpy(fw_name, "amdgpu/polaris12_k_smc.bin");
410 } else {
411 strcpy(fw_name, "amdgpu/polaris12_smc.bin");
412 }
389 break; 413 break;
390 case CHIP_VEGAM: 414 case CHIP_VEGAM:
391 strcpy(fw_name, "amdgpu/vegam_smc.bin"); 415 strcpy(fw_name, "amdgpu/vegam_smc.bin");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 663043c8f0f5..0acc8dee2cb8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -124,14 +124,14 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs
124 goto free_chunk; 124 goto free_chunk;
125 } 125 }
126 126
127 mutex_lock(&p->ctx->lock);
128
127 /* skip guilty context job */ 129 /* skip guilty context job */
128 if (atomic_read(&p->ctx->guilty) == 1) { 130 if (atomic_read(&p->ctx->guilty) == 1) {
129 ret = -ECANCELED; 131 ret = -ECANCELED;
130 goto free_chunk; 132 goto free_chunk;
131 } 133 }
132 134
133 mutex_lock(&p->ctx->lock);
134
135 /* get chunks */ 135 /* get chunks */
136 chunk_array_user = u64_to_user_ptr(cs->in.chunks); 136 chunk_array_user = u64_to_user_ptr(cs->in.chunks);
137 if (copy_from_user(chunk_array, chunk_array_user, 137 if (copy_from_user(chunk_array, chunk_array_user,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index f9b54236102d..95f4c4139fc6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -39,6 +39,7 @@ const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM] = {
39 [AMDGPU_HW_IP_UVD_ENC] = 1, 39 [AMDGPU_HW_IP_UVD_ENC] = 1,
40 [AMDGPU_HW_IP_VCN_DEC] = 1, 40 [AMDGPU_HW_IP_VCN_DEC] = 1,
41 [AMDGPU_HW_IP_VCN_ENC] = 1, 41 [AMDGPU_HW_IP_VCN_ENC] = 1,
42 [AMDGPU_HW_IP_VCN_JPEG] = 1,
42}; 43};
43 44
44static int amdgput_ctx_total_num_entities(void) 45static int amdgput_ctx_total_num_entities(void)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 6748cd7fc129..686a26de50f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -626,6 +626,13 @@ int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
626 "dither", 626 "dither",
627 amdgpu_dither_enum_list, sz); 627 amdgpu_dither_enum_list, sz);
628 628
629 if (amdgpu_device_has_dc_support(adev)) {
630 adev->mode_info.max_bpc_property =
631 drm_property_create_range(adev->ddev, 0, "max bpc", 8, 16);
632 if (!adev->mode_info.max_bpc_property)
633 return -ENOMEM;
634 }
635
629 return 0; 636 return 0;
630} 637}
631 638
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 8de55f7f1a3a..74b611e8a1b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -872,7 +872,13 @@ static const struct pci_device_id pciidlist[] = {
872 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 872 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
873 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 873 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
874 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 874 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
875 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
876 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
877 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
875 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 878 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
879 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
880 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
881 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
876 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 882 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
877 /* Vega 12 */ 883 /* Vega 12 */
878 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 884 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
@@ -885,6 +891,7 @@ static const struct pci_device_id pciidlist[] = {
885 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 891 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
886 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 892 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
887 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 893 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
894 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
888 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 895 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
889 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 896 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
890 /* Raven */ 897 /* Raven */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 81732a84c2ab..8f3d44e5e787 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -467,9 +467,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
467 if (!info->return_size || !info->return_pointer) 467 if (!info->return_size || !info->return_pointer)
468 return -EINVAL; 468 return -EINVAL;
469 469
470 /* Ensure IB tests are run on ring */
471 flush_delayed_work(&adev->late_init_work);
472
473 switch (info->query) { 470 switch (info->query) {
474 case AMDGPU_INFO_ACCEL_WORKING: 471 case AMDGPU_INFO_ACCEL_WORKING:
475 ui32 = adev->accel_working; 472 ui32 = adev->accel_working;
@@ -950,6 +947,9 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
950 struct amdgpu_fpriv *fpriv; 947 struct amdgpu_fpriv *fpriv;
951 int r, pasid; 948 int r, pasid;
952 949
950 /* Ensure IB tests are run on ring */
951 flush_delayed_work(&adev->late_init_work);
952
953 file_priv->driver_priv = NULL; 953 file_priv->driver_priv = NULL;
954 954
955 r = pm_runtime_get_sync(dev->dev); 955 r = pm_runtime_get_sync(dev->dev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index b9e9e8b02fb7..d1b4d9b6aae0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -339,6 +339,8 @@ struct amdgpu_mode_info {
339 struct drm_property *audio_property; 339 struct drm_property *audio_property;
340 /* FMT dithering */ 340 /* FMT dithering */
341 struct drm_property *dither_property; 341 struct drm_property *dither_property;
342 /* maximum number of bits per channel for monitor color */
343 struct drm_property *max_bpc_property;
342 /* hardcoded DFP edid from BIOS */ 344 /* hardcoded DFP edid from BIOS */
343 struct edid *bios_hardcoded_edid; 345 struct edid *bios_hardcoded_edid;
344 int bios_hardcoded_edid_size; 346 int bios_hardcoded_edid_size;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index dad0e2342df9..0877ff9a9594 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -181,7 +181,7 @@ static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
181 181
182 if (level == adev->vm_manager.root_level) 182 if (level == adev->vm_manager.root_level)
183 /* For the root directory */ 183 /* For the root directory */
184 return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift; 184 return round_up(adev->vm_manager.max_pfn, 1ULL << shift) >> shift;
185 else if (level != AMDGPU_VM_PTB) 185 else if (level != AMDGPU_VM_PTB)
186 /* Everything in between */ 186 /* Everything in between */
187 return 512; 187 return 512;
@@ -1656,9 +1656,11 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
1656 if (!amdgpu_vm_pt_descendant(adev, &cursor)) 1656 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1657 return -ENOENT; 1657 return -ENOENT;
1658 continue; 1658 continue;
1659 } else if (frag >= parent_shift) { 1659 } else if (frag >= parent_shift &&
1660 cursor.level - 1 != adev->vm_manager.root_level) {
1660 /* If the fragment size is even larger than the parent 1661 /* If the fragment size is even larger than the parent
1661 * shift we should go up one level and check it again. 1662 * shift we should go up one level and check it again
1663 * unless one level up is the root level.
1662 */ 1664 */
1663 if (!amdgpu_vm_pt_ancestor(&cursor)) 1665 if (!amdgpu_vm_pt_ancestor(&cursor))
1664 return -ENOENT; 1666 return -ENOENT;
@@ -1666,10 +1668,10 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
1666 } 1668 }
1667 1669
1668 /* Looks good so far, calculate parameters for the update */ 1670 /* Looks good so far, calculate parameters for the update */
1669 incr = AMDGPU_GPU_PAGE_SIZE << shift; 1671 incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
1670 mask = amdgpu_vm_entries_mask(adev, cursor.level); 1672 mask = amdgpu_vm_entries_mask(adev, cursor.level);
1671 pe_start = ((cursor.pfn >> shift) & mask) * 8; 1673 pe_start = ((cursor.pfn >> shift) & mask) * 8;
1672 entry_end = (mask + 1) << shift; 1674 entry_end = (uint64_t)(mask + 1) << shift;
1673 entry_end += cursor.pfn & ~(entry_end - 1); 1675 entry_end += cursor.pfn & ~(entry_end - 1);
1674 entry_end = min(entry_end, end); 1676 entry_end = min(entry_end, end);
1675 1677
@@ -1682,7 +1684,7 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
1682 flags | AMDGPU_PTE_FRAG(frag)); 1684 flags | AMDGPU_PTE_FRAG(frag));
1683 1685
1684 pe_start += nptes * 8; 1686 pe_start += nptes * 8;
1685 dst += nptes * AMDGPU_GPU_PAGE_SIZE << shift; 1687 dst += (uint64_t)nptes * AMDGPU_GPU_PAGE_SIZE << shift;
1686 1688
1687 frag_start = upd_end; 1689 frag_start = upd_end;
1688 if (frag_start >= frag_end) { 1690 if (frag_start >= frag_end) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 6d7baf59d6e1..21363b2b2ee5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2440,12 +2440,13 @@ static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2440#endif 2440#endif
2441 2441
2442 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2442 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
2443 udelay(50);
2443 2444
2444 /* carrizo do enable cp interrupt after cp inited */ 2445 /* carrizo do enable cp interrupt after cp inited */
2445 if (!(adev->flags & AMD_IS_APU)) 2446 if (!(adev->flags & AMD_IS_APU)) {
2446 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 2447 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2447 2448 udelay(50);
2448 udelay(50); 2449 }
2449 2450
2450#ifdef AMDGPU_RLC_DEBUG_RETRY 2451#ifdef AMDGPU_RLC_DEBUG_RETRY
2451 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 2452 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index e1c2b4e9c7b2..73ad02aea2b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -46,6 +46,7 @@ MODULE_FIRMWARE("amdgpu/tahiti_mc.bin");
46MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin"); 46MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin");
47MODULE_FIRMWARE("amdgpu/verde_mc.bin"); 47MODULE_FIRMWARE("amdgpu/verde_mc.bin");
48MODULE_FIRMWARE("amdgpu/oland_mc.bin"); 48MODULE_FIRMWARE("amdgpu/oland_mc.bin");
49MODULE_FIRMWARE("amdgpu/hainan_mc.bin");
49MODULE_FIRMWARE("amdgpu/si58_mc.bin"); 50MODULE_FIRMWARE("amdgpu/si58_mc.bin");
50 51
51#define MC_SEQ_MISC0__MT__MASK 0xf0000000 52#define MC_SEQ_MISC0__MT__MASK 0xf0000000
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 1d3265c97b70..747c068379dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -56,6 +56,9 @@ MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
56MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); 56MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
57MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); 57MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
58MODULE_FIRMWARE("amdgpu/polaris12_mc.bin"); 58MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
59MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin");
60MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin");
61MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin");
59 62
60static const u32 golden_settings_tonga_a11[] = 63static const u32 golden_settings_tonga_a11[] =
61{ 64{
@@ -224,13 +227,39 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
224 chip_name = "tonga"; 227 chip_name = "tonga";
225 break; 228 break;
226 case CHIP_POLARIS11: 229 case CHIP_POLARIS11:
227 chip_name = "polaris11"; 230 if (((adev->pdev->device == 0x67ef) &&
231 ((adev->pdev->revision == 0xe0) ||
232 (adev->pdev->revision == 0xe5))) ||
233 ((adev->pdev->device == 0x67ff) &&
234 ((adev->pdev->revision == 0xcf) ||
235 (adev->pdev->revision == 0xef) ||
236 (adev->pdev->revision == 0xff))))
237 chip_name = "polaris11_k";
238 else if ((adev->pdev->device == 0x67ef) &&
239 (adev->pdev->revision == 0xe2))
240 chip_name = "polaris11_k";
241 else
242 chip_name = "polaris11";
228 break; 243 break;
229 case CHIP_POLARIS10: 244 case CHIP_POLARIS10:
230 chip_name = "polaris10"; 245 if ((adev->pdev->device == 0x67df) &&
246 ((adev->pdev->revision == 0xe1) ||
247 (adev->pdev->revision == 0xf7)))
248 chip_name = "polaris10_k";
249 else
250 chip_name = "polaris10";
231 break; 251 break;
232 case CHIP_POLARIS12: 252 case CHIP_POLARIS12:
233 chip_name = "polaris12"; 253 if (((adev->pdev->device == 0x6987) &&
254 ((adev->pdev->revision == 0xc0) ||
255 (adev->pdev->revision == 0xc3))) ||
256 ((adev->pdev->device == 0x6981) &&
257 ((adev->pdev->revision == 0x00) ||
258 (adev->pdev->revision == 0x01) ||
259 (adev->pdev->revision == 0x10))))
260 chip_name = "polaris12_k";
261 else
262 chip_name = "polaris12";
234 break; 263 break;
235 case CHIP_FIJI: 264 case CHIP_FIJI:
236 case CHIP_CARRIZO: 265 case CHIP_CARRIZO:
@@ -337,7 +366,7 @@ static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
337 const struct mc_firmware_header_v1_0 *hdr; 366 const struct mc_firmware_header_v1_0 *hdr;
338 const __le32 *fw_data = NULL; 367 const __le32 *fw_data = NULL;
339 const __le32 *io_mc_regs = NULL; 368 const __le32 *io_mc_regs = NULL;
340 u32 data, vbios_version; 369 u32 data;
341 int i, ucode_size, regs_size; 370 int i, ucode_size, regs_size;
342 371
343 /* Skip MC ucode loading on SR-IOV capable boards. 372 /* Skip MC ucode loading on SR-IOV capable boards.
@@ -348,13 +377,6 @@ static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
348 if (amdgpu_sriov_bios(adev)) 377 if (amdgpu_sriov_bios(adev))
349 return 0; 378 return 0;
350 379
351 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
352 data = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
353 vbios_version = data & 0xf;
354
355 if (vbios_version == 0)
356 return 0;
357
358 if (!adev->gmc.fw) 380 if (!adev->gmc.fw)
359 return -EINVAL; 381 return -EINVAL;
360 382
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index bf5e6a413dee..4cc0dcb1a187 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -65,6 +65,13 @@
65#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 65#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
66#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 66#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
67 67
68/* for Vega20 register name change */
69#define mmHDP_MEM_POWER_CTRL 0x00d4
70#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
71#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
72#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
73#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
74#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
68/* 75/*
69 * Indirect registers accessor 76 * Indirect registers accessor
70 */ 77 */
@@ -870,15 +877,33 @@ static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable
870{ 877{
871 uint32_t def, data; 878 uint32_t def, data;
872 879
873 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 880 if (adev->asic_type == CHIP_VEGA20) {
881 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
874 882
875 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 883 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
876 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; 884 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
877 else 885 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
878 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; 886 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
887 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
888 else
889 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
890 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
891 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
892 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
879 893
880 if (def != data) 894 if (def != data)
881 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); 895 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
896 } else {
897 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
898
899 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
900 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
901 else
902 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
903
904 if (def != data)
905 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
906 }
882} 907}
883 908
884static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 909static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index eae90922fdbe..322e09b5b448 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -48,6 +48,7 @@ static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
48static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev); 48static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
49static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev); 49static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
50static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr); 50static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr);
51static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state);
51 52
52/** 53/**
53 * vcn_v1_0_early_init - set function pointers 54 * vcn_v1_0_early_init - set function pointers
@@ -222,7 +223,7 @@ static int vcn_v1_0_hw_fini(void *handle)
222 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 223 struct amdgpu_ring *ring = &adev->vcn.ring_dec;
223 224
224 if (RREG32_SOC15(VCN, 0, mmUVD_STATUS)) 225 if (RREG32_SOC15(VCN, 0, mmUVD_STATUS))
225 vcn_v1_0_stop(adev); 226 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
226 227
227 ring->ready = false; 228 ring->ready = false;
228 229
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index a9f18ea7e354..e4ded890b1cb 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -337,12 +337,19 @@ static const struct kfd_deviceid supported_devices[] = {
337 { 0x6864, &vega10_device_info }, /* Vega10 */ 337 { 0x6864, &vega10_device_info }, /* Vega10 */
338 { 0x6867, &vega10_device_info }, /* Vega10 */ 338 { 0x6867, &vega10_device_info }, /* Vega10 */
339 { 0x6868, &vega10_device_info }, /* Vega10 */ 339 { 0x6868, &vega10_device_info }, /* Vega10 */
340 { 0x6869, &vega10_device_info }, /* Vega10 */
341 { 0x686A, &vega10_device_info }, /* Vega10 */
342 { 0x686B, &vega10_device_info }, /* Vega10 */
340 { 0x686C, &vega10_vf_device_info }, /* Vega10 vf*/ 343 { 0x686C, &vega10_vf_device_info }, /* Vega10 vf*/
344 { 0x686D, &vega10_device_info }, /* Vega10 */
345 { 0x686E, &vega10_device_info }, /* Vega10 */
346 { 0x686F, &vega10_device_info }, /* Vega10 */
341 { 0x687F, &vega10_device_info }, /* Vega10 */ 347 { 0x687F, &vega10_device_info }, /* Vega10 */
342 { 0x66a0, &vega20_device_info }, /* Vega20 */ 348 { 0x66a0, &vega20_device_info }, /* Vega20 */
343 { 0x66a1, &vega20_device_info }, /* Vega20 */ 349 { 0x66a1, &vega20_device_info }, /* Vega20 */
344 { 0x66a2, &vega20_device_info }, /* Vega20 */ 350 { 0x66a2, &vega20_device_info }, /* Vega20 */
345 { 0x66a3, &vega20_device_info }, /* Vega20 */ 351 { 0x66a3, &vega20_device_info }, /* Vega20 */
352 { 0x66a4, &vega20_device_info }, /* Vega20 */
346 { 0x66a7, &vega20_device_info }, /* Vega20 */ 353 { 0x66a7, &vega20_device_info }, /* Vega20 */
347 { 0x66af, &vega20_device_info } /* Vega20 */ 354 { 0x66af, &vega20_device_info } /* Vega20 */
348}; 355};
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index c1262f62cd9f..5a6edf65c9ea 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2358,8 +2358,15 @@ static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2358static enum dc_color_depth 2358static enum dc_color_depth
2359convert_color_depth_from_display_info(const struct drm_connector *connector) 2359convert_color_depth_from_display_info(const struct drm_connector *connector)
2360{ 2360{
2361 struct dm_connector_state *dm_conn_state =
2362 to_dm_connector_state(connector->state);
2361 uint32_t bpc = connector->display_info.bpc; 2363 uint32_t bpc = connector->display_info.bpc;
2362 2364
2365 /* TODO: Remove this when there's support for max_bpc in drm */
2366 if (dm_conn_state && bpc > dm_conn_state->max_bpc)
2367 /* Round down to nearest even number. */
2368 bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1);
2369
2363 switch (bpc) { 2370 switch (bpc) {
2364 case 0: 2371 case 0:
2365 /* 2372 /*
@@ -2547,9 +2554,9 @@ static void fill_audio_info(struct audio_info *audio_info,
2547 2554
2548 cea_revision = drm_connector->display_info.cea_rev; 2555 cea_revision = drm_connector->display_info.cea_rev;
2549 2556
2550 strncpy(audio_info->display_name, 2557 strscpy(audio_info->display_name,
2551 edid_caps->display_name, 2558 edid_caps->display_name,
2552 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1); 2559 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
2553 2560
2554 if (cea_revision >= 3) { 2561 if (cea_revision >= 3) {
2555 audio_info->mode_count = edid_caps->audio_mode_count; 2562 audio_info->mode_count = edid_caps->audio_mode_count;
@@ -2943,6 +2950,9 @@ int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2943 } else if (property == adev->mode_info.underscan_property) { 2950 } else if (property == adev->mode_info.underscan_property) {
2944 dm_new_state->underscan_enable = val; 2951 dm_new_state->underscan_enable = val;
2945 ret = 0; 2952 ret = 0;
2953 } else if (property == adev->mode_info.max_bpc_property) {
2954 dm_new_state->max_bpc = val;
2955 ret = 0;
2946 } 2956 }
2947 2957
2948 return ret; 2958 return ret;
@@ -2985,6 +2995,9 @@ int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2985 } else if (property == adev->mode_info.underscan_property) { 2995 } else if (property == adev->mode_info.underscan_property) {
2986 *val = dm_state->underscan_enable; 2996 *val = dm_state->underscan_enable;
2987 ret = 0; 2997 ret = 0;
2998 } else if (property == adev->mode_info.max_bpc_property) {
2999 *val = dm_state->max_bpc;
3000 ret = 0;
2988 } 3001 }
2989 return ret; 3002 return ret;
2990} 3003}
@@ -3029,6 +3042,7 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
3029 state->underscan_enable = false; 3042 state->underscan_enable = false;
3030 state->underscan_hborder = 0; 3043 state->underscan_hborder = 0;
3031 state->underscan_vborder = 0; 3044 state->underscan_vborder = 0;
3045 state->max_bpc = 8;
3032 3046
3033 __drm_atomic_helper_connector_reset(connector, &state->base); 3047 __drm_atomic_helper_connector_reset(connector, &state->base);
3034 } 3048 }
@@ -3050,6 +3064,7 @@ amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
3050 3064
3051 new_state->freesync_capable = state->freesync_capable; 3065 new_state->freesync_capable = state->freesync_capable;
3052 new_state->freesync_enable = state->freesync_enable; 3066 new_state->freesync_enable = state->freesync_enable;
3067 new_state->max_bpc = state->max_bpc;
3053 3068
3054 return &new_state->base; 3069 return &new_state->base;
3055} 3070}
@@ -3637,7 +3652,7 @@ amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3637 mode->hdisplay = hdisplay; 3652 mode->hdisplay = hdisplay;
3638 mode->vdisplay = vdisplay; 3653 mode->vdisplay = vdisplay;
3639 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 3654 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3640 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 3655 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3641 3656
3642 return mode; 3657 return mode;
3643 3658
@@ -3795,6 +3810,9 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3795 drm_object_attach_property(&aconnector->base.base, 3810 drm_object_attach_property(&aconnector->base.base,
3796 adev->mode_info.underscan_vborder_property, 3811 adev->mode_info.underscan_vborder_property,
3797 0); 3812 0);
3813 drm_object_attach_property(&aconnector->base.base,
3814 adev->mode_info.max_bpc_property,
3815 0);
3798 3816
3799} 3817}
3800 3818
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 924a38a1fc44..6e069d777ab2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -204,6 +204,7 @@ struct dm_connector_state {
204 enum amdgpu_rmx_type scaling; 204 enum amdgpu_rmx_type scaling;
205 uint8_t underscan_vborder; 205 uint8_t underscan_vborder;
206 uint8_t underscan_hborder; 206 uint8_t underscan_hborder;
207 uint8_t max_bpc;
207 bool underscan_enable; 208 bool underscan_enable;
208 bool freesync_enable; 209 bool freesync_enable;
209 bool freesync_capable; 210 bool freesync_capable;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index d02c32a1039c..1b0d209d8367 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -342,10 +342,9 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
342 master->connector_id); 342 master->connector_id);
343 343
344 aconnector->mst_encoder = dm_dp_create_fake_mst_encoder(master); 344 aconnector->mst_encoder = dm_dp_create_fake_mst_encoder(master);
345 drm_connector_attach_encoder(&aconnector->base,
346 &aconnector->mst_encoder->base);
345 347
346 /*
347 * TODO: understand why this one is needed
348 */
349 drm_object_attach_property( 348 drm_object_attach_property(
350 &connector->base, 349 &connector->base,
351 dev->mode_config.path_property, 350 dev->mode_config.path_property,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index b459867a05b2..a6bcb90e8419 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2512,6 +2512,8 @@ static void pplib_apply_display_requirements(
2512 dc, 2512 dc,
2513 context->bw.dce.sclk_khz); 2513 context->bw.dce.sclk_khz);
2514 2514
2515 pp_display_cfg->min_dcfclock_khz = pp_display_cfg->min_engine_clock_khz;
2516
2515 pp_display_cfg->min_engine_clock_deep_sleep_khz 2517 pp_display_cfg->min_engine_clock_deep_sleep_khz
2516 = context->bw.dce.sclk_deep_sleep_khz; 2518 = context->bw.dce.sclk_deep_sleep_khz;
2517 2519
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index 85119c2bdcc8..a2a7e0e94aa6 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -80,7 +80,9 @@ int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
80 PHM_FUNC_CHECK(hwmgr); 80 PHM_FUNC_CHECK(hwmgr);
81 adev = hwmgr->adev; 81 adev = hwmgr->adev;
82 82
83 if (smum_is_dpm_running(hwmgr) && !amdgpu_passthrough(adev)) { 83 /* Skip for suspend/resume case */
84 if (smum_is_dpm_running(hwmgr) && !amdgpu_passthrough(adev)
85 && adev->in_suspend) {
84 pr_info("dpm has been enabled\n"); 86 pr_info("dpm has been enabled\n");
85 return 0; 87 return 0;
86 } 88 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 47ac92369739..0173d0480024 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -352,6 +352,9 @@ int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id,
352 352
353 switch (task_id) { 353 switch (task_id) {
354 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 354 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
355 ret = phm_pre_display_configuration_changed(hwmgr);
356 if (ret)
357 return ret;
355 ret = phm_set_cpu_power_state(hwmgr); 358 ret = phm_set_cpu_power_state(hwmgr);
356 if (ret) 359 if (ret)
357 return ret; 360 return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
index 91ffb7bc4ee7..56437866d120 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
@@ -265,8 +265,6 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip,
265 if (skip) 265 if (skip)
266 return 0; 266 return 0;
267 267
268 phm_pre_display_configuration_changed(hwmgr);
269
270 phm_display_configuration_changed(hwmgr); 268 phm_display_configuration_changed(hwmgr);
271 269
272 if (hwmgr->ps) 270 if (hwmgr->ps)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index ed35ec0341e6..b61a01f55284 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3589,8 +3589,10 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
3589 } 3589 }
3590 3590
3591 if (i >= sclk_table->count) { 3591 if (i >= sclk_table->count) {
3592 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 3592 if (sclk > sclk_table->dpm_levels[i-1].value) {
3593 sclk_table->dpm_levels[i-1].value = sclk; 3593 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3594 sclk_table->dpm_levels[i-1].value = sclk;
3595 }
3594 } else { 3596 } else {
3595 /* TODO: Check SCLK in DAL's minimum clocks 3597 /* TODO: Check SCLK in DAL's minimum clocks
3596 * in case DeepSleep divider update is required. 3598 * in case DeepSleep divider update is required.
@@ -3607,8 +3609,10 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
3607 } 3609 }
3608 3610
3609 if (i >= mclk_table->count) { 3611 if (i >= mclk_table->count) {
3610 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 3612 if (mclk > mclk_table->dpm_levels[i-1].value) {
3611 mclk_table->dpm_levels[i-1].value = mclk; 3613 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3614 mclk_table->dpm_levels[i-1].value = mclk;
3615 }
3612 } 3616 }
3613 3617
3614 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 3618 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
@@ -4525,12 +4529,12 @@ static int smu7_get_sclk_od(struct pp_hwmgr *hwmgr)
4525 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); 4529 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4526 struct smu7_single_dpm_table *golden_sclk_table = 4530 struct smu7_single_dpm_table *golden_sclk_table =
4527 &(data->golden_dpm_table.sclk_table); 4531 &(data->golden_dpm_table.sclk_table);
4528 int value; 4532 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
4533 int golden_value = golden_sclk_table->dpm_levels
4534 [golden_sclk_table->count - 1].value;
4529 4535
4530 value = (sclk_table->dpm_levels[sclk_table->count - 1].value - 4536 value -= golden_value;
4531 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) * 4537 value = DIV_ROUND_UP(value * 100, golden_value);
4532 100 /
4533 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
4534 4538
4535 return value; 4539 return value;
4536} 4540}
@@ -4567,12 +4571,12 @@ static int smu7_get_mclk_od(struct pp_hwmgr *hwmgr)
4567 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); 4571 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4568 struct smu7_single_dpm_table *golden_mclk_table = 4572 struct smu7_single_dpm_table *golden_mclk_table =
4569 &(data->golden_dpm_table.mclk_table); 4573 &(data->golden_dpm_table.mclk_table);
4570 int value; 4574 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
4575 int golden_value = golden_mclk_table->dpm_levels
4576 [golden_mclk_table->count - 1].value;
4571 4577
4572 value = (mclk_table->dpm_levels[mclk_table->count - 1].value - 4578 value -= golden_value;
4573 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) * 4579 value = DIV_ROUND_UP(value * 100, golden_value);
4574 100 /
4575 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
4576 4580
4577 return value; 4581 return value;
4578} 4582}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 8c4db86bb4b7..79c86247d0ac 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3266,8 +3266,10 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co
3266 } 3266 }
3267 3267
3268 if (i >= sclk_table->count) { 3268 if (i >= sclk_table->count) {
3269 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 3269 if (sclk > sclk_table->dpm_levels[i-1].value) {
3270 sclk_table->dpm_levels[i-1].value = sclk; 3270 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3271 sclk_table->dpm_levels[i-1].value = sclk;
3272 }
3271 } 3273 }
3272 3274
3273 for (i = 0; i < mclk_table->count; i++) { 3275 for (i = 0; i < mclk_table->count; i++) {
@@ -3276,8 +3278,10 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co
3276 } 3278 }
3277 3279
3278 if (i >= mclk_table->count) { 3280 if (i >= mclk_table->count) {
3279 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 3281 if (mclk > mclk_table->dpm_levels[i-1].value) {
3280 mclk_table->dpm_levels[i-1].value = mclk; 3282 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3283 mclk_table->dpm_levels[i-1].value = mclk;
3284 }
3281 } 3285 }
3282 3286
3283 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 3287 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
@@ -4522,15 +4526,13 @@ static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr)
4522 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 4526 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4523 struct vega10_single_dpm_table *golden_sclk_table = 4527 struct vega10_single_dpm_table *golden_sclk_table =
4524 &(data->golden_dpm_table.gfx_table); 4528 &(data->golden_dpm_table.gfx_table);
4525 int value; 4529 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
4526 4530 int golden_value = golden_sclk_table->dpm_levels
4527 value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
4528 golden_sclk_table->dpm_levels
4529 [golden_sclk_table->count - 1].value) *
4530 100 /
4531 golden_sclk_table->dpm_levels
4532 [golden_sclk_table->count - 1].value; 4531 [golden_sclk_table->count - 1].value;
4533 4532
4533 value -= golden_value;
4534 value = DIV_ROUND_UP(value * 100, golden_value);
4535
4534 return value; 4536 return value;
4535} 4537}
4536 4538
@@ -4575,16 +4577,13 @@ static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr)
4575 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 4577 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4576 struct vega10_single_dpm_table *golden_mclk_table = 4578 struct vega10_single_dpm_table *golden_mclk_table =
4577 &(data->golden_dpm_table.mem_table); 4579 &(data->golden_dpm_table.mem_table);
4578 int value; 4580 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
4579 4581 int golden_value = golden_mclk_table->dpm_levels
4580 value = (mclk_table->dpm_levels
4581 [mclk_table->count - 1].value -
4582 golden_mclk_table->dpm_levels
4583 [golden_mclk_table->count - 1].value) *
4584 100 /
4585 golden_mclk_table->dpm_levels
4586 [golden_mclk_table->count - 1].value; 4582 [golden_mclk_table->count - 1].value;
4587 4583
4584 value -= golden_value;
4585 value = DIV_ROUND_UP(value * 100, golden_value);
4586
4588 return value; 4587 return value;
4589} 4588}
4590 4589
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 74bc37308dc0..54364444ecd1 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -2243,12 +2243,12 @@ static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr)
2243 struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 2243 struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
2244 struct vega12_single_dpm_table *golden_sclk_table = 2244 struct vega12_single_dpm_table *golden_sclk_table =
2245 &(data->golden_dpm_table.gfx_table); 2245 &(data->golden_dpm_table.gfx_table);
2246 int value; 2246 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
2247 int golden_value = golden_sclk_table->dpm_levels
2248 [golden_sclk_table->count - 1].value;
2247 2249
2248 value = (sclk_table->dpm_levels[sclk_table->count - 1].value - 2250 value -= golden_value;
2249 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) * 2251 value = DIV_ROUND_UP(value * 100, golden_value);
2250 100 /
2251 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
2252 2252
2253 return value; 2253 return value;
2254} 2254}
@@ -2264,16 +2264,13 @@ static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr)
2264 struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 2264 struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
2265 struct vega12_single_dpm_table *golden_mclk_table = 2265 struct vega12_single_dpm_table *golden_mclk_table =
2266 &(data->golden_dpm_table.mem_table); 2266 &(data->golden_dpm_table.mem_table);
2267 int value; 2267 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
2268 2268 int golden_value = golden_mclk_table->dpm_levels
2269 value = (mclk_table->dpm_levels
2270 [mclk_table->count - 1].value -
2271 golden_mclk_table->dpm_levels
2272 [golden_mclk_table->count - 1].value) *
2273 100 /
2274 golden_mclk_table->dpm_levels
2275 [golden_mclk_table->count - 1].value; 2269 [golden_mclk_table->count - 1].value;
2276 2270
2271 value -= golden_value;
2272 value = DIV_ROUND_UP(value * 100, golden_value);
2273
2277 return value; 2274 return value;
2278} 2275}
2279 2276
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 99861f32b1f9..3b7fce5d7258 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -75,7 +75,17 @@ static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
75 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 75 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
76 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 76 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
77 77
78 data->registry_data.disallowed_features = 0x0; 78 /*
79 * Disable the following features for now:
80 * GFXCLK DS
81 * SOCLK DS
82 * LCLK DS
83 * DCEFCLK DS
84 * FCLK DS
85 * MP1CLK DS
86 * MP0CLK DS
87 */
88 data->registry_data.disallowed_features = 0xE0041C00;
79 data->registry_data.od_state_in_dc_support = 0; 89 data->registry_data.od_state_in_dc_support = 0;
80 data->registry_data.thermal_support = 1; 90 data->registry_data.thermal_support = 1;
81 data->registry_data.skip_baco_hardware = 0; 91 data->registry_data.skip_baco_hardware = 0;
@@ -120,7 +130,7 @@ static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
120 data->registry_data.disable_auto_wattman = 1; 130 data->registry_data.disable_auto_wattman = 1;
121 data->registry_data.auto_wattman_debug = 0; 131 data->registry_data.auto_wattman_debug = 0;
122 data->registry_data.auto_wattman_sample_period = 100; 132 data->registry_data.auto_wattman_sample_period = 100;
123 data->registry_data.fclk_gfxclk_ratio = 0x3F6CCCCD; 133 data->registry_data.fclk_gfxclk_ratio = 0;
124 data->registry_data.auto_wattman_threshold = 50; 134 data->registry_data.auto_wattman_threshold = 50;
125 data->registry_data.gfxoff_controlled_by_driver = 1; 135 data->registry_data.gfxoff_controlled_by_driver = 1;
126 data->gfxoff_allowed = false; 136 data->gfxoff_allowed = false;
@@ -1313,12 +1323,13 @@ static int vega20_get_sclk_od(
1313 &(data->dpm_table.gfx_table); 1323 &(data->dpm_table.gfx_table);
1314 struct vega20_single_dpm_table *golden_sclk_table = 1324 struct vega20_single_dpm_table *golden_sclk_table =
1315 &(data->golden_dpm_table.gfx_table); 1325 &(data->golden_dpm_table.gfx_table);
1316 int value; 1326 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
1327 int golden_value = golden_sclk_table->dpm_levels
1328 [golden_sclk_table->count - 1].value;
1317 1329
1318 /* od percentage */ 1330 /* od percentage */
1319 value = DIV_ROUND_UP((sclk_table->dpm_levels[sclk_table->count - 1].value - 1331 value -= golden_value;
1320 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) * 100, 1332 value = DIV_ROUND_UP(value * 100, golden_value);
1321 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value);
1322 1333
1323 return value; 1334 return value;
1324} 1335}
@@ -1358,12 +1369,13 @@ static int vega20_get_mclk_od(
1358 &(data->dpm_table.mem_table); 1369 &(data->dpm_table.mem_table);
1359 struct vega20_single_dpm_table *golden_mclk_table = 1370 struct vega20_single_dpm_table *golden_mclk_table =
1360 &(data->golden_dpm_table.mem_table); 1371 &(data->golden_dpm_table.mem_table);
1361 int value; 1372 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
1373 int golden_value = golden_mclk_table->dpm_levels
1374 [golden_mclk_table->count - 1].value;
1362 1375
1363 /* od percentage */ 1376 /* od percentage */
1364 value = DIV_ROUND_UP((mclk_table->dpm_levels[mclk_table->count - 1].value - 1377 value -= golden_value;
1365 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) * 100, 1378 value = DIV_ROUND_UP(value * 100, golden_value);
1366 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value);
1367 1379
1368 return value; 1380 return value;
1369} 1381}
@@ -1648,14 +1660,15 @@ static uint32_t vega20_find_highest_dpm_level(
1648 return i; 1660 return i;
1649} 1661}
1650 1662
1651static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr) 1663static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1652{ 1664{
1653 struct vega20_hwmgr *data = 1665 struct vega20_hwmgr *data =
1654 (struct vega20_hwmgr *)(hwmgr->backend); 1666 (struct vega20_hwmgr *)(hwmgr->backend);
1655 uint32_t min_freq; 1667 uint32_t min_freq;
1656 int ret = 0; 1668 int ret = 0;
1657 1669
1658 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 1670 if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1671 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1659 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level; 1672 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1660 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1673 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1661 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1674 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
@@ -1664,7 +1677,8 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
1664 return ret); 1677 return ret);
1665 } 1678 }
1666 1679
1667 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 1680 if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1681 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1668 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level; 1682 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1669 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1683 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1670 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1684 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
@@ -1680,7 +1694,8 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
1680 return ret); 1694 return ret);
1681 } 1695 }
1682 1696
1683 if (data->smu_features[GNLD_DPM_UVD].enabled) { 1697 if (data->smu_features[GNLD_DPM_UVD].enabled &&
1698 (feature_mask & FEATURE_DPM_UVD_MASK)) {
1684 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level; 1699 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1685 1700
1686 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1701 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@ -1698,7 +1713,8 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
1698 return ret); 1713 return ret);
1699 } 1714 }
1700 1715
1701 if (data->smu_features[GNLD_DPM_VCE].enabled) { 1716 if (data->smu_features[GNLD_DPM_VCE].enabled &&
1717 (feature_mask & FEATURE_DPM_VCE_MASK)) {
1702 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level; 1718 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1703 1719
1704 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1720 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@ -1708,7 +1724,8 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
1708 return ret); 1724 return ret);
1709 } 1725 }
1710 1726
1711 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { 1727 if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1728 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1712 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level; 1729 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1713 1730
1714 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1731 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@ -1721,14 +1738,15 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
1721 return ret; 1738 return ret;
1722} 1739}
1723 1740
1724static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr) 1741static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1725{ 1742{
1726 struct vega20_hwmgr *data = 1743 struct vega20_hwmgr *data =
1727 (struct vega20_hwmgr *)(hwmgr->backend); 1744 (struct vega20_hwmgr *)(hwmgr->backend);
1728 uint32_t max_freq; 1745 uint32_t max_freq;
1729 int ret = 0; 1746 int ret = 0;
1730 1747
1731 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 1748 if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1749 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1732 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level; 1750 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1733 1751
1734 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1752 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@ -1738,7 +1756,8 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
1738 return ret); 1756 return ret);
1739 } 1757 }
1740 1758
1741 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 1759 if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1760 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1742 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level; 1761 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1743 1762
1744 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1763 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@ -1748,7 +1767,8 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
1748 return ret); 1767 return ret);
1749 } 1768 }
1750 1769
1751 if (data->smu_features[GNLD_DPM_UVD].enabled) { 1770 if (data->smu_features[GNLD_DPM_UVD].enabled &&
1771 (feature_mask & FEATURE_DPM_UVD_MASK)) {
1752 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level; 1772 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1753 1773
1754 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1774 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@ -1765,7 +1785,8 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
1765 return ret); 1785 return ret);
1766 } 1786 }
1767 1787
1768 if (data->smu_features[GNLD_DPM_VCE].enabled) { 1788 if (data->smu_features[GNLD_DPM_VCE].enabled &&
1789 (feature_mask & FEATURE_DPM_VCE_MASK)) {
1769 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level; 1790 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1770 1791
1771 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1792 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@ -1775,7 +1796,8 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
1775 return ret); 1796 return ret);
1776 } 1797 }
1777 1798
1778 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { 1799 if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1800 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1779 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level; 1801 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1780 1802
1781 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1803 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@ -2114,12 +2136,12 @@ static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
2114 data->dpm_table.mem_table.dpm_state.soft_max_level = 2136 data->dpm_table.mem_table.dpm_state.soft_max_level =
2115 data->dpm_table.mem_table.dpm_levels[soft_level].value; 2137 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2116 2138
2117 ret = vega20_upload_dpm_min_level(hwmgr); 2139 ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2118 PP_ASSERT_WITH_CODE(!ret, 2140 PP_ASSERT_WITH_CODE(!ret,
2119 "Failed to upload boot level to highest!", 2141 "Failed to upload boot level to highest!",
2120 return ret); 2142 return ret);
2121 2143
2122 ret = vega20_upload_dpm_max_level(hwmgr); 2144 ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2123 PP_ASSERT_WITH_CODE(!ret, 2145 PP_ASSERT_WITH_CODE(!ret,
2124 "Failed to upload dpm max level to highest!", 2146 "Failed to upload dpm max level to highest!",
2125 return ret); 2147 return ret);
@@ -2146,12 +2168,12 @@ static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2146 data->dpm_table.mem_table.dpm_state.soft_max_level = 2168 data->dpm_table.mem_table.dpm_state.soft_max_level =
2147 data->dpm_table.mem_table.dpm_levels[soft_level].value; 2169 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2148 2170
2149 ret = vega20_upload_dpm_min_level(hwmgr); 2171 ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2150 PP_ASSERT_WITH_CODE(!ret, 2172 PP_ASSERT_WITH_CODE(!ret,
2151 "Failed to upload boot level to highest!", 2173 "Failed to upload boot level to highest!",
2152 return ret); 2174 return ret);
2153 2175
2154 ret = vega20_upload_dpm_max_level(hwmgr); 2176 ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2155 PP_ASSERT_WITH_CODE(!ret, 2177 PP_ASSERT_WITH_CODE(!ret,
2156 "Failed to upload dpm max level to highest!", 2178 "Failed to upload dpm max level to highest!",
2157 return ret); 2179 return ret);
@@ -2164,12 +2186,12 @@ static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2164{ 2186{
2165 int ret = 0; 2187 int ret = 0;
2166 2188
2167 ret = vega20_upload_dpm_min_level(hwmgr); 2189 ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2168 PP_ASSERT_WITH_CODE(!ret, 2190 PP_ASSERT_WITH_CODE(!ret,
2169 "Failed to upload DPM Bootup Levels!", 2191 "Failed to upload DPM Bootup Levels!",
2170 return ret); 2192 return ret);
2171 2193
2172 ret = vega20_upload_dpm_max_level(hwmgr); 2194 ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2173 PP_ASSERT_WITH_CODE(!ret, 2195 PP_ASSERT_WITH_CODE(!ret,
2174 "Failed to upload DPM Max Levels!", 2196 "Failed to upload DPM Max Levels!",
2175 return ret); 2197 return ret);
@@ -2227,12 +2249,12 @@ static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
2227 data->dpm_table.gfx_table.dpm_state.soft_max_level = 2249 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2228 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value; 2250 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2229 2251
2230 ret = vega20_upload_dpm_min_level(hwmgr); 2252 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2231 PP_ASSERT_WITH_CODE(!ret, 2253 PP_ASSERT_WITH_CODE(!ret,
2232 "Failed to upload boot level to lowest!", 2254 "Failed to upload boot level to lowest!",
2233 return ret); 2255 return ret);
2234 2256
2235 ret = vega20_upload_dpm_max_level(hwmgr); 2257 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2236 PP_ASSERT_WITH_CODE(!ret, 2258 PP_ASSERT_WITH_CODE(!ret,
2237 "Failed to upload dpm max level to highest!", 2259 "Failed to upload dpm max level to highest!",
2238 return ret); 2260 return ret);
@@ -2247,12 +2269,12 @@ static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
2247 data->dpm_table.mem_table.dpm_state.soft_max_level = 2269 data->dpm_table.mem_table.dpm_state.soft_max_level =
2248 data->dpm_table.mem_table.dpm_levels[soft_max_level].value; 2270 data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2249 2271
2250 ret = vega20_upload_dpm_min_level(hwmgr); 2272 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2251 PP_ASSERT_WITH_CODE(!ret, 2273 PP_ASSERT_WITH_CODE(!ret,
2252 "Failed to upload boot level to lowest!", 2274 "Failed to upload boot level to lowest!",
2253 return ret); 2275 return ret);
2254 2276
2255 ret = vega20_upload_dpm_max_level(hwmgr); 2277 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2256 PP_ASSERT_WITH_CODE(!ret, 2278 PP_ASSERT_WITH_CODE(!ret,
2257 "Failed to upload dpm max level to highest!", 2279 "Failed to upload dpm max level to highest!",
2258 return ret); 2280 return ret);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu7_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/smu7_ppsmc.h
index 62f36ba2435b..c1a99dfe4913 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu7_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu7_ppsmc.h
@@ -386,6 +386,8 @@ typedef uint16_t PPSMC_Result;
386#define PPSMC_MSG_AgmResetPsm ((uint16_t) 0x403) 386#define PPSMC_MSG_AgmResetPsm ((uint16_t) 0x403)
387#define PPSMC_MSG_ReadVftCell ((uint16_t) 0x404) 387#define PPSMC_MSG_ReadVftCell ((uint16_t) 0x404)
388 388
389#define PPSMC_MSG_ApplyAvfsCksOffVoltage ((uint16_t) 0x415)
390
389#define PPSMC_MSG_GFX_CU_PG_ENABLE ((uint16_t) 0x280) 391#define PPSMC_MSG_GFX_CU_PG_ENABLE ((uint16_t) 0x280)
390#define PPSMC_MSG_GFX_CU_PG_DISABLE ((uint16_t) 0x281) 392#define PPSMC_MSG_GFX_CU_PG_DISABLE ((uint16_t) 0x281)
391#define PPSMC_MSG_GetCurrPkgPwr ((uint16_t) 0x282) 393#define PPSMC_MSG_GetCurrPkgPwr ((uint16_t) 0x282)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index 872d3824337b..a1e0ac9ae248 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -1985,6 +1985,12 @@ int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
1985 1985
1986 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs); 1986 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs);
1987 1987
1988 /* Apply avfs cks-off voltages to avoid the overshoot
1989 * when switching to the highest sclk frequency
1990 */
1991 if (data->apply_avfs_cks_off_voltage)
1992 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ApplyAvfsCksOffVoltage);
1993
1988 return 0; 1994 return 0;
1989} 1995}
1990 1996
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
index 99d5e4f98f49..a6edd5df33b0 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
@@ -37,10 +37,13 @@ MODULE_FIRMWARE("amdgpu/fiji_smc.bin");
37MODULE_FIRMWARE("amdgpu/polaris10_smc.bin"); 37MODULE_FIRMWARE("amdgpu/polaris10_smc.bin");
38MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin"); 38MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin");
39MODULE_FIRMWARE("amdgpu/polaris10_k_smc.bin"); 39MODULE_FIRMWARE("amdgpu/polaris10_k_smc.bin");
40MODULE_FIRMWARE("amdgpu/polaris10_k2_smc.bin");
40MODULE_FIRMWARE("amdgpu/polaris11_smc.bin"); 41MODULE_FIRMWARE("amdgpu/polaris11_smc.bin");
41MODULE_FIRMWARE("amdgpu/polaris11_smc_sk.bin"); 42MODULE_FIRMWARE("amdgpu/polaris11_smc_sk.bin");
42MODULE_FIRMWARE("amdgpu/polaris11_k_smc.bin"); 43MODULE_FIRMWARE("amdgpu/polaris11_k_smc.bin");
44MODULE_FIRMWARE("amdgpu/polaris11_k2_smc.bin");
43MODULE_FIRMWARE("amdgpu/polaris12_smc.bin"); 45MODULE_FIRMWARE("amdgpu/polaris12_smc.bin");
46MODULE_FIRMWARE("amdgpu/polaris12_k_smc.bin");
44MODULE_FIRMWARE("amdgpu/vegam_smc.bin"); 47MODULE_FIRMWARE("amdgpu/vegam_smc.bin");
45MODULE_FIRMWARE("amdgpu/vega10_smc.bin"); 48MODULE_FIRMWARE("amdgpu/vega10_smc.bin");
46MODULE_FIRMWARE("amdgpu/vega10_acg_smc.bin"); 49MODULE_FIRMWARE("amdgpu/vega10_acg_smc.bin");
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-17 12:18:47 -0400