13 files changed, 151 insertions, 185 deletions

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
index 5e19f5977eb1..d138ddae563d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
@@ -967,7 +967,7 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
             PP_CAP(PHM_PlatformCaps_TDRamping) ||
             PP_CAP(PHM_PlatformCaps_TCPRamping)) {
 
-                adev->gfx.rlc.funcs->enter_safe_mode(adev);
+                amdgpu_gfx_rlc_enter_safe_mode(adev);
                 mutex_lock(&adev->grbm_idx_mutex);
                 value = 0;
                 value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX);
@@ -1014,13 +1014,13 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
                                         "Failed to enable DPM DIDT.", goto error);
                 }
                 mutex_unlock(&adev->grbm_idx_mutex);
-                adev->gfx.rlc.funcs->exit_safe_mode(adev);
+                amdgpu_gfx_rlc_exit_safe_mode(adev);
         }
 
         return 0;
 error:
         mutex_unlock(&adev->grbm_idx_mutex);
-        adev->gfx.rlc.funcs->exit_safe_mode(adev);
+        amdgpu_gfx_rlc_exit_safe_mode(adev);
         return result;
 }
 
@@ -1034,7 +1034,7 @@ int smu7_disable_didt_config(struct pp_hwmgr *hwmgr)
             PP_CAP(PHM_PlatformCaps_TDRamping) ||
             PP_CAP(PHM_PlatformCaps_TCPRamping)) {
 
-                adev->gfx.rlc.funcs->enter_safe_mode(adev);
+                amdgpu_gfx_rlc_enter_safe_mode(adev);
 
                 result = smu7_enable_didt(hwmgr, false);
                 PP_ASSERT_WITH_CODE((result == 0),
@@ -1046,12 +1046,12 @@ int smu7_disable_didt_config(struct pp_hwmgr *hwmgr)
                         PP_ASSERT_WITH_CODE((0 == result),
                                         "Failed to disable DPM DIDT.", goto error);
                 }
-                adev->gfx.rlc.funcs->exit_safe_mode(adev);
+                amdgpu_gfx_rlc_exit_safe_mode(adev);
         }
 
         return 0;
 error:
-        adev->gfx.rlc.funcs->exit_safe_mode(adev);
+        amdgpu_gfx_rlc_exit_safe_mode(adev);
         return result;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
index 99a33c33a32c..101c09b212ad 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
@@ -713,20 +713,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,
         for (i = 0; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) {
                 table->WatermarkRow[1][i].MinClock =
                         cpu_to_le16((uint16_t)
-                        (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz) /
-                        1000);
+                        (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
+                        1000));
                 table->WatermarkRow[1][i].MaxClock =
                         cpu_to_le16((uint16_t)
-                        (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz) /
-                        1000);
+                        (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
+                        1000));
                 table->WatermarkRow[1][i].MinUclk =
                         cpu_to_le16((uint16_t)
-                        (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
-                        1000);
+                        (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
+                        1000));
                 table->WatermarkRow[1][i].MaxUclk =
                         cpu_to_le16((uint16_t)
-                        (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz) /
-                        1000);
+                        (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
+                        1000));
                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
                                 wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
         }
@@ -734,20 +734,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,
         for (i = 0; i < wm_with_clock_ranges->num_wm_mcif_sets; i++) {
                 table->WatermarkRow[0][i].MinClock =
                         cpu_to_le16((uint16_t)
-                        (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz) /
-                        1000);
+                        (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
+                        1000));
                 table->WatermarkRow[0][i].MaxClock =
                         cpu_to_le16((uint16_t)
-                        (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz) /
-                        1000);
+                        (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
+                        1000));
                 table->WatermarkRow[0][i].MinUclk =
                         cpu_to_le16((uint16_t)
-                        (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
-                        1000);
+                        (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
+                        1000));
                 table->WatermarkRow[0][i].MaxUclk =
                         cpu_to_le16((uint16_t)
-                        (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz) /
-                        1000);
+                        (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
+                        1000));
                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
                                 wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
         }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
index 2d88abf97e7b..6f26cb241ecc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
@@ -937,7 +937,7 @@ static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
 
         num_se = adev->gfx.config.max_shader_engines;
 
-        adev->gfx.rlc.funcs->enter_safe_mode(adev);
+        amdgpu_gfx_rlc_enter_safe_mode(adev);
 
         mutex_lock(&adev->grbm_idx_mutex);
         for (count = 0; count < num_se; count++) {
@@ -962,7 +962,7 @@ static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
 
         vega10_didt_set_mask(hwmgr, true);
 
-        adev->gfx.rlc.funcs->exit_safe_mode(adev);
+        amdgpu_gfx_rlc_exit_safe_mode(adev);
 
         return 0;
 }
@@ -971,11 +971,11 @@ static int vega10_disable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
 {
         struct amdgpu_device *adev = hwmgr->adev;
 
-        adev->gfx.rlc.funcs->enter_safe_mode(adev);
+        amdgpu_gfx_rlc_enter_safe_mode(adev);
 
         vega10_didt_set_mask(hwmgr, false);
 
-        adev->gfx.rlc.funcs->exit_safe_mode(adev);
+        amdgpu_gfx_rlc_exit_safe_mode(adev);
 
         return 0;
 }
@@ -988,7 +988,7 @@ static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
 
         num_se = adev->gfx.config.max_shader_engines;
 
-        adev->gfx.rlc.funcs->enter_safe_mode(adev);
+        amdgpu_gfx_rlc_enter_safe_mode(adev);
 
         mutex_lock(&adev->grbm_idx_mutex);
         for (count = 0; count < num_se; count++) {
@@ -1007,7 +1007,7 @@ static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
 
         vega10_didt_set_mask(hwmgr, true);
 
-        adev->gfx.rlc.funcs->exit_safe_mode(adev);
+        amdgpu_gfx_rlc_exit_safe_mode(adev);
 
         vega10_program_gc_didt_config_registers(hwmgr, GCDiDtDroopCtrlConfig_vega10);
         if (PP_CAP(PHM_PlatformCaps_GCEDC))
@@ -1024,11 +1024,11 @@ static int vega10_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
         struct amdgpu_device *adev = hwmgr->adev;
         uint32_t data;
 
-        adev->gfx.rlc.funcs->enter_safe_mode(adev);
+        amdgpu_gfx_rlc_enter_safe_mode(adev);
 
         vega10_didt_set_mask(hwmgr, false);
 
-        adev->gfx.rlc.funcs->exit_safe_mode(adev);
+        amdgpu_gfx_rlc_exit_safe_mode(adev);
 
         if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
                 data = 0x00000000;
@@ -1049,7 +1049,7 @@ static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr)
 
         num_se = adev->gfx.config.max_shader_engines;
 
-        adev->gfx.rlc.funcs->enter_safe_mode(adev);
+        amdgpu_gfx_rlc_enter_safe_mode(adev);
 
         mutex_lock(&adev->grbm_idx_mutex);
         for (count = 0; count < num_se; count++) {
@@ -1070,7 +1070,7 @@ static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr)
 
         vega10_didt_set_mask(hwmgr, true);
 
-        adev->gfx.rlc.funcs->exit_safe_mode(adev);
+        amdgpu_gfx_rlc_exit_safe_mode(adev);
 
         return 0;
 }
@@ -1079,11 +1079,11 @@ static int vega10_disable_se_edc_config(struct pp_hwmgr *hwmgr)
 {
         struct amdgpu_device *adev = hwmgr->adev;
 
-        adev->gfx.rlc.funcs->enter_safe_mode(adev);
+        amdgpu_gfx_rlc_enter_safe_mode(adev);
 
         vega10_didt_set_mask(hwmgr, false);
 
-        adev->gfx.rlc.funcs->exit_safe_mode(adev);
+        amdgpu_gfx_rlc_exit_safe_mode(adev);
 
         return 0;
 }
@@ -1097,7 +1097,7 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
 
         num_se = adev->gfx.config.max_shader_engines;
 
-        adev->gfx.rlc.funcs->enter_safe_mode(adev);
+        amdgpu_gfx_rlc_enter_safe_mode(adev);
 
         vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
 
@@ -1118,7 +1118,7 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
 
         vega10_didt_set_mask(hwmgr, true);
 
-        adev->gfx.rlc.funcs->exit_safe_mode(adev);
+        amdgpu_gfx_rlc_exit_safe_mode(adev);
 
         vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCDroopCtrlConfig_vega10);
 
@@ -1138,11 +1138,11 @@ static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
         struct amdgpu_device *adev = hwmgr->adev;
         uint32_t data;
 
-        adev->gfx.rlc.funcs->enter_safe_mode(adev);
+        amdgpu_gfx_rlc_enter_safe_mode(adev);
 
         vega10_didt_set_mask(hwmgr, false);
 
-        adev->gfx.rlc.funcs->exit_safe_mode(adev);
+        amdgpu_gfx_rlc_exit_safe_mode(adev);
 
         if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
                 data = 0x00000000;
@@ -1160,7 +1160,7 @@ static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
         struct amdgpu_device *adev = hwmgr->adev;
         int result;
 
-        adev->gfx.rlc.funcs->enter_safe_mode(adev);
+        amdgpu_gfx_rlc_enter_safe_mode(adev);
 
         mutex_lock(&adev->grbm_idx_mutex);
         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
@@ -1173,7 +1173,7 @@ static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
 
         vega10_didt_set_mask(hwmgr, false);
 
-        adev->gfx.rlc.funcs->exit_safe_mode(adev);
+        amdgpu_gfx_rlc_exit_safe_mode(adev);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 57143d51e3ee..f2daf00cc911 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -120,6 +120,7 @@ static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
         data->registry_data.disable_auto_wattman = 1;
         data->registry_data.auto_wattman_debug = 0;
         data->registry_data.auto_wattman_sample_period = 100;
+        data->registry_data.fclk_gfxclk_ratio = 0x3F6CCCCD;
         data->registry_data.auto_wattman_threshold = 50;
         data->registry_data.gfxoff_controlled_by_driver = 1;
         data->gfxoff_allowed = false;
@@ -829,6 +830,28 @@ static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
         return 0;
 }
 
+static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
+{
+        struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
+
+        if (data->smu_features[GNLD_DPM_UCLK].enabled)
+                return smum_send_msg_to_smc_with_parameter(hwmgr,
+                        PPSMC_MSG_SetUclkFastSwitch,
+                        1);
+
+        return 0;
+}
+
+static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
+{
+        struct vega20_hwmgr *data =
+                        (struct vega20_hwmgr *)(hwmgr->backend);
+
+        return smum_send_msg_to_smc_with_parameter(hwmgr,
+                        PPSMC_MSG_SetFclkGfxClkRatio,
+                        data->registry_data.fclk_gfxclk_ratio);
+}
+
 static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
 {
         struct vega20_hwmgr *data =
@@ -1532,6 +1555,16 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
                         "[EnableDPMTasks] Failed to enable all smu features!",
                         return result);
 
+        result = vega20_notify_smc_display_change(hwmgr);
+        PP_ASSERT_WITH_CODE(!result,
+                        "[EnableDPMTasks] Failed to notify smc display change!",
+                        return result);
+
+        result = vega20_send_clock_ratio(hwmgr);
+        PP_ASSERT_WITH_CODE(!result,
+                        "[EnableDPMTasks] Failed to send clock ratio!",
+                        return result);
+
         /* Initialize UVD/VCE powergating state */
         vega20_init_powergate_state(hwmgr);
 
@@ -1972,19 +2005,6 @@ static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
         return ret;
 }
 
-static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr,
-                bool has_disp)
-{
-        struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
-
-        if (data->smu_features[GNLD_DPM_UCLK].enabled)
-                return smum_send_msg_to_smc_with_parameter(hwmgr,
-                        PPSMC_MSG_SetUclkFastSwitch,
-                        has_disp ? 1 : 0);
-
-        return 0;
-}
-
 int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
                 struct pp_display_clock_request *clock_req)
 {
@@ -2044,13 +2064,6 @@ static int vega20_notify_smc_display_config_after_ps_adjustment(
         struct pp_display_clock_request clock_req;
         int ret = 0;
 
-        if ((hwmgr->display_config->num_display > 1) &&
-             !hwmgr->display_config->multi_monitor_in_sync &&
-             !hwmgr->display_config->nb_pstate_switch_disable)
-                vega20_notify_smc_display_change(hwmgr, false);
-        else
-                vega20_notify_smc_display_change(hwmgr, true);
-
         min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
         min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
         min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
@@ -2742,7 +2755,7 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
                 for (i = 0; i < clocks.num_levels; i++)
                         size += sprintf(buf + size, "%d: %uMhz %s\n",
                                 i, clocks.data[i].clocks_in_khz / 1000,
-                                (clocks.data[i].clocks_in_khz == now) ? "*" : "");
+                                (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
                 break;
 
         case PP_MCLK:
@@ -2759,7 +2772,7 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
                 for (i = 0; i < clocks.num_levels; i++)
                         size += sprintf(buf + size, "%d: %uMhz %s\n",
                                 i, clocks.data[i].clocks_in_khz / 1000,
-                                (clocks.data[i].clocks_in_khz == now) ? "*" : "");
+                                (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
                 break;
 
         case PP_PCIE:
@@ -3441,109 +3454,64 @@ static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
 
 static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
         /* init/fini related */
-        .backend_init =
-                vega20_hwmgr_backend_init,
-        .backend_fini =
-                vega20_hwmgr_backend_fini,
-        .asic_setup =
-                vega20_setup_asic_task,
-        .power_off_asic =
-                vega20_power_off_asic,
-        .dynamic_state_management_enable =
-                vega20_enable_dpm_tasks,
-        .dynamic_state_management_disable =
-                vega20_disable_dpm_tasks,
+        .backend_init = vega20_hwmgr_backend_init,
+        .backend_fini = vega20_hwmgr_backend_fini,
+        .asic_setup = vega20_setup_asic_task,
+        .power_off_asic = vega20_power_off_asic,
+        .dynamic_state_management_enable = vega20_enable_dpm_tasks,
+        .dynamic_state_management_disable = vega20_disable_dpm_tasks,
         /* power state related */
-        .apply_clocks_adjust_rules =
-                vega20_apply_clocks_adjust_rules,
-        .pre_display_config_changed =
-                vega20_pre_display_configuration_changed_task,
-        .display_config_changed =
-                vega20_display_configuration_changed_task,
+        .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
+        .pre_display_config_changed = vega20_pre_display_configuration_changed_task,
+        .display_config_changed = vega20_display_configuration_changed_task,
         .check_smc_update_required_for_display_configuration =
                 vega20_check_smc_update_required_for_display_configuration,
         .notify_smc_display_config_after_ps_adjustment =
                 vega20_notify_smc_display_config_after_ps_adjustment,
         /* export to DAL */
-        .get_sclk =
-                vega20_dpm_get_sclk,
-        .get_mclk =
-                vega20_dpm_get_mclk,
-        .get_dal_power_level =
-                vega20_get_dal_power_level,
-        .get_clock_by_type_with_latency =
-                vega20_get_clock_by_type_with_latency,
-        .get_clock_by_type_with_voltage =
-                vega20_get_clock_by_type_with_voltage,
-        .set_watermarks_for_clocks_ranges =
-                vega20_set_watermarks_for_clocks_ranges,
-        .display_clock_voltage_request =
-                vega20_display_clock_voltage_request,
-        .get_performance_level =
-                vega20_get_performance_level,
+        .get_sclk = vega20_dpm_get_sclk,
+        .get_mclk = vega20_dpm_get_mclk,
+        .get_dal_power_level = vega20_get_dal_power_level,
+        .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
+        .get_clock_by_type_with_voltage = vega20_get_clock_by_type_with_voltage,
+        .set_watermarks_for_clocks_ranges = vega20_set_watermarks_for_clocks_ranges,
+        .display_clock_voltage_request = vega20_display_clock_voltage_request,
+        .get_performance_level = vega20_get_performance_level,
         /* UMD pstate, profile related */
-        .force_dpm_level =
-                vega20_dpm_force_dpm_level,
-        .get_power_profile_mode =
-                vega20_get_power_profile_mode,
-        .set_power_profile_mode =
-                vega20_set_power_profile_mode,
+        .force_dpm_level = vega20_dpm_force_dpm_level,
+        .get_power_profile_mode = vega20_get_power_profile_mode,
+        .set_power_profile_mode = vega20_set_power_profile_mode,
         /* od related */
-        .set_power_limit =
-                vega20_set_power_limit,
-        .get_sclk_od =
-                vega20_get_sclk_od,
-        .set_sclk_od =
-                vega20_set_sclk_od,
-        .get_mclk_od =
-                vega20_get_mclk_od,
-        .set_mclk_od =
-                vega20_set_mclk_od,
-        .odn_edit_dpm_table =
-                vega20_odn_edit_dpm_table,
+        .set_power_limit = vega20_set_power_limit,
+        .get_sclk_od = vega20_get_sclk_od,
+        .set_sclk_od = vega20_set_sclk_od,
+        .get_mclk_od = vega20_get_mclk_od,
+        .set_mclk_od = vega20_set_mclk_od,
+        .odn_edit_dpm_table = vega20_odn_edit_dpm_table,
         /* for sysfs to retrive/set gfxclk/memclk */
-        .force_clock_level =
-                vega20_force_clock_level,
-        .print_clock_levels =
-                vega20_print_clock_levels,
-        .read_sensor =
-                vega20_read_sensor,
+        .force_clock_level = vega20_force_clock_level,
+        .print_clock_levels = vega20_print_clock_levels,
+        .read_sensor = vega20_read_sensor,
         /* powergate related */
-        .powergate_uvd =
-                vega20_power_gate_uvd,
-        .powergate_vce =
-                vega20_power_gate_vce,
+        .powergate_uvd = vega20_power_gate_uvd,
+        .powergate_vce = vega20_power_gate_vce,
         /* thermal related */
-        .start_thermal_controller =
-                vega20_start_thermal_controller,
-        .stop_thermal_controller =
-                vega20_thermal_stop_thermal_controller,
-        .get_thermal_temperature_range =
-                vega20_get_thermal_temperature_range,
-        .register_irq_handlers =
-                smu9_register_irq_handlers,
-        .disable_smc_firmware_ctf =
-                vega20_thermal_disable_alert,
+        .start_thermal_controller = vega20_start_thermal_controller,
+        .stop_thermal_controller = vega20_thermal_stop_thermal_controller,
+        .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
+        .register_irq_handlers = smu9_register_irq_handlers,
+        .disable_smc_firmware_ctf = vega20_thermal_disable_alert,
         /* fan control related */
-        .get_fan_speed_percent =
-                vega20_fan_ctrl_get_fan_speed_percent,
-        .set_fan_speed_percent =
-                vega20_fan_ctrl_set_fan_speed_percent,
-        .get_fan_speed_info =
-                vega20_fan_ctrl_get_fan_speed_info,
-        .get_fan_speed_rpm =
-                vega20_fan_ctrl_get_fan_speed_rpm,
-        .set_fan_speed_rpm =
-                vega20_fan_ctrl_set_fan_speed_rpm,
-        .get_fan_control_mode =
-                vega20_get_fan_control_mode,
-        .set_fan_control_mode =
-                vega20_set_fan_control_mode,
+        .get_fan_speed_percent = vega20_fan_ctrl_get_fan_speed_percent,
+        .set_fan_speed_percent = vega20_fan_ctrl_set_fan_speed_percent,
+        .get_fan_speed_info = vega20_fan_ctrl_get_fan_speed_info,
+        .get_fan_speed_rpm = vega20_fan_ctrl_get_fan_speed_rpm,
+        .set_fan_speed_rpm = vega20_fan_ctrl_set_fan_speed_rpm,
+        .get_fan_control_mode = vega20_get_fan_control_mode,
+        .set_fan_control_mode = vega20_set_fan_control_mode,
         /* smu memory related */
-        .notify_cac_buffer_info =
-                vega20_notify_cac_buffer_info,
-        .enable_mgpu_fan_boost =
-                vega20_enable_mgpu_fan_boost,
+        .notify_cac_buffer_info = vega20_notify_cac_buffer_info,
+        .enable_mgpu_fan_boost = vega20_enable_mgpu_fan_boost,
 };
 
 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
index 56fe6a0d42e8..25faaa5c5b10 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
@@ -328,6 +328,7 @@ struct vega20_registry_data {
         uint8_t   disable_auto_wattman;
         uint32_t  auto_wattman_debug;
         uint32_t  auto_wattman_sample_period;
+        uint32_t  fclk_gfxclk_ratio;
         uint8_t   auto_wattman_threshold;
         uint8_t   log_avfs_param;
         uint8_t   enable_enginess;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index e5a60aa44b5d..07d180ce4d18 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -28,7 +28,6 @@
 #include "hardwaremanager.h"
 #include "hwmgr_ppt.h"
 #include "ppatomctrl.h"
-#include "hwmgr_ppt.h"
 #include "power_state.h"
 #include "smu_helper.h"
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu7_common.h b/drivers/gpu/drm/amd/powerplay/inc/smu7_common.h
index 65eb630bfea3..94bf7b649c20 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu7_common.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu7_common.h
@@ -40,10 +40,6 @@
 #include "bif/bif_5_0_d.h"
 #include "bif/bif_5_0_sh_mask.h"
 
-
-#include "bif/bif_5_0_d.h"
-#include "bif/bif_5_0_sh_mask.h"
-
 #include "dce/dce_10_0_d.h"
 #include "dce/dce_10_0_sh_mask.h"
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
index 45d64a81e945..4f63a736ea0e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
@@ -105,7 +105,8 @@
 #define PPSMC_MSG_SetSystemVirtualDramAddrHigh   0x4B
 #define PPSMC_MSG_SetSystemVirtualDramAddrLow    0x4C
 #define PPSMC_MSG_WaflTest                       0x4D
-// Unused ID 0x4E to 0x50
+#define PPSMC_MSG_SetFclkGfxClkRatio             0x4E
+// Unused ID 0x4F to 0x50
 #define PPSMC_MSG_AllowGfxOff                    0x51
 #define PPSMC_MSG_DisallowGfxOff                 0x52
 #define PPSMC_MSG_GetPptLimit                    0x53
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index 872d3824337b..2b2c26616902 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -44,7 +44,6 @@
 
 #include "smu7_hwmgr.h"
 #include "hardwaremanager.h"
-#include "ppatomctrl.h"
 #include "atombios.h"
 #include "pppcielanes.h"
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
index d0eb8ab50148..d111dd4e03d7 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
@@ -29,7 +29,6 @@
 #include "rv_ppsmc.h"
 #include "smu10_driver_if.h"
 #include "smu10.h"
-#include "ppatomctrl.h"
 #include "pp_debug.h"
 
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
index 09b844ec3eab..e2787e14a500 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
@@ -24,6 +24,7 @@
 #include <linux/delay.h>
 #include <linux/gfp.h>
 #include <linux/kernel.h>
+#include <linux/ktime.h>
 #include <linux/slab.h>
 #include <linux/types.h>
 
@@ -61,9 +62,13 @@ static uint32_t smu8_get_argument(struct pp_hwmgr *hwmgr)
                                         mmSMU_MP1_SRBM2P_ARG_0);
 }
 
-static int smu8_send_msg_to_smc_async(struct pp_hwmgr *hwmgr, uint16_t msg)
+/* Send a message to the SMC, and wait for its response.*/
+static int smu8_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
+                                            uint16_t msg, uint32_t parameter)
 {
         int result = 0;
+        ktime_t t_start;
+        s64 elapsed_us;
 
         if (hwmgr == NULL || hwmgr->device == NULL)
                 return -EINVAL;
@@ -74,28 +79,31 @@ static int smu8_send_msg_to_smc_async(struct pp_hwmgr *hwmgr, uint16_t msg)
                 /* Read the last message to SMU, to report actual cause */
                 uint32_t val = cgs_read_register(hwmgr->device,
                                                  mmSMU_MP1_SRBM2P_MSG_0);
-                pr_err("smu8_send_msg_to_smc_async (0x%04x) failed\n", msg);
-                pr_err("SMU still servicing msg (0x%04x)\n", val);
+                pr_err("%s(0x%04x) aborted; SMU still servicing msg (0x%04x)\n",
+                        __func__, msg, val);
                 return result;
         }
+        t_start = ktime_get();
+
+        cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter);
 
         cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0);
         cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg);
 
-        return 0;
+        result = PHM_WAIT_FIELD_UNEQUAL(hwmgr,
+                                        SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
+
+        elapsed_us = ktime_us_delta(ktime_get(), t_start);
+
+        WARN(result, "%s(0x%04x, %#x) timed out after %lld us\n",
+                        __func__, msg, parameter, elapsed_us);
+
+        return result;
 }
 
-/* Send a message to the SMC, and wait for its response.*/
 static int smu8_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
 {
-        int result = 0;
-
-        result = smu8_send_msg_to_smc_async(hwmgr, msg);
-        if (result != 0)
-                return result;
-
-        return PHM_WAIT_FIELD_UNEQUAL(hwmgr,
-                                        SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
+        return smu8_send_msg_to_smc_with_parameter(hwmgr, msg, 0);
 }
 
 static int smu8_set_smc_sram_address(struct pp_hwmgr *hwmgr,
@@ -135,17 +143,6 @@ static int smu8_write_smc_sram_dword(struct pp_hwmgr *hwmgr,
         return result;
 }
 
-static int smu8_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
-                                          uint16_t msg, uint32_t parameter)
-{
-        if (hwmgr == NULL || hwmgr->device == NULL)
-                return -EINVAL;
-
-        cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter);
-
-        return smu8_send_msg_to_smc(hwmgr, msg);
-}
-
 static int smu8_check_fw_load_finish(struct pp_hwmgr *hwmgr,
                                    uint32_t firmware)
 {
@@ -737,6 +734,10 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr)
 
         cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
         hwmgr->smu_version = cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA);
+        pr_info("smu version %02d.%02d.%02d\n",
+                ((hwmgr->smu_version >> 16) & 0xFF),
+                ((hwmgr->smu_version >> 8) & 0xFF),
+                (hwmgr->smu_version & 0xFF));
         adev->pm.fw_version = hwmgr->smu_version >> 8;
 
         return smu8_request_smu_load_fw(hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
index 99d5e4f98f49..a6edd5df33b0 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
@@ -37,10 +37,13 @@ MODULE_FIRMWARE("amdgpu/fiji_smc.bin");
 MODULE_FIRMWARE("amdgpu/polaris10_smc.bin");
 MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin");
 MODULE_FIRMWARE("amdgpu/polaris10_k_smc.bin");
+MODULE_FIRMWARE("amdgpu/polaris10_k2_smc.bin");
 MODULE_FIRMWARE("amdgpu/polaris11_smc.bin");
 MODULE_FIRMWARE("amdgpu/polaris11_smc_sk.bin");
 MODULE_FIRMWARE("amdgpu/polaris11_k_smc.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_k2_smc.bin");
 MODULE_FIRMWARE("amdgpu/polaris12_smc.bin");
+MODULE_FIRMWARE("amdgpu/polaris12_k_smc.bin");
 MODULE_FIRMWARE("amdgpu/vegam_smc.bin");
 MODULE_FIRMWARE("amdgpu/vega10_smc.bin");
 MODULE_FIRMWARE("amdgpu/vega10_acg_smc.bin");
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
index 9f71512b2510..1e69300f6175 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
@@ -40,7 +40,6 @@
 
 #include "smu7_hwmgr.h"
 #include "hardwaremanager.h"
-#include "ppatomctrl.h"
 #include "atombios.h"
 #include "pppcielanes.h"