22 files changed, 234 insertions, 129 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index cf4e190c0a72..1c49b8266d69 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1428,6 +1428,9 @@ int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
        if (IS_ERR(fence))
                return PTR_ERR(fence);
+        if (!fence)
+                fence = dma_fence_get_stub();
        switch (info->in.what) {
        case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
                r = drm_syncobj_create(&syncobj, 0, fence);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b60afeade50a..8a078f4ae73d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3476,14 +3476,16 @@ static void amdgpu_device_lock_adev(struct amdgpu_device *adev)
        mutex_lock(&adev->lock_reset);
        atomic_inc(&adev->gpu_reset_counter);
        adev->in_gpu_reset = 1;
-        /* Block kfd */
+        /* Block kfd: SRIOV would do it separately */
-        amdgpu_amdkfd_pre_reset(adev);
+        if (!amdgpu_sriov_vf(adev))
+                amdgpu_amdkfd_pre_reset(adev);
 }
 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
 {
-        /*unlock kfd */
+        /*unlock kfd: SRIOV would do it separately */
-        amdgpu_amdkfd_post_reset(adev);
+        if (!amdgpu_sriov_vf(adev))
+                amdgpu_amdkfd_post_reset(adev);
        amdgpu_vf_error_trans_all(adev);
        adev->in_gpu_reset = 0;
        mutex_unlock(&adev->lock_reset);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 9c77eaa45982..c806f984bcc5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -865,6 +865,7 @@ static const struct pci_device_id pciidlist[] = {
        /* VEGAM */
        {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
        {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
+        {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
        /* Vega 10 */
        {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
        {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index e0af44fd6a0c..0a17fb1af204 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -32,6 +32,9 @@ static void amdgpu_job_timedout(struct drm_sched_job *s_job)
 {
        struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
        struct amdgpu_job *job = to_amdgpu_job(s_job);
+        struct amdgpu_task_info ti;
+        memset(&ti, 0, sizeof(struct amdgpu_task_info));
        if (amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) {
                DRM_ERROR("ring %s timeout, but soft recovered\n",
@@ -39,9 +42,12 @@ static void amdgpu_job_timedout(struct drm_sched_job *s_job)
                return;
        }
+        amdgpu_vm_get_task_info(ring->adev, job->pasid, &ti);
        DRM_ERROR("ring %s timeout, signaled seq=%u, emitted seq=%u\n",
                  job->base.sched->name, atomic_read(&ring->fence_drv.last_seq),
                  ring->fence_drv.sync_seq);
+        DRM_ERROR("Process information: process %s pid %d thread %s pid %d\n",
+                  ti.process_name, ti.tgid, ti.task_name, ti.pid);
        if (amdgpu_device_should_recover_gpu(ring->adev))
                amdgpu_device_gpu_recover(ring->adev, job);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index e55508b39496..3e6823fdd939 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -238,44 +238,40 @@ static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node,
 * amdgpu_mn_invalidate_range_start_gfx - callback to notify about mm change
 *
 * @mn: our notifier
- * @mm: the mm this callback is about
+ * @range: mmu notifier context
- * @start: start of updated range
- * @end: end of updated range
 *
 * Block for operations on BOs to finish and mark pages as accessed and
 * potentially dirty.
 */
 static int amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn,
-                                                 struct mm_struct *mm,
+                        const struct mmu_notifier_range *range)
-                                                 unsigned long start,
-                                                 unsigned long end,
-                                                 bool blockable)
 {
        struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn);
        struct interval_tree_node *it;
+        unsigned long end;
        /* notification is exclusive, but interval is inclusive */
-        end -= 1;
+        end = range->end - 1;
        /* TODO we should be able to split locking for interval tree and
         * amdgpu_mn_invalidate_node
         */
-        if (amdgpu_mn_read_lock(amn, blockable))
+        if (amdgpu_mn_read_lock(amn, range->blockable))
                return -EAGAIN;
-        it = interval_tree_iter_first(&amn->objects, start, end);
+        it = interval_tree_iter_first(&amn->objects, range->start, end);
        while (it) {
                struct amdgpu_mn_node *node;
-                if (!blockable) {
+                if (!range->blockable) {
                        amdgpu_mn_read_unlock(amn);
                        return -EAGAIN;
                }
                node = container_of(it, struct amdgpu_mn_node, it);
-                it = interval_tree_iter_next(it, start, end);
+                it = interval_tree_iter_next(it, range->start, end);
-                amdgpu_mn_invalidate_node(node, start, end);
+                amdgpu_mn_invalidate_node(node, range->start, end);
        }
        return 0;
@@ -294,39 +290,38 @@ static int amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn,
 * are restorted in amdgpu_mn_invalidate_range_end_hsa.
 */
 static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn,
-                                                 struct mm_struct *mm,
+                        const struct mmu_notifier_range *range)
-                                                 unsigned long start,
-                                                 unsigned long end,
-                                                 bool blockable)
 {
        struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn);
        struct interval_tree_node *it;
+        unsigned long end;
        /* notification is exclusive, but interval is inclusive */
-        end -= 1;
+        end = range->end - 1;
-        if (amdgpu_mn_read_lock(amn, blockable))
+        if (amdgpu_mn_read_lock(amn, range->blockable))
                return -EAGAIN;
-        it = interval_tree_iter_first(&amn->objects, start, end);
+        it = interval_tree_iter_first(&amn->objects, range->start, end);
        while (it) {
                struct amdgpu_mn_node *node;
                struct amdgpu_bo *bo;
-                if (!blockable) {
+                if (!range->blockable) {
                        amdgpu_mn_read_unlock(amn);
                        return -EAGAIN;
                }
                node = container_of(it, struct amdgpu_mn_node, it);
-                it = interval_tree_iter_next(it, start, end);
+                it = interval_tree_iter_next(it, range->start, end);
                list_for_each_entry(bo, &node->bos, mn_list) {
                        struct kgd_mem *mem = bo->kfd_bo;
                        if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm,
-                                                         start, end))
+                                                         range->start,
-                                amdgpu_amdkfd_evict_userptr(mem, mm);
+                                                         end))
+                                amdgpu_amdkfd_evict_userptr(mem, range->mm);
                }
        }
@@ -344,9 +339,7 @@ static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn,
 * Release the lock again to allow new command submissions.
 */
 static void amdgpu_mn_invalidate_range_end(struct mmu_notifier *mn,
-                                           struct mm_struct *mm,
+                        const struct mmu_notifier_range *range)
-                                           unsigned long start,
-                                           unsigned long end)
 {
        struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index fd271f9746a2..728e15e5d68a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -912,7 +912,7 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
        struct ttm_operation_ctx ctx = { false, false };
        int r, i;
-        if (!bo->pin_count) {
+        if (WARN_ON_ONCE(!bo->pin_count)) {
                dev_warn(adev->dev, "%p unpin not necessary\n", bo);
                return 0;
        }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 6759d898b3ab..8fab0d637ee5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -155,14 +155,6 @@ psp_cmd_submit_buf(struct psp_context *psp,
        return ret;
 }
-bool psp_support_vmr_ring(struct psp_context *psp)
-{
-        if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
-                return true;
-        else
-                return false;
-}
 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
                                 struct psp_gfx_cmd_resp *cmd,
                                 uint64_t tmr_mc, uint32_t size)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 10decf70c9aa..3ee573b4016e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -83,12 +83,13 @@ struct psp_funcs
                                  enum AMDGPU_UCODE_ID ucode_type);
        bool (*smu_reload_quirk)(struct psp_context *psp);
        int (*mode1_reset)(struct psp_context *psp);
-        uint64_t (*xgmi_get_node_id)(struct psp_context *psp);
+        int (*xgmi_get_node_id)(struct psp_context *psp, uint64_t *node_id);
-        uint64_t (*xgmi_get_hive_id)(struct psp_context *psp);
+        int (*xgmi_get_hive_id)(struct psp_context *psp, uint64_t *hive_id);
        int (*xgmi_get_topology_info)(struct psp_context *psp, int number_devices,
                                      struct psp_xgmi_topology_info *topology);
        int (*xgmi_set_topology_info)(struct psp_context *psp, int number_devices,
                                      struct psp_xgmi_topology_info *topology);
+        bool (*support_vmr_ring)(struct psp_context *psp);
 };
 struct psp_xgmi_context {
@@ -192,12 +193,14 @@ struct psp_xgmi_topology_info {
                ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
 #define psp_smu_reload_quirk(psp) \
                ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
+#define psp_support_vmr_ring(psp) \
+                ((psp)->funcs->support_vmr_ring ? (psp)->funcs->support_vmr_ring((psp)) : false)
 #define psp_mode1_reset(psp) \
                ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
-#define psp_xgmi_get_node_id(psp) \
+#define psp_xgmi_get_node_id(psp, node_id) \
-                ((psp)->funcs->xgmi_get_node_id ? (psp)->funcs->xgmi_get_node_id((psp)) : 0)
+                ((psp)->funcs->xgmi_get_node_id ? (psp)->funcs->xgmi_get_node_id((psp), (node_id)) : -EINVAL)
-#define psp_xgmi_get_hive_id(psp) \
+#define psp_xgmi_get_hive_id(psp, hive_id) \
-                ((psp)->funcs->xgmi_get_hive_id ? (psp)->funcs->xgmi_get_hive_id((psp)) : 0)
+                ((psp)->funcs->xgmi_get_hive_id ? (psp)->funcs->xgmi_get_hive_id((psp), (hive_id)) : -EINVAL)
 #define psp_xgmi_get_topology_info(psp, num_device, topology) \
                ((psp)->funcs->xgmi_get_topology_info ? \
                (psp)->funcs->xgmi_get_topology_info((psp), (num_device), (topology)) : -EINVAL)
@@ -217,8 +220,6 @@ extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
 int psp_gpu_reset(struct amdgpu_device *adev);
 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
-bool psp_support_vmr_ring(struct psp_context *psp);
 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 0beb01fef83f..d87e828a084b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -29,7 +29,7 @@
 #include <drm/drm_print.h>
 /* max number of rings */
-#define AMDGPU_MAX_RINGS                21
+#define AMDGPU_MAX_RINGS                23
 #define AMDGPU_MAX_GFX_RINGS            1
 #define AMDGPU_MAX_COMPUTE_RINGS        8
 #define AMDGPU_MAX_VCE_RINGS            3
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index e2e42e3fbcf3..ecf6f96df2ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -262,7 +262,7 @@ static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev,
                                ring = &adev->vcn.ring_dec;
                                WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
-                                                   RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2));
+                                                   RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
                                SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
                                                   UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
                                                   UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
@@ -322,7 +322,7 @@ static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev,
                                ring = &adev->vcn.ring_dec;
                                WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
-                                                   RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2));
+                                                   RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
                                SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
                                                   UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
                                                   UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
@@ -396,16 +396,26 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
        if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
                struct dpg_pause_state new_state;
+                unsigned int fences = 0;
+                unsigned int i;
-                if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
+                for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+                        fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]);
+                }
+                if (fences)
                        new_state.fw_based = VCN_DPG_STATE__PAUSE;
                else
-                        new_state.fw_based = adev->vcn.pause_state.fw_based;
+                        new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
-                if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
+                if (amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg))
                        new_state.jpeg = VCN_DPG_STATE__PAUSE;
                else
-                        new_state.jpeg = adev->vcn.pause_state.jpeg;
+                        new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
+                if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
+                        new_state.fw_based = VCN_DPG_STATE__PAUSE;
+                else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
+                        new_state.jpeg = VCN_DPG_STATE__PAUSE;
                amdgpu_vcn_pause_dpg_mode(adev, &new_state);
        }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 0b263a9857c6..8a8bc60cb6b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -97,8 +97,19 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
        if (!adev->gmc.xgmi.supported)
                return 0;
-        adev->gmc.xgmi.node_id = psp_xgmi_get_node_id(&adev->psp);
+        ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id);
-        adev->gmc.xgmi.hive_id = psp_xgmi_get_hive_id(&adev->psp);
+        if (ret) {
+                dev_err(adev->dev,
+                        "XGMI: Failed to get node id\n");
+                return ret;
+        }
+        ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id);
+        if (ret) {
+                dev_err(adev->dev,
+                        "XGMI: Failed to get hive id\n");
+                return ret;
+        }
        mutex_lock(&xgmi_mutex);
        hive = amdgpu_get_xgmi_hive(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index ce150de723c9..bacdaef77b6c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -718,37 +718,46 @@ static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
        }
 }
-static int gmc_v9_0_late_init(void *handle)
+static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev)
 {
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        struct amdgpu_ring *ring;
-        /*
+        unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] =
-         * The latest engine allocation on gfx9 is:
+                {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP};
-         * Engine 0, 1: idle
-         * Engine 2, 3: firmware
-         * Engine 4~13: amdgpu ring, subject to change when ring number changes
-         * Engine 14~15: idle
-         * Engine 16: kfd tlb invalidation
-         * Engine 17: Gart flushes
-         */
-        unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
        unsigned i;
-        int r;
+        unsigned vmhub, inv_eng;
-        if (!gmc_v9_0_keep_stolen_memory(adev))
+        for (i = 0; i < adev->num_rings; ++i) {
-                amdgpu_bo_late_init(adev);
+                ring = adev->rings[i];
+                vmhub = ring->funcs->vmhub;
+                inv_eng = ffs(vm_inv_engs[vmhub]);
+                if (!inv_eng) {
+                        dev_err(adev->dev, "no VM inv eng for ring %s\n",
+                                ring->name);
+                        return -EINVAL;
+                }
-        for(i = 0; i < adev->num_rings; ++i) {
+                ring->vm_inv_eng = inv_eng - 1;
-                struct amdgpu_ring *ring = adev->rings[i];
+                change_bit(inv_eng - 1, (unsigned long *)(&vm_inv_engs[vmhub]));
-                unsigned vmhub = ring->funcs->vmhub;
-                ring->vm_inv_eng = vm_inv_eng[vmhub]++;
                dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
                         ring->name, ring->vm_inv_eng, ring->funcs->vmhub);
        }
-        /* Engine 16 is used for KFD and 17 for GART flushes */
+        return 0;
-        for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
+}
-                BUG_ON(vm_inv_eng[i] > 16);
+static int gmc_v9_0_late_init(void *handle)
+{
+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        int r;
+        if (!gmc_v9_0_keep_stolen_memory(adev))
+                amdgpu_bo_late_init(adev);
+        r = gmc_v9_0_allocate_vm_inv_eng(adev);
+        if (r)
+                return r;
        if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) {
                r = gmc_v9_0_ecc_available(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
index b030ca5ea107..5c8deac65580 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
@@ -24,6 +24,16 @@
 #ifndef __GMC_V9_0_H__
 #define __GMC_V9_0_H__
+        /*
+         * The latest engine allocation on gfx9 is:
+         * Engine 2, 3: firmware
+         * Engine 0, 1, 4~16: amdgpu ring,
+         *                    subject to change when ring number changes
+         * Engine 17: Gart flushes
+         */
+#define GFXHUB_FREE_VM_INV_ENGS_BITMAP          0x1FFF3
+#define MMHUB_FREE_VM_INV_ENGS_BITMAP           0x1FFF3
 extern const struct amd_ip_funcs gmc_v9_0_ip_funcs;
 extern const struct amdgpu_ip_block_version gmc_v9_0_ip_block;
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 6f9c54978cc1..accdedd63c98 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -32,6 +32,7 @@
 #define smnCPM_CONTROL                                                                                  0x11180460
 #define smnPCIE_CNTL2                                                                                   0x11180070
 #define smnPCIE_CONFIG_CNTL                                                                             0x11180044
+#define smnPCIE_CI_CNTL                                                                                 0x11180080
 static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
 {
@@ -270,6 +271,12 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
        if (def != data)
                WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
+        def = data = RREG32_PCIE(smnPCIE_CI_CNTL);
+        data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);
+        if (def != data)
+                WREG32_PCIE(smnPCIE_CI_CNTL, data);
 }
 const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index f8cee95d61cc..4cd31a276dcd 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -31,6 +31,7 @@
 #define smnCPM_CONTROL                                                                                  0x11180460
 #define smnPCIE_CNTL2                                                                                   0x11180070
+#define smnPCIE_CI_CNTL                                                                                 0x11180080
 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
 {
@@ -222,7 +223,13 @@ static void nbio_v7_4_detect_hw_virt(struct amdgpu_device *adev)
 static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
 {
+        uint32_t def, data;
+        def = data = RREG32_PCIE(smnPCIE_CI_CNTL);
+        data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);
+        if (def != data)
+                WREG32_PCIE(smnPCIE_CI_CNTL, data);
 }
 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 6c9a1b748ca7..0c6e7f9b143f 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -34,6 +34,7 @@
 #include "nbio/nbio_7_4_offset.h"
 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
+MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
 /* address block */
@@ -100,6 +101,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
        char fw_name[30];
        int err = 0;
        const struct psp_firmware_header_v1_0 *sos_hdr;
+        const struct psp_firmware_header_v1_0 *asd_hdr;
        const struct ta_firmware_header_v1_0 *ta_hdr;
        DRM_DEBUG("\n");
@@ -132,14 +134,30 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
        adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
                                le32_to_cpu(sos_hdr->sos_offset_bytes);
+        snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
+        err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
+        if (err)
+                goto out1;
+        err = amdgpu_ucode_validate(adev->psp.asd_fw);
+        if (err)
+                goto out1;
+        asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
+        adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
+        adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
+        adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
+        adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
+                                le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
        snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
        err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
        if (err)
-                goto out;
+                goto out2;
        err = amdgpu_ucode_validate(adev->psp.ta_fw);
        if (err)
-                goto out;
+                goto out2;
        ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
        adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
@@ -148,14 +166,18 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
                le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
        return 0;
+out2:
+        release_firmware(adev->psp.ta_fw);
+        adev->psp.ta_fw = NULL;
+out1:
+        release_firmware(adev->psp.asd_fw);
+        adev->psp.asd_fw = NULL;
 out:
-        if (err) {
+        dev_err(adev->dev,
-                dev_err(adev->dev,
+                "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
-                        "psp v11.0: Failed to load firmware \"%s\"\n",
+        release_firmware(adev->psp.sos_fw);
-                        fw_name);
+        adev->psp.sos_fw = NULL;
-                release_firmware(adev->psp.sos_fw);
-                adev->psp.sos_fw = NULL;
-        }
        return err;
 }
@@ -291,6 +313,13 @@ static int psp_v11_0_ring_init(struct psp_context *psp,
        return 0;
 }
+static bool psp_v11_0_support_vmr_ring(struct psp_context *psp)
+{
+        if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
+                return true;
+        return false;
+}
 static int psp_v11_0_ring_create(struct psp_context *psp,
                                enum psp_ring_type ring_type)
 {
@@ -299,7 +328,7 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
        struct psp_ring *ring = &psp->km_ring;
        struct amdgpu_device *adev = psp->adev;
-        if (psp_support_vmr_ring(psp)) {
+        if (psp_v11_0_support_vmr_ring(psp)) {
                /* Write low address of the ring to C2PMSG_102 */
                psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
@@ -351,7 +380,7 @@ static int psp_v11_0_ring_stop(struct psp_context *psp,
        struct amdgpu_device *adev = psp->adev;
        /* Write the ring destroy command*/
-        if (psp_support_vmr_ring(psp))
+        if (psp_v11_0_support_vmr_ring(psp))
                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
                                     GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
        else
@@ -362,7 +391,7 @@ static int psp_v11_0_ring_stop(struct psp_context *psp,
        mdelay(20);
        /* Wait for response flag (bit 31) */
-        if (psp_support_vmr_ring(psp))
+        if (psp_v11_0_support_vmr_ring(psp))
                ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
                                   0x80000000, 0x80000000, false);
        else
@@ -406,7 +435,7 @@ static int psp_v11_0_cmd_submit(struct psp_context *psp,
        uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
        /* KM (GPCOM) prepare write pointer */
-        if (psp_support_vmr_ring(psp))
+        if (psp_v11_0_support_vmr_ring(psp))
                psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
        else
                psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
@@ -438,7 +467,7 @@ static int psp_v11_0_cmd_submit(struct psp_context *psp,
        /* Update the write Pointer in DWORDs */
        psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
-        if (psp_support_vmr_ring(psp)) {
+        if (psp_v11_0_support_vmr_ring(psp)) {
                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
        } else
@@ -680,7 +709,7 @@ static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp,
        return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
 }
-static u64 psp_v11_0_xgmi_get_hive_id(struct psp_context *psp)
+static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
 {
        struct ta_xgmi_shared_memory *xgmi_cmd;
        int ret;
@@ -693,12 +722,14 @@ static u64 psp_v11_0_xgmi_get_hive_id(struct psp_context *psp)
        /* Invoke xgmi ta to get hive id */
        ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
        if (ret)
-                return 0;
+                return ret;
-        else
-                return xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
+        *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
+        return 0;
 }
-static u64 psp_v11_0_xgmi_get_node_id(struct psp_context *psp)
+static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
 {
        struct ta_xgmi_shared_memory *xgmi_cmd;
        int ret;
@@ -711,9 +742,11 @@ static u64 psp_v11_0_xgmi_get_node_id(struct psp_context *psp)
        /* Invoke xgmi ta to get the node id */
        ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
        if (ret)
-                return 0;
+                return ret;
-        else
-                return xgmi_cmd->xgmi_out_message.get_node_id.node_id;
+        *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
+        return 0;
 }
 static const struct psp_funcs psp_v11_0_funcs = {
@@ -732,6 +765,7 @@ static const struct psp_funcs psp_v11_0_funcs = {
        .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,
        .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,
        .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id,
+        .support_vmr_ring = psp_v11_0_support_vmr_ring,
 };
 void psp_v11_0_set_psp_funcs(struct psp_context *psp)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 7357fd56e614..79694ff16969 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -240,8 +240,11 @@ static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
         * are already been loaded.
         */
        sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
-        if (sol_reg)
+        if (sol_reg) {
+                psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
+                printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
                return 0;
+        }
        /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 4b6d3e5c821f..fd0bfe140ee0 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1458,8 +1458,7 @@ static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
                /*return fw_version >= 31;*/
                return false;
        case CHIP_VEGA20:
-                /*return fw_version >= 115;*/
+                return fw_version >= 123;
-                return false;
        default:
                return false;
        }
@@ -1706,13 +1705,15 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
                amdgpu_fence_process(&adev->sdma.instance[instance].ring);
                break;
        case 1:
-                /* XXX compute */
+                if (adev->asic_type == CHIP_VEGA20)
+                        amdgpu_fence_process(&adev->sdma.instance[instance].page);
                break;
        case 2:
                /* XXX compute */
                break;
        case 3:
-                amdgpu_fence_process(&adev->sdma.instance[instance].page);
+                if (adev->asic_type != CHIP_VEGA20)
+                        amdgpu_fence_process(&adev->sdma.instance[instance].page);
                break;
        }
        return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index 958b10a57073..49c262540940 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -49,14 +49,19 @@
 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask, ret) \
        do {                                                    \
+                uint32_t old_ = 0;      \
                uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
                uint32_t loop = adev->usec_timeout;             \
                while ((tmp_ & (mask)) != (expected_value)) {   \
-                        udelay(2);                              \
+                        if (old_ != tmp_) {                     \
+                                loop = adev->usec_timeout;      \
+                                old_ = tmp_;                            \
+                        } else                                          \
+                                udelay(1);                              \
                        tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
                        loop--;                                 \
                        if (!loop) {                            \
-                                DRM_ERROR("Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n", \
+                                DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n", \
                                          inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \
                                ret = -ETIMEDOUT;               \
                                break;                          \
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 089645e78f98..aef924026a28 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -435,7 +435,7 @@ static int uvd_v7_0_sw_init(void *handle)
                        continue;
                if (!amdgpu_sriov_vf(adev)) {
                        ring = &adev->uvd.inst[j].ring;
-                        sprintf(ring->name, "uvd<%d>", j);
+                        sprintf(ring->name, "uvd_%d", ring->me);
                        r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
                        if (r)
                                return r;
@@ -443,7 +443,7 @@ static int uvd_v7_0_sw_init(void *handle)
                for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
                        ring = &adev->uvd.inst[j].ring_enc[i];
-                        sprintf(ring->name, "uvd_enc%d<%d>", i, j);
+                        sprintf(ring->name, "uvd_enc_%d.%d", ring->me, i);
                        if (amdgpu_sriov_vf(adev)) {
                                ring->use_doorbell = true;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 4f8352044563..89bb2fef90eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -214,7 +214,8 @@ static int vcn_v1_0_hw_fini(void *handle)
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        struct amdgpu_ring *ring = &adev->vcn.ring_dec;
-        if (RREG32_SOC15(VCN, 0, mmUVD_STATUS))
+        if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
+                RREG32_SOC15(VCN, 0, mmUVD_STATUS))
                vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
        ring->sched.ready = false;
@@ -1087,7 +1088,8 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
                        ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
-        /* initialize wptr */
+        /* initialize JPEG wptr */
+        ring = &adev->vcn.ring_jpeg;
        ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
        /* copy patch commands to the jpeg ring */
@@ -1159,21 +1161,29 @@ static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
 {
        int ret_code = 0;
+        uint32_t tmp;
        /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
        SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
                        UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
                        UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
-        if (!ret_code) {
+        /* wait for read ptr to be equal to write ptr */
-                int tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
+        tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
-                /* wait for read ptr to be equal to write ptr */
+        SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
-                SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
-                SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
+        tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
-                        UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
+        SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);
-                        UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
-        }
+        tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+        SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
+        tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
+        SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
+        SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
+                UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
+                UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
        /* disable dynamic power gating mode */
        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index ff2906c215fa..77e367459101 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -87,9 +87,9 @@ static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
        u32 r;
        spin_lock_irqsave(&adev->pcie_idx_lock, flags);
-        WREG32(mmPCIE_INDEX, reg);
+        WREG32_NO_KIQ(mmPCIE_INDEX, reg);
-        (void)RREG32(mmPCIE_INDEX);
+        (void)RREG32_NO_KIQ(mmPCIE_INDEX);
-        r = RREG32(mmPCIE_DATA);
+        r = RREG32_NO_KIQ(mmPCIE_DATA);
        spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
        return r;
 }
@@ -99,10 +99,10 @@ static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
        unsigned long flags;
        spin_lock_irqsave(&adev->pcie_idx_lock, flags);
-        WREG32(mmPCIE_INDEX, reg);
+        WREG32_NO_KIQ(mmPCIE_INDEX, reg);
-        (void)RREG32(mmPCIE_INDEX);
+        (void)RREG32_NO_KIQ(mmPCIE_INDEX);
-        WREG32(mmPCIE_DATA, v);
+        WREG32_NO_KIQ(mmPCIE_DATA, v);
-        (void)RREG32(mmPCIE_DATA);
+        (void)RREG32_NO_KIQ(mmPCIE_DATA);
        spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 }
@@ -123,8 +123,8 @@ static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
        unsigned long flags;
        spin_lock_irqsave(&adev->smc_idx_lock, flags);
-        WREG32(mmSMC_IND_INDEX_11, (reg));
+        WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
-        WREG32(mmSMC_IND_DATA_11, (v));
+        WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v));
        spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 }