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-rw-r--r--drivers/gpu/drm/amd/amdgpu/Makefile1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h60
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c57
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h89
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c14
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c16
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c18
9 files changed, 160 insertions, 107 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index ec4a9d539322..f76bcb9c45e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -105,6 +105,7 @@ amdgpu-y += \
105# add GFX block 105# add GFX block
106amdgpu-y += \ 106amdgpu-y += \
107 amdgpu_gfx.o \ 107 amdgpu_gfx.o \
108 amdgpu_rlc.o \
108 gfx_v8_0.o \ 109 gfx_v8_0.o \
109 gfx_v9_0.o 110 gfx_v9_0.o
110 111
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 1a656b8657f7..6a70c0b7105f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -25,6 +25,7 @@
25#include <drm/drmP.h> 25#include <drm/drmP.h>
26#include "amdgpu.h" 26#include "amdgpu.h"
27#include "amdgpu_gfx.h" 27#include "amdgpu_gfx.h"
28#include "amdgpu_rlc.h"
28 29
29/* delay 0.1 second to enable gfx off feature */ 30/* delay 0.1 second to enable gfx off feature */
30#define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(100) 31#define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(100)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 0a7c285c0454..f790e15bcd08 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -29,6 +29,7 @@
29 */ 29 */
30#include "clearstate_defs.h" 30#include "clearstate_defs.h"
31#include "amdgpu_ring.h" 31#include "amdgpu_ring.h"
32#include "amdgpu_rlc.h"
32 33
33/* GFX current status */ 34/* GFX current status */
34#define AMDGPU_GFX_NORMAL_MODE 0x00000000L 35#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
@@ -37,65 +38,6 @@
37#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 38#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
38#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 39#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
39 40
40
41struct amdgpu_rlc_funcs {
42 void (*enter_safe_mode)(struct amdgpu_device *adev);
43 void (*exit_safe_mode)(struct amdgpu_device *adev);
44 int (*init)(struct amdgpu_device *adev);
45 void (*fini)(struct amdgpu_device *adev);
46 int (*resume)(struct amdgpu_device *adev);
47 void (*stop)(struct amdgpu_device *adev);
48 void (*reset)(struct amdgpu_device *adev);
49 void (*start)(struct amdgpu_device *adev);
50};
51
52struct amdgpu_rlc {
53 /* for power gating */
54 struct amdgpu_bo *save_restore_obj;
55 uint64_t save_restore_gpu_addr;
56 volatile uint32_t *sr_ptr;
57 const u32 *reg_list;
58 u32 reg_list_size;
59 /* for clear state */
60 struct amdgpu_bo *clear_state_obj;
61 uint64_t clear_state_gpu_addr;
62 volatile uint32_t *cs_ptr;
63 const struct cs_section_def *cs_data;
64 u32 clear_state_size;
65 /* for cp tables */
66 struct amdgpu_bo *cp_table_obj;
67 uint64_t cp_table_gpu_addr;
68 volatile uint32_t *cp_table_ptr;
69 u32 cp_table_size;
70
71 /* safe mode for updating CG/PG state */
72 bool in_safe_mode;
73 const struct amdgpu_rlc_funcs *funcs;
74
75 /* for firmware data */
76 u32 save_and_restore_offset;
77 u32 clear_state_descriptor_offset;
78 u32 avail_scratch_ram_locations;
79 u32 reg_restore_list_size;
80 u32 reg_list_format_start;
81 u32 reg_list_format_separate_start;
82 u32 starting_offsets_start;
83 u32 reg_list_format_size_bytes;
84 u32 reg_list_size_bytes;
85 u32 reg_list_format_direct_reg_list_length;
86 u32 save_restore_list_cntl_size_bytes;
87 u32 save_restore_list_gpm_size_bytes;
88 u32 save_restore_list_srm_size_bytes;
89
90 u32 *register_list_format;
91 u32 *register_restore;
92 u8 *save_restore_list_cntl;
93 u8 *save_restore_list_gpm;
94 u8 *save_restore_list_srm;
95
96 bool is_rlc_v2_1;
97};
98
99#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 41#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
100 42
101struct amdgpu_mec { 43struct amdgpu_mec {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
new file mode 100644
index 000000000000..c5459ab6a31f
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
@@ -0,0 +1,57 @@
1
2/*
3 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 * Copyright 2009 Jerome Glisse.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23 * OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include "amdgpu.h"
28#include "amdgpu_gfx.h"
29#include "amdgpu_rlc.h"
30
31/**
32 * amdgpu_gfx_rlc_fini - Free BO which used for RLC
33 *
34 * @adev: amdgpu_device pointer
35 *
36 * Free three BO which is used for rlc_save_restore_block, rlc_clear_state_block
37 * and rlc_jump_table_block.
38 */
39void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev)
40{
41 /* save restore block */
42 if (adev->gfx.rlc.save_restore_obj) {
43 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj,
44 &adev->gfx.rlc.save_restore_gpu_addr,
45 (void **)&adev->gfx.rlc.sr_ptr);
46 }
47
48 /* clear state block */
49 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
50 &adev->gfx.rlc.clear_state_gpu_addr,
51 (void **)&adev->gfx.rlc.cs_ptr);
52
53 /* jump table block */
54 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
55 &adev->gfx.rlc.cp_table_gpu_addr,
56 (void **)&adev->gfx.rlc.cp_table_ptr);
57}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
new file mode 100644
index 000000000000..b3b092022fc4
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
@@ -0,0 +1,89 @@
1
2/*
3 * Copyright 2014 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25#ifndef __AMDGPU_RLC_H__
26#define __AMDGPU_RLC_H__
27
28#include "clearstate_defs.h"
29
30struct amdgpu_rlc_funcs {
31 void (*enter_safe_mode)(struct amdgpu_device *adev);
32 void (*exit_safe_mode)(struct amdgpu_device *adev);
33 int (*init)(struct amdgpu_device *adev);
34 int (*resume)(struct amdgpu_device *adev);
35 void (*stop)(struct amdgpu_device *adev);
36 void (*reset)(struct amdgpu_device *adev);
37 void (*start)(struct amdgpu_device *adev);
38};
39
40struct amdgpu_rlc {
41 /* for power gating */
42 struct amdgpu_bo *save_restore_obj;
43 uint64_t save_restore_gpu_addr;
44 volatile uint32_t *sr_ptr;
45 const u32 *reg_list;
46 u32 reg_list_size;
47 /* for clear state */
48 struct amdgpu_bo *clear_state_obj;
49 uint64_t clear_state_gpu_addr;
50 volatile uint32_t *cs_ptr;
51 const struct cs_section_def *cs_data;
52 u32 clear_state_size;
53 /* for cp tables */
54 struct amdgpu_bo *cp_table_obj;
55 uint64_t cp_table_gpu_addr;
56 volatile uint32_t *cp_table_ptr;
57 u32 cp_table_size;
58
59 /* safe mode for updating CG/PG state */
60 bool in_safe_mode;
61 const struct amdgpu_rlc_funcs *funcs;
62
63 /* for firmware data */
64 u32 save_and_restore_offset;
65 u32 clear_state_descriptor_offset;
66 u32 avail_scratch_ram_locations;
67 u32 reg_restore_list_size;
68 u32 reg_list_format_start;
69 u32 reg_list_format_separate_start;
70 u32 starting_offsets_start;
71 u32 reg_list_format_size_bytes;
72 u32 reg_list_size_bytes;
73 u32 reg_list_format_direct_reg_list_length;
74 u32 save_restore_list_cntl_size_bytes;
75 u32 save_restore_list_gpm_size_bytes;
76 u32 save_restore_list_srm_size_bytes;
77
78 u32 *register_list_format;
79 u32 *register_restore;
80 u8 *save_restore_list_cntl;
81 u8 *save_restore_list_gpm;
82 u8 *save_restore_list_srm;
83
84 bool is_rlc_v2_1;
85};
86
87void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev);
88
89#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 2082347a374f..192d98490188 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2351,13 +2351,6 @@ static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
2351 amdgpu_ring_write(ring, val); 2351 amdgpu_ring_write(ring, val);
2352} 2352}
2353 2353
2354static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
2355{
2356 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL);
2357 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL);
2358 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL);
2359}
2360
2361static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) 2354static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2362{ 2355{
2363 const u32 *src_ptr; 2356 const u32 *src_ptr;
@@ -2386,7 +2379,7 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2386 if (r) { 2379 if (r) {
2387 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", 2380 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n",
2388 r); 2381 r);
2389 adev->gfx.rlc.funcs->fini(adev); 2382 amdgpu_gfx_rlc_fini(adev);
2390 return r; 2383 return r;
2391 } 2384 }
2392 2385
@@ -2411,7 +2404,7 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2411 (void **)&adev->gfx.rlc.cs_ptr); 2404 (void **)&adev->gfx.rlc.cs_ptr);
2412 if (r) { 2405 if (r) {
2413 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 2406 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2414 adev->gfx.rlc.funcs->fini(adev); 2407 amdgpu_gfx_rlc_fini(adev);
2415 return r; 2408 return r;
2416 } 2409 }
2417 2410
@@ -3060,7 +3053,6 @@ static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
3060 3053
3061static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = { 3054static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = {
3062 .init = gfx_v6_0_rlc_init, 3055 .init = gfx_v6_0_rlc_init,
3063 .fini = gfx_v6_0_rlc_fini,
3064 .resume = gfx_v6_0_rlc_resume, 3056 .resume = gfx_v6_0_rlc_resume,
3065 .stop = gfx_v6_0_rlc_stop, 3057 .stop = gfx_v6_0_rlc_stop,
3066 .reset = gfx_v6_0_rlc_reset, 3058 .reset = gfx_v6_0_rlc_reset,
@@ -3158,7 +3150,7 @@ static int gfx_v6_0_sw_fini(void *handle)
3158 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3150 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3159 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 3151 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
3160 3152
3161 adev->gfx.rlc.funcs->fini(adev); 3153 amdgpu_gfx_rlc_fini(adev);
3162 3154
3163 return 0; 3155 return 0;
3164} 3156}
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index d8e2ad875cfe..8097534aa6c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3252,13 +3252,6 @@ static void gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
3252 * The RLC is a multi-purpose microengine that handles a 3252 * The RLC is a multi-purpose microengine that handles a
3253 * variety of functions. 3253 * variety of functions.
3254 */ 3254 */
3255static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3256{
3257 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL);
3258 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL);
3259 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL);
3260}
3261
3262static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) 3255static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3263{ 3256{
3264 const u32 *src_ptr; 3257 const u32 *src_ptr;
@@ -3298,7 +3291,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3298 (void **)&adev->gfx.rlc.sr_ptr); 3291 (void **)&adev->gfx.rlc.sr_ptr);
3299 if (r) { 3292 if (r) {
3300 dev_warn(adev->dev, "(%d) create, pin or map of RLC sr bo failed\n", r); 3293 dev_warn(adev->dev, "(%d) create, pin or map of RLC sr bo failed\n", r);
3301 adev->gfx.rlc.funcs->fini(adev); 3294 amdgpu_gfx_rlc_fini(adev);
3302 return r; 3295 return r;
3303 } 3296 }
3304 3297
@@ -3321,7 +3314,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3321 (void **)&adev->gfx.rlc.cs_ptr); 3314 (void **)&adev->gfx.rlc.cs_ptr);
3322 if (r) { 3315 if (r) {
3323 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 3316 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3324 adev->gfx.rlc.funcs->fini(adev); 3317 amdgpu_gfx_rlc_fini(adev);
3325 return r; 3318 return r;
3326 } 3319 }
3327 3320
@@ -3341,7 +3334,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3341 (void **)&adev->gfx.rlc.cp_table_ptr); 3334 (void **)&adev->gfx.rlc.cp_table_ptr);
3342 if (r) { 3335 if (r) {
3343 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r); 3336 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3344 adev->gfx.rlc.funcs->fini(adev); 3337 amdgpu_gfx_rlc_fini(adev);
3345 return r; 3338 return r;
3346 } 3339 }
3347 3340
@@ -4275,7 +4268,6 @@ static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
4275 .enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode, 4268 .enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode,
4276 .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode, 4269 .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode,
4277 .init = gfx_v7_0_rlc_init, 4270 .init = gfx_v7_0_rlc_init,
4278 .fini = gfx_v7_0_rlc_fini,
4279 .resume = gfx_v7_0_rlc_resume, 4271 .resume = gfx_v7_0_rlc_resume,
4280 .stop = gfx_v7_0_rlc_stop, 4272 .stop = gfx_v7_0_rlc_stop,
4281 .reset = gfx_v7_0_rlc_reset, 4273 .reset = gfx_v7_0_rlc_reset,
@@ -4594,7 +4586,7 @@ static int gfx_v7_0_sw_fini(void *handle)
4594 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4586 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4595 4587
4596 gfx_v7_0_cp_compute_fini(adev); 4588 gfx_v7_0_cp_compute_fini(adev);
4597 adev->gfx.rlc.funcs->fini(adev); 4589 amdgpu_gfx_rlc_fini(adev);
4598 gfx_v7_0_mec_fini(adev); 4590 gfx_v7_0_mec_fini(adev);
4599 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4591 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4600 &adev->gfx.rlc.clear_state_gpu_addr, 4592 &adev->gfx.rlc.clear_state_gpu_addr,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 7dbcb2ea20fd..81a308bac230 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1348,12 +1348,6 @@ static void cz_init_cp_jump_table(struct amdgpu_device *adev)
1348 } 1348 }
1349} 1349}
1350 1350
1351static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev)
1352{
1353 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL);
1354 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL);
1355}
1356
1357static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) 1351static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1358{ 1352{
1359 volatile u32 *dst_ptr; 1353 volatile u32 *dst_ptr;
@@ -1376,7 +1370,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1376 (void **)&adev->gfx.rlc.cs_ptr); 1370 (void **)&adev->gfx.rlc.cs_ptr);
1377 if (r) { 1371 if (r) {
1378 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 1372 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
1379 adev->gfx.rlc.funcs->fini(adev); 1373 amdgpu_gfx_rlc_fini(adev);
1380 return r; 1374 return r;
1381 } 1375 }
1382 1376
@@ -2166,7 +2160,7 @@ static int gfx_v8_0_sw_fini(void *handle)
2166 amdgpu_gfx_kiq_fini(adev); 2160 amdgpu_gfx_kiq_fini(adev);
2167 2161
2168 gfx_v8_0_mec_fini(adev); 2162 gfx_v8_0_mec_fini(adev);
2169 adev->gfx.rlc.funcs->fini(adev); 2163 amdgpu_gfx_rlc_fini(adev);
2170 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 2164 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
2171 &adev->gfx.rlc.clear_state_gpu_addr, 2165 &adev->gfx.rlc.clear_state_gpu_addr,
2172 (void **)&adev->gfx.rlc.cs_ptr); 2166 (void **)&adev->gfx.rlc.cs_ptr);
@@ -5634,7 +5628,6 @@ static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
5634 .enter_safe_mode = iceland_enter_rlc_safe_mode, 5628 .enter_safe_mode = iceland_enter_rlc_safe_mode,
5635 .exit_safe_mode = iceland_exit_rlc_safe_mode, 5629 .exit_safe_mode = iceland_exit_rlc_safe_mode,
5636 .init = gfx_v8_0_rlc_init, 5630 .init = gfx_v8_0_rlc_init,
5637 .fini = gfx_v8_0_rlc_fini,
5638 .resume = gfx_v8_0_rlc_resume, 5631 .resume = gfx_v8_0_rlc_resume,
5639 .stop = gfx_v8_0_rlc_stop, 5632 .stop = gfx_v8_0_rlc_stop,
5640 .reset = gfx_v8_0_rlc_reset, 5633 .reset = gfx_v8_0_rlc_reset,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ae720851974f..84831839070c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1112,19 +1112,6 @@ static void rv_init_cp_jump_table(struct amdgpu_device *adev)
1112 } 1112 }
1113} 1113}
1114 1114
1115static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
1116{
1117 /* clear state block */
1118 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
1119 &adev->gfx.rlc.clear_state_gpu_addr,
1120 (void **)&adev->gfx.rlc.cs_ptr);
1121
1122 /* jump table block */
1123 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
1124 &adev->gfx.rlc.cp_table_gpu_addr,
1125 (void **)&adev->gfx.rlc.cp_table_ptr);
1126}
1127
1128static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) 1115static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
1129{ 1116{
1130 volatile u32 *dst_ptr; 1117 volatile u32 *dst_ptr;
@@ -1147,7 +1134,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
1147 if (r) { 1134 if (r) {
1148 dev_err(adev->dev, "(%d) failed to create rlc csb bo\n", 1135 dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
1149 r); 1136 r);
1150 adev->gfx.rlc.funcs->fini(adev); 1137 amdgpu_gfx_rlc_fini(adev);
1151 return r; 1138 return r;
1152 } 1139 }
1153 /* set up the cs buffer */ 1140 /* set up the cs buffer */
@@ -1169,7 +1156,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
1169 if (r) { 1156 if (r) {
1170 dev_err(adev->dev, 1157 dev_err(adev->dev,
1171 "(%d) failed to create cp table bo\n", r); 1158 "(%d) failed to create cp table bo\n", r);
1172 adev->gfx.rlc.funcs->fini(adev); 1159 amdgpu_gfx_rlc_fini(adev);
1173 return r; 1160 return r;
1174 } 1161 }
1175 1162
@@ -3884,7 +3871,6 @@ static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3884 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode, 3871 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3885 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode, 3872 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode,
3886 .init = gfx_v9_0_rlc_init, 3873 .init = gfx_v9_0_rlc_init,
3887 .fini = gfx_v9_0_rlc_fini,
3888 .resume = gfx_v9_0_rlc_resume, 3874 .resume = gfx_v9_0_rlc_resume,
3889 .stop = gfx_v9_0_rlc_stop, 3875 .stop = gfx_v9_0_rlc_stop,
3890 .reset = gfx_v9_0_rlc_reset, 3876 .reset = gfx_v9_0_rlc_reset,
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-26 10:43:10 -0400