16 files changed, 183 insertions, 89 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
index a028661d9e20..92b11de19581 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
@@ -576,6 +576,7 @@ static const struct amdgpu_px_quirk amdgpu_px_quirk_list[] = {
         { 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },
         { 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },
         { 0x1002, 0x6900, 0x1025, 0x125A, AMDGPU_PX_QUIRK_FORCE_ATPX },
+        { 0x1002, 0x6900, 0x17AA, 0x3806, AMDGPU_PX_QUIRK_FORCE_ATPX },
         { 0, 0, 0, 0, 0 },
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 8a078f4ae73d..7ff3a28fc903 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1701,8 +1701,10 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
                 amdgpu_xgmi_add_device(adev);
         amdgpu_amdkfd_device_init(adev);
 
-        if (amdgpu_sriov_vf(adev))
+        if (amdgpu_sriov_vf(adev)) {
+                amdgpu_virt_init_data_exchange(adev);
                 amdgpu_virt_release_full_gpu(adev, true);
+        }
 
         return 0;
 }
@@ -2632,9 +2634,6 @@ fence_driver_init:
                 goto failed;
         }
 
-        if (amdgpu_sriov_vf(adev))
-                amdgpu_virt_init_data_exchange(adev);
-
         amdgpu_fbdev_init(adev);
 
         r = amdgpu_pm_sysfs_init(adev);
@@ -2798,7 +2797,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
                         struct drm_framebuffer *fb = crtc->primary->fb;
                         struct amdgpu_bo *robj;
 
-                        if (amdgpu_crtc->cursor_bo) {
+                        if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
                                 r = amdgpu_bo_reserve(aobj, true);
                                 if (r == 0) {
@@ -2906,7 +2905,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 
-                        if (amdgpu_crtc->cursor_bo) {
+                        if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
                                 r = amdgpu_bo_reserve(aobj, true);
                                 if (r == 0) {
@@ -3226,6 +3225,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
         r = amdgpu_ib_ring_tests(adev);
 
 error:
+        amdgpu_virt_init_data_exchange(adev);
         amdgpu_virt_release_full_gpu(adev, true);
         if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
                 atomic_inc(&adev->vram_lost_counter);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 15ce7e681d67..b083b219b1a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -188,10 +188,12 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
                 goto cleanup;
         }
 
-        r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev));
-        if (unlikely(r != 0)) {
-                DRM_ERROR("failed to pin new abo buffer before flip\n");
-                goto unreserve;
+        if (!adev->enable_virtual_display) {
+                r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev));
+                if (unlikely(r != 0)) {
+                        DRM_ERROR("failed to pin new abo buffer before flip\n");
+                        goto unreserve;
+                }
         }
 
         r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
@@ -211,7 +213,8 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
         amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
         amdgpu_bo_unreserve(new_abo);
 
-        work->base = amdgpu_bo_gpu_offset(new_abo);
+        if (!adev->enable_virtual_display)
+                work->base = amdgpu_bo_gpu_offset(new_abo);
         work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
                 amdgpu_get_vblank_counter_kms(dev, work->crtc_id);
 
@@ -242,9 +245,10 @@ pflip_cleanup:
                 goto cleanup;
         }
 unpin:
-        if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) {
-                DRM_ERROR("failed to unpin new abo in error path\n");
-        }
+        if (!adev->enable_virtual_display)
+                if (unlikely(amdgpu_bo_unpin(new_abo) != 0))
+                        DRM_ERROR("failed to unpin new abo in error path\n");
+
 unreserve:
         amdgpu_bo_unreserve(new_abo);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index bc62bf41b7e9..5dc349173e4f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -212,6 +212,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
         }
 
         if (amdgpu_device_is_px(dev)) {
+                dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);
                 pm_runtime_use_autosuspend(dev->dev);
                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
                 pm_runtime_set_active(dev->dev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 1f61ed95727c..0ed41a9d2d77 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1686,7 +1686,8 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
                 effective_mode &= ~S_IWUSR;
 
         if ((adev->flags & AMD_IS_APU) &&
-            (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
+            (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
+             attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
                 return 0;
@@ -2008,6 +2009,7 @@ void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
 
 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 {
+        struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
         int ret;
 
         if (adev->pm.sysfs_initialized)
@@ -2091,12 +2093,14 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
                                 "pp_power_profile_mode\n");
                 return ret;
         }
-        ret = device_create_file(adev->dev,
-                        &dev_attr_pp_od_clk_voltage);
-        if (ret) {
-                DRM_ERROR("failed to create device file "
-                                "pp_od_clk_voltage\n");
-                return ret;
+        if (hwmgr->od_enabled) {
+                ret = device_create_file(adev->dev,
+                                &dev_attr_pp_od_clk_voltage);
+                if (ret) {
+                        DRM_ERROR("failed to create device file "
+                                        "pp_od_clk_voltage\n");
+                        return ret;
+                }
         }
         ret = device_create_file(adev->dev,
                         &dev_attr_gpu_busy_percent);
@@ -2118,6 +2122,8 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 
 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 {
+        struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
+
         if (adev->pm.dpm_enabled == 0)
                 return;
 
@@ -2138,8 +2144,9 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
         device_remove_file(adev->dev,
                         &dev_attr_pp_power_profile_mode);
-        device_remove_file(adev->dev,
-                        &dev_attr_pp_od_clk_voltage);
+        if (hwmgr->od_enabled)
+                device_remove_file(adev->dev,
+                                &dev_attr_pp_od_clk_voltage);
         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
index 71913a18d142..a38e0fb4a6fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
@@ -38,6 +38,7 @@
 #include "amdgpu_gem.h"
 #include <drm/amdgpu_drm.h>
 #include <linux/dma-buf.h>
+#include <linux/dma-fence-array.h>
 
 /**
  * amdgpu_gem_prime_get_sg_table - &drm_driver.gem_prime_get_sg_table
@@ -187,6 +188,48 @@ error:
         return ERR_PTR(ret);
 }
 
+static int
+__reservation_object_make_exclusive(struct reservation_object *obj)
+{
+        struct dma_fence **fences;
+        unsigned int count;
+        int r;
+
+        if (!reservation_object_get_list(obj)) /* no shared fences to convert */
+                return 0;
+
+        r = reservation_object_get_fences_rcu(obj, NULL, &count, &fences);
+        if (r)
+                return r;
+
+        if (count == 0) {
+                /* Now that was unexpected. */
+        } else if (count == 1) {
+                reservation_object_add_excl_fence(obj, fences[0]);
+                dma_fence_put(fences[0]);
+                kfree(fences);
+        } else {
+                struct dma_fence_array *array;
+
+                array = dma_fence_array_create(count, fences,
+                                               dma_fence_context_alloc(1), 0,
+                                               false);
+                if (!array)
+                        goto err_fences_put;
+
+                reservation_object_add_excl_fence(obj, &array->base);
+                dma_fence_put(&array->base);
+        }
+
+        return 0;
+
+err_fences_put:
+        while (count--)
+                dma_fence_put(fences[count]);
+        kfree(fences);
+        return -ENOMEM;
+}
+
 /**
  * amdgpu_gem_map_attach - &dma_buf_ops.attach implementation
  * @dma_buf: Shared DMA buffer
@@ -218,16 +261,16 @@ static int amdgpu_gem_map_attach(struct dma_buf *dma_buf,
 
         if (attach->dev->driver != adev->dev->driver) {
                 /*
-                 * Wait for all shared fences to complete before we switch to future
-                 * use of exclusive fence on this prime shared bo.
+                 * We only create shared fences for internal use, but importers
+                 * of the dmabuf rely on exclusive fences for implicitly
+                 * tracking write hazards. As any of the current fences may
+                 * correspond to a write, we need to convert all existing
+                 * fences on the reservation object into a single exclusive
+                 * fence.
                  */
-                r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
-                                                        true, false,
-                                                        MAX_SCHEDULE_TIMEOUT);
-                if (unlikely(r < 0)) {
-                        DRM_DEBUG_PRIME("Fence wait failed: %li\n", r);
+                r = __reservation_object_make_exclusive(bo->tbo.resv);
+                if (r)
                         goto error_unreserve;
-                }
         }
 
         /* pin buffer into GTT */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 8fab0d637ee5..3a9b48b227ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -90,8 +90,10 @@ static int psp_sw_fini(void *handle)
         adev->psp.sos_fw = NULL;
         release_firmware(adev->psp.asd_fw);
         adev->psp.asd_fw = NULL;
-        release_firmware(adev->psp.ta_fw);
-        adev->psp.ta_fw = NULL;
+        if (adev->psp.ta_fw) {
+                release_firmware(adev->psp.ta_fw);
+                adev->psp.ta_fw = NULL;
+        }
         return 0;
 }
 
@@ -435,6 +437,9 @@ static int psp_xgmi_initialize(struct psp_context *psp)
         struct ta_xgmi_shared_memory *xgmi_cmd;
         int ret;
 
+        if (!psp->adev->psp.ta_fw)
+                return -ENOENT;
+
         if (!psp->xgmi_context.initialized) {
                 ret = psp_xgmi_init_shared_buf(psp);
                 if (ret)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index e73d152659a2..698bcb8ce61d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -638,12 +638,14 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
         struct ttm_bo_global *glob = adev->mman.bdev.glob;
         struct amdgpu_vm_bo_base *bo_base;
 
+#if 0
         if (vm->bulk_moveable) {
                 spin_lock(&glob->lru_lock);
                 ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
                 spin_unlock(&glob->lru_lock);
                 return;
         }
+#endif
 
         memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
 
@@ -847,9 +849,6 @@ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
         bp->size = amdgpu_vm_bo_size(adev, level);
         bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
         bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
-        if (bp->size <= PAGE_SIZE && adev->asic_type >= CHIP_VEGA10 &&
-            adev->flags & AMD_IS_APU)
-                bp->domain |= AMDGPU_GEM_DOMAIN_GTT;
         bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
         bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
                 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
@@ -3366,14 +3365,15 @@ void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
                          struct amdgpu_task_info *task_info)
 {
         struct amdgpu_vm *vm;
+        unsigned long flags;
 
-        spin_lock(&adev->vm_manager.pasid_lock);
+        spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
 
         vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
         if (vm)
                 *task_info = vm->task_info;
 
-        spin_unlock(&adev->vm_manager.pasid_lock);
+        spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index fdace004544d..e4cc1d48eaab 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -167,19 +167,6 @@ static void dce_virtual_crtc_disable(struct drm_crtc *crtc)
         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 
         dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
-        if (crtc->primary->fb) {
-                int r;
-                struct amdgpu_bo *abo;
-
-                abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
-                r = amdgpu_bo_reserve(abo, true);
-                if (unlikely(r))
-                        DRM_ERROR("failed to reserve abo before unpin\n");
-                else {
-                        amdgpu_bo_unpin(abo);
-                        amdgpu_bo_unreserve(abo);
-                }
-        }
 
         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
         amdgpu_crtc->encoder = NULL;
@@ -692,7 +679,9 @@ static int dce_virtual_pageflip(struct amdgpu_device *adev,
         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 
         drm_crtc_vblank_put(&amdgpu_crtc->base);
-        schedule_work(&works->unpin_work);
+        amdgpu_bo_unref(&works->old_abo);
+        kfree(works->shared);
+        kfree(works);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 381f593b0cda..57cb3a51bda7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4233,7 +4233,6 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
         u32 tmp;
         u32 rb_bufsz;
         u64 rb_addr, rptr_addr, wptr_gpu_addr;
-        int r;
 
         /* Set the write pointer delay */
         WREG32(mmCP_RB_WPTR_DELAY, 0);
@@ -4278,9 +4277,8 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
         amdgpu_ring_clear_ring(ring);
         gfx_v8_0_cp_gfx_start(adev);
         ring->sched.ready = true;
-        r = amdgpu_ring_test_helper(ring);
 
-        return r;
+        return 0;
 }
 
 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
@@ -4369,10 +4367,9 @@ static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)
                 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
         }
 
-        r = amdgpu_ring_test_helper(kiq_ring);
-        if (r)
-                DRM_ERROR("KCQ enable failed\n");
-        return r;
+        amdgpu_ring_commit(kiq_ring);
+
+        return 0;
 }
 
 static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req)
@@ -4709,16 +4706,32 @@ static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev)
         if (r)
                 goto done;
 
-        /* Test KCQs - reversing the order of rings seems to fix ring test failure
-         * after GPU reset
-         */
-        for (i = adev->gfx.num_compute_rings - 1; i >= 0; i--) {
+done:
+        return r;
+}
+
+static int gfx_v8_0_cp_test_all_rings(struct amdgpu_device *adev)
+{
+        int r, i;
+        struct amdgpu_ring *ring;
+
+        /* collect all the ring_tests here, gfx, kiq, compute */
+        ring = &adev->gfx.gfx_ring[0];
+        r = amdgpu_ring_test_helper(ring);
+        if (r)
+                return r;
+
+        ring = &adev->gfx.kiq.ring;
+        r = amdgpu_ring_test_helper(ring);
+        if (r)
+                return r;
+
+        for (i = 0; i < adev->gfx.num_compute_rings; i++) {
                 ring = &adev->gfx.compute_ring[i];
-                r = amdgpu_ring_test_helper(ring);
+                amdgpu_ring_test_helper(ring);
         }
 
-done:
-        return r;
+        return 0;
 }
 
 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
@@ -4739,6 +4752,11 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
         r = gfx_v8_0_kcq_resume(adev);
         if (r)
                 return r;
+
+        r = gfx_v8_0_cp_test_all_rings(adev);
+        if (r)
+                return r;
+
         gfx_v8_0_enable_gui_idle_interrupt(adev, true);
 
         return 0;
@@ -5086,6 +5104,8 @@ static int gfx_v8_0_post_soft_reset(void *handle)
             REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
                 gfx_v8_0_cp_gfx_resume(adev);
 
+        gfx_v8_0_cp_test_all_rings(adev);
+
         adev->gfx.rlc.funcs->start(adev);
 
         return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 7556716038d3..fbca0494f871 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -113,7 +113,10 @@ static const struct soc15_reg_golden golden_settings_gc_9_0[] =
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
 };
 
 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
@@ -135,10 +138,7 @@ static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
 };
 
 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
@@ -3587,6 +3587,8 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
 {
         uint32_t data, def;
 
+        amdgpu_gfx_rlc_enter_safe_mode(adev);
+
         /* It is disabled by HW by default */
         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
@@ -3651,6 +3653,8 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
                 }
         }
+
+        amdgpu_gfx_rlc_exit_safe_mode(adev);
 }
 
 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
index 8cbb4655896a..b11a1c17a7f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -174,7 +174,7 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,
                         return r;
                 }
                 /* Retrieve checksum from mailbox2 */
-                if (req == IDH_REQ_GPU_INIT_ACCESS) {
+                if (req == IDH_REQ_GPU_INIT_ACCESS || req == IDH_REQ_GPU_RESET_ACCESS) {
                         adev->virt.fw_reserve.checksum_key =
                                 RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
                                         mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2));
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 4cd31a276dcd..186db182f924 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -93,7 +93,20 @@ static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev,
 static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
                                                         bool enable)
 {
+        u32 tmp = 0;
 
+        if (enable) {
+                tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
+                      REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
+                      REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
+
+                WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW,
+                             lower_32_bits(adev->doorbell.base));
+                WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH,
+                             upper_32_bits(adev->doorbell.base));
+        }
+
+        WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp);
 }
 
 static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 0c6e7f9b143f..189fcb004579 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -152,18 +152,22 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
 
         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
         err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
-        if (err)
-                goto out2;
-
-        err = amdgpu_ucode_validate(adev->psp.ta_fw);
-        if (err)
-                goto out2;
-
-        ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
-        adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
-        adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
-        adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
-                le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
+        if (err) {
+                release_firmware(adev->psp.ta_fw);
+                adev->psp.ta_fw = NULL;
+                dev_info(adev->dev,
+                         "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
+        } else {
+                err = amdgpu_ucode_validate(adev->psp.ta_fw);
+                if (err)
+                        goto out2;
+
+                ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
+                adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
+                adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
+                adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
+                        le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
+        }
 
         return 0;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index fd0bfe140ee0..aa2f71cc1eba 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -78,7 +78,6 @@ static const struct soc15_reg_golden golden_settings_sdma_4[] = {
         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
-        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
@@ -96,6 +95,7 @@ static const struct soc15_reg_golden golden_settings_sdma_4[] = {
 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
+        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002)
 };
@@ -103,6 +103,7 @@ static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
+        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001)
 };
@@ -127,7 +128,7 @@ static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = {
 
 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
 {
-        SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
+        SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
@@ -157,7 +158,7 @@ static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
 };
 
 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
-        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
+        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 8849b74078d6..9b639974c70c 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -729,11 +729,13 @@ static int soc15_common_early_init(void *handle)
         case CHIP_RAVEN:
                 adev->asic_funcs = &soc15_asic_funcs;
                 if (adev->rev_id >= 0x8)
-                        adev->external_rev_id = adev->rev_id + 0x81;
+                        adev->external_rev_id = adev->rev_id + 0x79;
                 else if (adev->pdev->device == 0x15d8)
                         adev->external_rev_id = adev->rev_id + 0x41;
+                else if (adev->rev_id == 1)
+                        adev->external_rev_id = adev->rev_id + 0x20;
                 else
-                        adev->external_rev_id = 0x1;
+                        adev->external_rev_id = adev->rev_id + 0x01;
 
                 if (adev->rev_id >= 0x8) {
                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |