1 files changed, 104 insertions, 77 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 700c56baf2de..72c68dbb9821 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -51,11 +51,13 @@
 #include "amdgpu_ih.h"
 #include "amdgpu_irq.h"
 #include "amdgpu_ucode.h"
+#include "amdgpu_ttm.h"
 #include "amdgpu_gds.h"
 #include "amd_powerplay.h"
 #include "amdgpu_acp.h"
 
 #include "gpu_scheduler.h"
+#include "amdgpu_virt.h"
 
 /*
  * Modules parameters.
@@ -63,6 +65,7 @@
 extern int amdgpu_modeset;
 extern int amdgpu_vram_limit;
 extern int amdgpu_gart_size;
+extern int amdgpu_moverate;
 extern int amdgpu_benchmarking;
 extern int amdgpu_testing;
 extern int amdgpu_audio;
@@ -91,6 +94,9 @@ extern unsigned amdgpu_pcie_lane_cap;
 extern unsigned amdgpu_cg_mask;
 extern unsigned amdgpu_pg_mask;
 extern char *amdgpu_disable_cu;
+extern int amdgpu_sclk_deep_sleep_en;
+extern char *amdgpu_virtual_display;
+extern unsigned amdgpu_pp_feature_mask;
 
 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS          3000
 #define AMDGPU_MAX_USEC_TIMEOUT                 100000  /* 100 ms */
@@ -105,7 +111,7 @@ extern char *amdgpu_disable_cu;
 #define AMDGPU_MAX_RINGS                        16
 #define AMDGPU_MAX_GFX_RINGS                    1
 #define AMDGPU_MAX_COMPUTE_RINGS                8
-#define AMDGPU_MAX_VCE_RINGS                    2
+#define AMDGPU_MAX_VCE_RINGS                    3
 
 /* max number of IP instances */
 #define AMDGPU_MAX_SDMA_INSTANCES               2
@@ -248,10 +254,9 @@ struct amdgpu_vm_pte_funcs {
                          uint64_t pe, uint64_t src,
                          unsigned count);
         /* write pte one entry at a time with addr mapping */
-        void (*write_pte)(struct amdgpu_ib *ib,
-                          const dma_addr_t *pages_addr, uint64_t pe,
-                          uint64_t addr, unsigned count,
-                          uint32_t incr, uint32_t flags);
+        void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
+                          uint64_t value, unsigned count,
+                          uint32_t incr);
         /* for linear pte/pde updates without addr mapping */
         void (*set_pte_pde)(struct amdgpu_ib *ib,
                             uint64_t pe,
@@ -316,6 +321,10 @@ struct amdgpu_ring_funcs {
         /* note usage for clock and power gating */
         void (*begin_use)(struct amdgpu_ring *ring);
         void (*end_use)(struct amdgpu_ring *ring);
+        void (*emit_switch_buffer) (struct amdgpu_ring *ring);
+        void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
+        unsigned (*get_emit_ib_size) (struct amdgpu_ring *ring);
+        unsigned (*get_dma_frame_size) (struct amdgpu_ring *ring);
 };
 
 /*
@@ -396,48 +405,8 @@ int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
 
 /*
- * TTM.
+ * BO.
  */
-
-#define AMDGPU_TTM_LRU_SIZE     20
-
-struct amdgpu_mman_lru {
-        struct list_head                *lru[TTM_NUM_MEM_TYPES];
-        struct list_head                *swap_lru;
-};
-
-struct amdgpu_mman {
-        struct ttm_bo_global_ref        bo_global_ref;
-        struct drm_global_reference     mem_global_ref;
-        struct ttm_bo_device            bdev;
-        bool                            mem_global_referenced;
-        bool                            initialized;
-
-#if defined(CONFIG_DEBUG_FS)
-        struct dentry                   *vram;
-        struct dentry                   *gtt;
-#endif
-
-        /* buffer handling */
-        const struct amdgpu_buffer_funcs        *buffer_funcs;
-        struct amdgpu_ring                      *buffer_funcs_ring;
-        /* Scheduler entity for buffer moves */
-        struct amd_sched_entity                 entity;
-
-        /* custom LRU management */
-        struct amdgpu_mman_lru                  log2_size[AMDGPU_TTM_LRU_SIZE];
-        /* guard for log2_size array, don't add anything in between */
-        struct amdgpu_mman_lru                  guard;
-};
-
-int amdgpu_copy_buffer(struct amdgpu_ring *ring,
-                       uint64_t src_offset,
-                       uint64_t dst_offset,
-                       uint32_t byte_count,
-                       struct reservation_object *resv,
-                       struct fence **fence);
-int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
-
 struct amdgpu_bo_list_entry {
         struct amdgpu_bo                *robj;
         struct ttm_validate_buffer      tv;
@@ -500,10 +469,12 @@ struct amdgpu_bo {
         struct amdgpu_device            *adev;
         struct drm_gem_object           gem_base;
         struct amdgpu_bo                *parent;
+        struct amdgpu_bo                *shadow;
 
         struct ttm_bo_kmap_obj          dma_buf_vmap;
         struct amdgpu_mn                *mn;
         struct list_head                mn_list;
+        struct list_head                shadow_list;
 };
 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
 
@@ -653,6 +624,7 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
                      int pages, struct page **pagelist,
                      dma_addr_t *dma_addr, uint32_t flags);
+int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
 
 /*
  * GPU MC structures, functions & helpers
@@ -679,6 +651,8 @@ struct amdgpu_mc {
         uint32_t                fw_version;
         struct amdgpu_irq_src   vm_fault;
         uint32_t                vram_type;
+        uint32_t                srbm_soft_reset;
+        struct amdgpu_mode_mc_save save;
 };
 
 /*
@@ -723,10 +697,11 @@ void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
  */
 
 struct amdgpu_flip_work {
-        struct work_struct              flip_work;
+        struct delayed_work             flip_work;
         struct work_struct              unpin_work;
         struct amdgpu_device            *adev;
         int                             crtc_id;
+        u32                             target_vblank;
         uint64_t                        base;
         struct drm_pending_vblank_event *event;
         struct amdgpu_bo                *old_rbo;
@@ -817,13 +792,17 @@ struct amdgpu_ring {
 /* maximum number of VMIDs */
 #define AMDGPU_NUM_VM   16
 
+/* Maximum number of PTEs the hardware can write with one command */
+#define AMDGPU_VM_MAX_UPDATE_SIZE       0x3FFFF
+
 /* number of entries in page table */
 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
 
 /* PTBs (Page Table Blocks) need to be aligned to 32K */
 #define AMDGPU_VM_PTB_ALIGN_SIZE   32768
-#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
-#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
+
+/* LOG2 number of continuous pages for the fragment field */
+#define AMDGPU_LOG2_PAGES_PER_FRAG 4
 
 #define AMDGPU_PTE_VALID        (1 << 0)
 #define AMDGPU_PTE_SYSTEM       (1 << 1)
@@ -835,10 +814,7 @@ struct amdgpu_ring {
 #define AMDGPU_PTE_READABLE     (1 << 5)
 #define AMDGPU_PTE_WRITEABLE    (1 << 6)
 
-/* PTE (Page Table Entry) fragment field for different page sizes */
-#define AMDGPU_PTE_FRAG_4KB     (0 << 7)
-#define AMDGPU_PTE_FRAG_64KB    (4 << 7)
-#define AMDGPU_LOG2_PAGES_PER_FRAG 4
+#define AMDGPU_PTE_FRAG(x)      ((x & 0x1f) << 7)
 
 /* How to programm VM fault handling */
 #define AMDGPU_VM_FAULT_STOP_NEVER      0
@@ -848,6 +824,7 @@ struct amdgpu_ring {
 struct amdgpu_vm_pt {
         struct amdgpu_bo_list_entry     entry;
         uint64_t                        addr;
+        uint64_t                        shadow_addr;
 };
 
 struct amdgpu_vm {
@@ -950,7 +927,6 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
                       struct amdgpu_job *job);
 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job);
 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
-uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
                                     struct amdgpu_vm *vm);
 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
@@ -959,7 +935,7 @@ int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
                              struct amdgpu_sync *sync);
 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
                         struct amdgpu_bo_va *bo_va,
-                        struct ttm_mem_reg *mem);
+                        bool clear);
 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
                              struct amdgpu_bo *bo);
 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
@@ -994,6 +970,7 @@ struct amdgpu_ctx {
         spinlock_t              ring_lock;
         struct fence            **fences;
         struct amdgpu_ctx_ring  rings[AMDGPU_MAX_RINGS];
+        bool preamble_presented;
 };
 
 struct amdgpu_ctx_mgr {
@@ -1197,6 +1174,10 @@ struct amdgpu_gfx {
         unsigned                        ce_ram_size;
         struct amdgpu_cu_info           cu_info;
         const struct amdgpu_gfx_funcs   *funcs;
+
+        /* reset mask */
+        uint32_t                        grbm_soft_reset;
+        uint32_t                        srbm_soft_reset;
 };
 
 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
@@ -1249,11 +1230,16 @@ struct amdgpu_cs_parser {
         struct fence                    *fence;
         uint64_t                        bytes_moved_threshold;
         uint64_t                        bytes_moved;
+        struct amdgpu_bo_list_entry     *evictable;
 
         /* user fence */
         struct amdgpu_bo_list_entry     uf_entry;
 };
 
+#define AMDGPU_PREAMBLE_IB_PRESENT          (1 << 0) /* bit set means command submit involves a preamble IB */
+#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST    (1 << 1) /* bit set means preamble IB is first presented in belonging context */
+#define AMDGPU_HAVE_CTX_SWITCH              (1 << 2) /* bit set means context switch occured */
+
 struct amdgpu_job {
         struct amd_sched_job    base;
         struct amdgpu_device    *adev;
@@ -1262,9 +1248,10 @@ struct amdgpu_job {
         struct amdgpu_sync      sync;
         struct amdgpu_ib        *ibs;
         struct fence            *fence; /* the hw fence */
+        uint32_t                preamble_status;
         uint32_t                num_ibs;
         void                    *owner;
-        uint64_t                ctx;
+        uint64_t                fence_ctx; /* the fence_context this job uses */
         bool                    vm_needs_flush;
         unsigned                vm_id;
         uint64_t                vm_pd_addr;
@@ -1685,6 +1672,7 @@ struct amdgpu_uvd {
         bool                    address_64_bit;
         bool                    use_ctx_buf;
         struct amd_sched_entity entity;
+        uint32_t                srbm_soft_reset;
 };
 
 /*
@@ -1711,6 +1699,8 @@ struct amdgpu_vce {
         struct amdgpu_irq_src   irq;
         unsigned                harvest_config;
         struct amd_sched_entity entity;
+        uint32_t                srbm_soft_reset;
+        unsigned                num_rings;
 };
 
 /*
@@ -1728,9 +1718,14 @@ struct amdgpu_sdma_instance {
 
 struct amdgpu_sdma {
         struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
+#ifdef CONFIG_DRM_AMDGPU_SI
+        //SI DMA has a difference trap irq number for the second engine
+        struct amdgpu_irq_src   trap_irq_1;
+#endif
         struct amdgpu_irq_src   trap_irq;
         struct amdgpu_irq_src   illegal_inst_irq;
         int                     num_instances;
+        uint32_t                    srbm_soft_reset;
 };
 
 /*
@@ -1832,6 +1827,7 @@ struct amdgpu_asic_funcs {
         bool (*read_disabled_bios)(struct amdgpu_device *adev);
         bool (*read_bios_from_rom)(struct amdgpu_device *adev,
                                    u8 *bios, u32 length_bytes);
+        void (*detect_hw_virtualization) (struct amdgpu_device *adev);
         int (*read_register)(struct amdgpu_device *adev, u32 se_num,
                              u32 sh_num, u32 reg_offset, u32 *value);
         void (*set_vga_state)(struct amdgpu_device *adev, bool state);
@@ -1841,8 +1837,9 @@ struct amdgpu_asic_funcs {
         /* MM block clocks */
         int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
         int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
-        /* query virtual capabilities */
-        u32 (*get_virtual_caps)(struct amdgpu_device *adev);
+        /* static power management */
+        int (*get_pcie_lanes)(struct amdgpu_device *adev);
+        void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
 };
 
 /*
@@ -1935,16 +1932,6 @@ struct amdgpu_atcs {
 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
 
-
-/* GPU virtualization */
-#define AMDGPU_VIRT_CAPS_SRIOV_EN       (1 << 0)
-#define AMDGPU_VIRT_CAPS_IS_VF          (1 << 1)
-struct amdgpu_virtualization {
-        bool supports_sr_iov;
-        bool is_virtual;
-        u32 caps;
-};
-
 /*
  * Core structure, functions and helpers.
  */
@@ -1958,6 +1945,7 @@ struct amdgpu_ip_block_status {
         bool valid;
         bool sw;
         bool hw;
+        bool hang;
 };
 
 struct amdgpu_device {
@@ -2016,6 +2004,8 @@ struct amdgpu_device {
         spinlock_t pcie_idx_lock;
         amdgpu_rreg_t                   pcie_rreg;
         amdgpu_wreg_t                   pcie_wreg;
+        amdgpu_rreg_t                   pciep_rreg;
+        amdgpu_wreg_t                   pciep_wreg;
         /* protects concurrent UVD register access */
         spinlock_t uvd_ctx_idx_lock;
         amdgpu_rreg_t                   uvd_ctx_rreg;
@@ -2056,7 +2046,16 @@ struct amdgpu_device {
         atomic64_t                      num_evictions;
         atomic_t                        gpu_reset_counter;
 
+        /* data for buffer migration throttling */
+        struct {
+                spinlock_t              lock;
+                s64                     last_update_us;
+                s64                     accum_us; /* accumulated microseconds */
+                u32                     log2_max_MBps;
+        } mm_stats;
+
         /* display */
+        bool                            enable_virtual_display;
         struct amdgpu_mode_info         mode_info;
         struct work_struct              hotplug_work;
         struct amdgpu_irq_src           crtc_irq;
@@ -2119,6 +2118,14 @@ struct amdgpu_device {
         struct kfd_dev          *kfd;
 
         struct amdgpu_virtualization virtualization;
+
+        /* link all shadow bo */
+        struct list_head                shadow_list;
+        struct mutex                    shadow_list_lock;
+        /* link all gtt */
+        spinlock_t                      gtt_list_lock;
+        struct list_head                gtt_list;
+
 };
 
 bool amdgpu_device_is_px(struct drm_device *dev);
@@ -2151,6 +2158,8 @@ void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
+#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
+#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
@@ -2194,6 +2203,9 @@ void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
 #define REG_GET_FIELD(value, reg, field)                                \
         (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
 
+#define WREG32_FIELD(reg, field, val)   \
+        WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
+
 /*
  * BIOS helpers.
  */
@@ -2237,14 +2249,17 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
-#define amdgpu_asic_get_virtual_caps(adev) ((adev)->asic_funcs->get_virtual_caps((adev)))
+#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
+#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
+#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
+#define amdgpu_asic_detect_hw_virtualization(adev) (adev)->asic_funcs->detect_hw_virtualization((adev))
 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
-#define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
+#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
@@ -2259,9 +2274,13 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
+#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
+#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
+#define amdgpu_ring_get_emit_ib_size(r) (r)->funcs->get_emit_ib_size((r))
+#define amdgpu_ring_get_dma_frame_size(r) (r)->funcs->get_dma_frame_size((r))
 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
@@ -2293,6 +2312,11 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
 
+#define amdgpu_dpm_read_sensor(adev, idx, value) \
+        ((adev)->pp_enabled ? \
+                (adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), (value)) : \
+                -EINVAL)
+
 #define amdgpu_dpm_get_temperature(adev) \
         ((adev)->pp_enabled ?                                           \
               (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
@@ -2344,11 +2368,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
               (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
               (adev)->pm.funcs->powergate_vce((adev), (g)))
 
-#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
-        ((adev)->pp_enabled ?                                           \
-              (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
-              (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
-
 #define amdgpu_dpm_get_current_power_state(adev) \
         (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
 
@@ -2389,6 +2408,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 
 /* Common functions */
 int amdgpu_gpu_reset(struct amdgpu_device *adev);
+bool amdgpu_need_backup(struct amdgpu_device *adev);
 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
 bool amdgpu_card_posted(struct amdgpu_device *adev);
 void amdgpu_update_display_priority(struct amdgpu_device *adev);
@@ -2414,6 +2434,10 @@ uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
+u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev);
+int amdgpu_ttm_global_init(struct amdgpu_device *adev);
+int amdgpu_ttm_init(struct amdgpu_device *adev);
+void amdgpu_ttm_fini(struct amdgpu_device *adev);
 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
                                              const u32 *registers,
                                              const u32 array_size);
@@ -2425,11 +2449,13 @@ void amdgpu_register_atpx_handler(void);
 void amdgpu_unregister_atpx_handler(void);
 bool amdgpu_has_atpx_dgpu_power_cntl(void);
 bool amdgpu_is_atpx_hybrid(void);
+bool amdgpu_atpx_dgpu_req_power_for_displays(void);
 #else
 static inline void amdgpu_register_atpx_handler(void) {}
 static inline void amdgpu_unregister_atpx_handler(void) {}
 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
+static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
 #endif
 
 /*
@@ -2446,8 +2472,8 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
                                  struct drm_file *file_priv);
 void amdgpu_driver_preclose_kms(struct drm_device *dev,
                                 struct drm_file *file_priv);
-int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
-int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
+int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
+int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
@@ -2493,6 +2519,7 @@ static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
 struct amdgpu_bo_va_mapping *
 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
                        uint64_t addr, struct amdgpu_bo **bo);
+int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
 
 #include "amdgpu_object.h"
 #endif