aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/amdgpu/amdgpu.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h47
1 files changed, 4 insertions, 43 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 82edf95b7740..5e7770f9a415 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -87,6 +87,8 @@ extern int amdgpu_sched_jobs;
87extern int amdgpu_sched_hw_submission; 87extern int amdgpu_sched_hw_submission;
88extern int amdgpu_enable_semaphores; 88extern int amdgpu_enable_semaphores;
89extern int amdgpu_powerplay; 89extern int amdgpu_powerplay;
90extern unsigned amdgpu_pcie_gen_cap;
91extern unsigned amdgpu_pcie_lane_cap;
90 92
91#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 93#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
92#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 94#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
@@ -132,47 +134,6 @@ extern int amdgpu_powerplay;
132#define AMDGPU_RESET_VCE (1 << 13) 134#define AMDGPU_RESET_VCE (1 << 13)
133#define AMDGPU_RESET_VCE1 (1 << 14) 135#define AMDGPU_RESET_VCE1 (1 << 14)
134 136
135/* CG block flags */
136#define AMDGPU_CG_BLOCK_GFX (1 << 0)
137#define AMDGPU_CG_BLOCK_MC (1 << 1)
138#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
139#define AMDGPU_CG_BLOCK_UVD (1 << 3)
140#define AMDGPU_CG_BLOCK_VCE (1 << 4)
141#define AMDGPU_CG_BLOCK_HDP (1 << 5)
142#define AMDGPU_CG_BLOCK_BIF (1 << 6)
143
144/* CG flags */
145#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
146#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
147#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
148#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
149#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
150#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
151#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
152#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
153#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
154#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
155#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
156#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
157#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
158#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
159#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
160#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
161#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
162
163/* PG flags */
164#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
165#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
166#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
167#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
168#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
169#define AMDGPU_PG_SUPPORT_CP (1 << 5)
170#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
171#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
172#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
173#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
174#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
175
176/* GFX current status */ 137/* GFX current status */
177#define AMDGPU_GFX_NORMAL_MODE 0x00000000L 138#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
178#define AMDGPU_GFX_SAFE_MODE 0x00000001L 139#define AMDGPU_GFX_SAFE_MODE 0x00000001L
@@ -606,8 +567,6 @@ struct amdgpu_sa_manager {
606 uint32_t align; 567 uint32_t align;
607}; 568};
608 569
609struct amdgpu_sa_bo;
610
611/* sub-allocation buffer */ 570/* sub-allocation buffer */
612struct amdgpu_sa_bo { 571struct amdgpu_sa_bo {
613 struct list_head olist; 572 struct list_head olist;
@@ -2360,6 +2319,8 @@ bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2360int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2319int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2361 uint32_t flags); 2320 uint32_t flags);
2362bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 2321bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2322bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2323 unsigned long end);
2363bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 2324bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2364uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 2325uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2365 struct ttm_mem_reg *mem); 2326 struct ttm_mem_reg *mem);