diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu.h | 147 |
1 files changed, 1 insertions, 146 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index b6f5425ee52e..3ba97ea5e62c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h | |||
| @@ -54,6 +54,7 @@ | |||
| 54 | #include "amdgpu_ttm.h" | 54 | #include "amdgpu_ttm.h" |
| 55 | #include "amdgpu_gds.h" | 55 | #include "amdgpu_gds.h" |
| 56 | #include "amdgpu_sync.h" | 56 | #include "amdgpu_sync.h" |
| 57 | #include "amdgpu_ring.h" | ||
| 57 | #include "amd_powerplay.h" | 58 | #include "amd_powerplay.h" |
| 58 | #include "amdgpu_acp.h" | 59 | #include "amdgpu_acp.h" |
| 59 | 60 | ||
| @@ -109,12 +110,6 @@ extern int amdgpu_vram_page_split; | |||
| 109 | #define AMDGPUFB_CONN_LIMIT 4 | 110 | #define AMDGPUFB_CONN_LIMIT 4 |
| 110 | #define AMDGPU_BIOS_NUM_SCRATCH 8 | 111 | #define AMDGPU_BIOS_NUM_SCRATCH 8 |
| 111 | 112 | ||
| 112 | /* max number of rings */ | ||
| 113 | #define AMDGPU_MAX_RINGS 16 | ||
| 114 | #define AMDGPU_MAX_GFX_RINGS 1 | ||
| 115 | #define AMDGPU_MAX_COMPUTE_RINGS 8 | ||
| 116 | #define AMDGPU_MAX_VCE_RINGS 3 | ||
| 117 | |||
| 118 | /* max number of IP instances */ | 113 | /* max number of IP instances */ |
| 119 | #define AMDGPU_MAX_SDMA_INSTANCES 2 | 114 | #define AMDGPU_MAX_SDMA_INSTANCES 2 |
| 120 | 115 | ||
| @@ -155,7 +150,6 @@ extern int amdgpu_vram_page_split; | |||
| 155 | struct amdgpu_device; | 150 | struct amdgpu_device; |
| 156 | struct amdgpu_ib; | 151 | struct amdgpu_ib; |
| 157 | struct amdgpu_vm; | 152 | struct amdgpu_vm; |
| 158 | struct amdgpu_ring; | ||
| 159 | struct amdgpu_cs_parser; | 153 | struct amdgpu_cs_parser; |
| 160 | struct amdgpu_job; | 154 | struct amdgpu_job; |
| 161 | struct amdgpu_irq_src; | 155 | struct amdgpu_irq_src; |
| @@ -288,47 +282,6 @@ struct amdgpu_ih_funcs { | |||
| 288 | void (*set_rptr)(struct amdgpu_device *adev); | 282 | void (*set_rptr)(struct amdgpu_device *adev); |
| 289 | }; | 283 | }; |
| 290 | 284 | ||
| 291 | /* provided by hw blocks that expose a ring buffer for commands */ | ||
| 292 | struct amdgpu_ring_funcs { | ||
| 293 | /* ring read/write ptr handling */ | ||
| 294 | u32 (*get_rptr)(struct amdgpu_ring *ring); | ||
| 295 | u32 (*get_wptr)(struct amdgpu_ring *ring); | ||
| 296 | void (*set_wptr)(struct amdgpu_ring *ring); | ||
| 297 | /* validating and patching of IBs */ | ||
| 298 | int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); | ||
| 299 | /* command emit functions */ | ||
| 300 | void (*emit_ib)(struct amdgpu_ring *ring, | ||
| 301 | struct amdgpu_ib *ib, | ||
| 302 | unsigned vm_id, bool ctx_switch); | ||
| 303 | void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, | ||
| 304 | uint64_t seq, unsigned flags); | ||
| 305 | void (*emit_pipeline_sync)(struct amdgpu_ring *ring); | ||
| 306 | void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, | ||
| 307 | uint64_t pd_addr); | ||
| 308 | void (*emit_hdp_flush)(struct amdgpu_ring *ring); | ||
| 309 | void (*emit_hdp_invalidate)(struct amdgpu_ring *ring); | ||
| 310 | void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, | ||
| 311 | uint32_t gds_base, uint32_t gds_size, | ||
| 312 | uint32_t gws_base, uint32_t gws_size, | ||
| 313 | uint32_t oa_base, uint32_t oa_size); | ||
| 314 | /* testing functions */ | ||
| 315 | int (*test_ring)(struct amdgpu_ring *ring); | ||
| 316 | int (*test_ib)(struct amdgpu_ring *ring, long timeout); | ||
| 317 | /* insert NOP packets */ | ||
| 318 | void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); | ||
| 319 | /* pad the indirect buffer to the necessary number of dw */ | ||
| 320 | void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); | ||
| 321 | unsigned (*init_cond_exec)(struct amdgpu_ring *ring); | ||
| 322 | void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); | ||
| 323 | /* note usage for clock and power gating */ | ||
| 324 | void (*begin_use)(struct amdgpu_ring *ring); | ||
| 325 | void (*end_use)(struct amdgpu_ring *ring); | ||
| 326 | void (*emit_switch_buffer) (struct amdgpu_ring *ring); | ||
| 327 | void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); | ||
| 328 | unsigned (*get_emit_ib_size) (struct amdgpu_ring *ring); | ||
| 329 | unsigned (*get_dma_frame_size) (struct amdgpu_ring *ring); | ||
| 330 | }; | ||
| 331 | |||
| 332 | /* | 285 | /* |
| 333 | * BIOS. | 286 | * BIOS. |
| 334 | */ | 287 | */ |
| @@ -366,47 +319,6 @@ struct amdgpu_clock { | |||
| 366 | }; | 319 | }; |
| 367 | 320 | ||
| 368 | /* | 321 | /* |
| 369 | * Fences. | ||
| 370 | */ | ||
| 371 | struct amdgpu_fence_driver { | ||
| 372 | uint64_t gpu_addr; | ||
| 373 | volatile uint32_t *cpu_addr; | ||
| 374 | /* sync_seq is protected by ring emission lock */ | ||
| 375 | uint32_t sync_seq; | ||
| 376 | atomic_t last_seq; | ||
| 377 | bool initialized; | ||
| 378 | struct amdgpu_irq_src *irq_src; | ||
| 379 | unsigned irq_type; | ||
| 380 | struct timer_list fallback_timer; | ||
| 381 | unsigned num_fences_mask; | ||
| 382 | spinlock_t lock; | ||
| 383 | struct fence **fences; | ||
| 384 | }; | ||
| 385 | |||
| 386 | /* some special values for the owner field */ | ||
| 387 | #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) | ||
| 388 | #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) | ||
| 389 | |||
| 390 | #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) | ||
| 391 | #define AMDGPU_FENCE_FLAG_INT (1 << 1) | ||
| 392 | |||
| 393 | int amdgpu_fence_driver_init(struct amdgpu_device *adev); | ||
| 394 | void amdgpu_fence_driver_fini(struct amdgpu_device *adev); | ||
| 395 | void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); | ||
| 396 | |||
| 397 | int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, | ||
| 398 | unsigned num_hw_submission); | ||
| 399 | int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, | ||
| 400 | struct amdgpu_irq_src *irq_src, | ||
| 401 | unsigned irq_type); | ||
| 402 | void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); | ||
| 403 | void amdgpu_fence_driver_resume(struct amdgpu_device *adev); | ||
| 404 | int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence); | ||
| 405 | void amdgpu_fence_process(struct amdgpu_ring *ring); | ||
| 406 | int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); | ||
| 407 | unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); | ||
| 408 | |||
| 409 | /* | ||
| 410 | * BO. | 322 | * BO. |
| 411 | */ | 323 | */ |
| 412 | struct amdgpu_bo_list_entry { | 324 | struct amdgpu_bo_list_entry { |
| @@ -703,14 +615,6 @@ struct amdgpu_ib { | |||
| 703 | uint32_t flags; | 615 | uint32_t flags; |
| 704 | }; | 616 | }; |
| 705 | 617 | ||
| 706 | enum amdgpu_ring_type { | ||
| 707 | AMDGPU_RING_TYPE_GFX, | ||
| 708 | AMDGPU_RING_TYPE_COMPUTE, | ||
| 709 | AMDGPU_RING_TYPE_SDMA, | ||
| 710 | AMDGPU_RING_TYPE_UVD, | ||
| 711 | AMDGPU_RING_TYPE_VCE | ||
| 712 | }; | ||
| 713 | |||
| 714 | extern const struct amd_sched_backend_ops amdgpu_sched_ops; | 618 | extern const struct amd_sched_backend_ops amdgpu_sched_ops; |
| 715 | 619 | ||
| 716 | int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, | 620 | int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, |
| @@ -724,45 +628,6 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, | |||
| 724 | struct amd_sched_entity *entity, void *owner, | 628 | struct amd_sched_entity *entity, void *owner, |
| 725 | struct fence **f); | 629 | struct fence **f); |
| 726 | 630 | ||
| 727 | struct amdgpu_ring { | ||
| 728 | struct amdgpu_device *adev; | ||
| 729 | const struct amdgpu_ring_funcs *funcs; | ||
| 730 | struct amdgpu_fence_driver fence_drv; | ||
| 731 | struct amd_gpu_scheduler sched; | ||
| 732 | |||
| 733 | struct amdgpu_bo *ring_obj; | ||
| 734 | volatile uint32_t *ring; | ||
| 735 | unsigned rptr_offs; | ||
| 736 | unsigned wptr; | ||
| 737 | unsigned wptr_old; | ||
| 738 | unsigned ring_size; | ||
| 739 | unsigned max_dw; | ||
| 740 | int count_dw; | ||
| 741 | uint64_t gpu_addr; | ||
| 742 | uint32_t align_mask; | ||
| 743 | uint32_t ptr_mask; | ||
| 744 | bool ready; | ||
| 745 | u32 nop; | ||
| 746 | u32 idx; | ||
| 747 | u32 me; | ||
| 748 | u32 pipe; | ||
| 749 | u32 queue; | ||
| 750 | struct amdgpu_bo *mqd_obj; | ||
| 751 | u32 doorbell_index; | ||
| 752 | bool use_doorbell; | ||
| 753 | unsigned wptr_offs; | ||
| 754 | unsigned fence_offs; | ||
| 755 | uint64_t current_ctx; | ||
| 756 | enum amdgpu_ring_type type; | ||
| 757 | char name[16]; | ||
| 758 | unsigned cond_exe_offs; | ||
| 759 | u64 cond_exe_gpu_addr; | ||
| 760 | volatile u32 *cond_exe_cpu_addr; | ||
| 761 | #if defined(CONFIG_DEBUG_FS) | ||
| 762 | struct dentry *ent; | ||
| 763 | #endif | ||
| 764 | }; | ||
| 765 | |||
| 766 | /* | 631 | /* |
| 767 | * VM | 632 | * VM |
| 768 | */ | 633 | */ |
| @@ -1168,16 +1033,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, | |||
| 1168 | int amdgpu_ib_pool_init(struct amdgpu_device *adev); | 1033 | int amdgpu_ib_pool_init(struct amdgpu_device *adev); |
| 1169 | void amdgpu_ib_pool_fini(struct amdgpu_device *adev); | 1034 | void amdgpu_ib_pool_fini(struct amdgpu_device *adev); |
| 1170 | int amdgpu_ib_ring_tests(struct amdgpu_device *adev); | 1035 | int amdgpu_ib_ring_tests(struct amdgpu_device *adev); |
| 1171 | int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); | ||
| 1172 | void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); | ||
| 1173 | void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); | ||
| 1174 | void amdgpu_ring_commit(struct amdgpu_ring *ring); | ||
| 1175 | void amdgpu_ring_undo(struct amdgpu_ring *ring); | ||
| 1176 | int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, | ||
| 1177 | unsigned ring_size, u32 nop, u32 align_mask, | ||
| 1178 | struct amdgpu_irq_src *irq_src, unsigned irq_type, | ||
| 1179 | enum amdgpu_ring_type ring_type); | ||
| 1180 | void amdgpu_ring_fini(struct amdgpu_ring *ring); | ||
| 1181 | 1036 | ||
| 1182 | /* | 1037 | /* |
| 1183 | * CS. | 1038 | * CS. |
