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path: root/drivers/fpga/zynq-fpga.c
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Diffstat (limited to 'drivers/fpga/zynq-fpga.c')
-rw-r--r--drivers/fpga/zynq-fpga.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
index c2fb4120bd62..249682e92502 100644
--- a/drivers/fpga/zynq-fpga.c
+++ b/drivers/fpga/zynq-fpga.c
@@ -175,7 +175,8 @@ static irqreturn_t zynq_fpga_isr(int irq, void *data)
175 return IRQ_HANDLED; 175 return IRQ_HANDLED;
176} 176}
177 177
178static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags, 178static int zynq_fpga_ops_write_init(struct fpga_manager *mgr,
179 struct fpga_image_info *info,
179 const char *buf, size_t count) 180 const char *buf, size_t count)
180{ 181{
181 struct zynq_fpga_priv *priv; 182 struct zynq_fpga_priv *priv;
@@ -189,7 +190,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
189 return err; 190 return err;
190 191
191 /* don't globally reset PL if we're doing partial reconfig */ 192 /* don't globally reset PL if we're doing partial reconfig */
192 if (!(flags & FPGA_MGR_PARTIAL_RECONFIG)) { 193 if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
193 /* assert AXI interface resets */ 194 /* assert AXI interface resets */
194 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, 195 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,
195 FPGA_RST_ALL_MASK); 196 FPGA_RST_ALL_MASK);
@@ -343,7 +344,8 @@ out_free:
343 return err; 344 return err;
344} 345}
345 346
346static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, u32 flags) 347static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr,
348 struct fpga_image_info *info)
347{ 349{
348 struct zynq_fpga_priv *priv = mgr->priv; 350 struct zynq_fpga_priv *priv = mgr->priv;
349 int err; 351 int err;
@@ -364,7 +366,7 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, u32 flags)
364 return err; 366 return err;
365 367
366 /* for the partial reconfig case we didn't touch the level shifters */ 368 /* for the partial reconfig case we didn't touch the level shifters */
367 if (!(flags & FPGA_MGR_PARTIAL_RECONFIG)) { 369 if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
368 /* enable level shifters from PL to PS */ 370 /* enable level shifters from PL to PS */
369 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, 371 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
370 LVL_SHFTR_ENABLE_PL_TO_PS); 372 LVL_SHFTR_ENABLE_PL_TO_PS);