7 files changed, 45 insertions, 11 deletions

diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index 4e73ed5cab58..4bb130cd0062 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -158,12 +158,16 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
 
                 writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask,
                                               reg_data->div_core_shift) |
-                       HIWORD_UPDATE(1, 1, reg_data->mux_core_shift),
+                       HIWORD_UPDATE(reg_data->mux_core_alt,
+                                     reg_data->mux_core_mask,
+                                     reg_data->mux_core_shift),
                        cpuclk->reg_base + reg_data->core_reg);
         } else {
                 /* select alternate parent */
-                writel(HIWORD_UPDATE(1, 1, reg_data->mux_core_shift),
-                        cpuclk->reg_base + reg_data->core_reg);
+                writel(HIWORD_UPDATE(reg_data->mux_core_alt,
+                                     reg_data->mux_core_mask,
+                                     reg_data->mux_core_shift),
+                       cpuclk->reg_base + reg_data->core_reg);
         }
 
         spin_unlock_irqrestore(cpuclk->lock, flags);
@@ -198,7 +202,9 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
 
         writel(HIWORD_UPDATE(0, reg_data->div_core_mask,
                                 reg_data->div_core_shift) |
-               HIWORD_UPDATE(0, 1, reg_data->mux_core_shift),
+               HIWORD_UPDATE(reg_data->mux_core_main,
+                                reg_data->mux_core_mask,
+                                reg_data->mux_core_shift),
                cpuclk->reg_base + reg_data->core_reg);
 
         if (ndata->old_rate > ndata->new_rate)
@@ -252,7 +258,7 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
                 return ERR_PTR(-ENOMEM);
 
         init.name = name;
-        init.parent_names = &parent_names[0];
+        init.parent_names = &parent_names[reg_data->mux_core_main];
         init.num_parents = 1;
         init.ops = &rockchip_cpuclk_ops;
 
@@ -270,10 +276,10 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
         cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb;
         cpuclk->hw.init = &init;
 
-        cpuclk->alt_parent = __clk_lookup(parent_names[1]);
+        cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]);
         if (!cpuclk->alt_parent) {
-                pr_err("%s: could not lookup alternate parent\n",
-                       __func__);
+                pr_err("%s: could not lookup alternate parent: (%d)\n",
+                       __func__, reg_data->mux_core_alt);
                 ret = -EINVAL;
                 goto free_cpuclk;
         }
@@ -285,10 +291,11 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
                 goto free_cpuclk;
         }
 
-        clk = __clk_lookup(parent_names[0]);
+        clk = __clk_lookup(parent_names[reg_data->mux_core_main]);
         if (!clk) {
-                pr_err("%s: could not lookup parent clock %s\n",
-                       __func__, parent_names[0]);
+                pr_err("%s: could not lookup parent clock: (%d) %s\n",
+                       __func__, reg_data->mux_core_main,
+                       parent_names[reg_data->mux_core_main]);
                 ret = -EINVAL;
                 goto free_alt_parent;
         }
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 7cdb2d61f3e0..f9cbba0eac36 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -113,7 +113,10 @@ static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = {
         .core_reg = RK2928_CLKSEL_CON(0),
         .div_core_shift = 0,
         .div_core_mask = 0x1f,
+        .mux_core_alt = 1,
+        .mux_core_main = 0,
         .mux_core_shift = 7,
+        .mux_core_mask = 0x1,
 };
 
 PNAME(mux_pll_p)                = { "xin24m", "xin24m" };
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index 40bab3901491..e832403a0f9f 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -155,7 +155,10 @@ static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = {
         .core_reg = RK2928_CLKSEL_CON(0),
         .div_core_shift = 0,
         .div_core_mask = 0x1f,
+        .mux_core_alt = 1,
+        .mux_core_main = 0,
         .mux_core_shift = 8,
+        .mux_core_mask = 0x1,
 };
 
 #define RK3188_DIV_ACLK_CORE_MASK       0x7
@@ -191,7 +194,10 @@ static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = {
         .core_reg = RK2928_CLKSEL_CON(0),
         .div_core_shift = 9,
         .div_core_mask = 0x1f,
+        .mux_core_alt = 1,
+        .mux_core_main = 0,
         .mux_core_shift = 8,
+        .mux_core_mask = 0x1,
 };
 
 PNAME(mux_pll_p)                = { "xin24m", "xin32k" };
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index 7702d2855e9c..4b4137e85125 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -111,7 +111,10 @@ static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
         .core_reg = RK2928_CLKSEL_CON(0),
         .div_core_shift = 0,
         .div_core_mask = 0x1f,
+        .mux_core_alt = 1,
+        .mux_core_main = 0,
         .mux_core_shift = 6,
+        .mux_core_mask = 0x1,
 };
 
 PNAME(mux_pll_p)                = { "clk_24m", "xin24m" };
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 3cb72163a512..00faf3f9b179 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -165,7 +165,10 @@ static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
         .core_reg = RK3288_CLKSEL_CON(0),
         .div_core_shift = 8,
         .div_core_mask = 0x1f,
+        .mux_core_alt = 1,
+        .mux_core_main = 0,
         .mux_core_shift = 15,
+        .mux_core_mask = 0x1,
 };
 
 PNAME(mux_pll_p)                = { "xin24m", "xin32k" };
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index a2bb12200465..c26ff4a36dcd 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -165,14 +165,20 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = {
         .core_reg = RK3368_CLKSEL_CON(0),
         .div_core_shift = 0,
         .div_core_mask = 0x1f,
+        .mux_core_alt = 1,
+        .mux_core_main = 0,
         .mux_core_shift = 7,
+        .mux_core_mask = 0x1,
 };
 
 static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
         .core_reg = RK3368_CLKSEL_CON(2),
         .div_core_shift = 0,
+        .mux_core_alt = 1,
+        .mux_core_main = 0,
         .div_core_mask = 0x1f,
         .mux_core_shift = 7,
+        .mux_core_mask = 0x1,
 };
 
 #define RK3368_DIV_ACLKM_MASK           0x1f
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index f3da205073ee..4133bfc8f827 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -217,14 +217,20 @@ struct rockchip_cpuclk_rate_table {
  * @core_reg:           register offset of the core settings register
  * @div_core_shift:     core divider offset used to divide the pll value
  * @div_core_mask:      core divider mask
+ * @mux_core_alt:       mux value to select alternate parent
+ * @mux_core_main:      mux value to select main parent of core
  * @mux_core_shift:     offset of the core multiplexer
+ * @mux_core_mask:      core multiplexer mask
  */
 struct rockchip_cpuclk_reg_data {
         int             core_reg;
         u8              div_core_shift;
         u32             div_core_mask;
         int             mux_core_reg;
+        u8              mux_core_alt;
+        u8              mux_core_main;
         u8              mux_core_shift;
+        u32             mux_core_mask;
 };
 
 struct clk *rockchip_clk_register_cpuclk(const char *name,